{{ImportantMessage|text='''For BELK 3.0.2 or older, the boot process was based on the FSBL+second-stage bootloader (U-Boot) combination. From BELK 4.0.0 on, the boot process is based on the first-stage bootloader (U-Boot SPL)+second-stage bootloader (U-Boot) combination.'''
}}
==Kit content==
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!Component
!Notes
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|style="text-align: center;" | [[File:Bora5-small.jpg|60px]]|[[:Category:Bora|BORABora]] SOM<br>CPU(p/n DBRF5110C1R)*SoC: Xilinx Zynx 7000XC7Z030 (866Mhz, Speed "-3", Tj 0-100°C)*SDRAM: 1 GB DDR3*NOR: bootable SPI flash 16 MB*NAND: 1GB (SLC)|Please * For more details, please refer to the[[Hardware Manual (Bora) | Bora Hardware Manual]]* By default, ARM cores frequency is set to 667 MHz and the [[Creating and building example Vivado project (BELK/BXELK)|example Vivado project]] is implemented for a "-1" device. This choice makes the software released with the kit compatible with possible variants based on different SoM models. In this regard, see also the [[#Order codes|order codes section]].