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{{Applies To Bora}}
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[[File:Boraevb-02.png|400px650px|frameless|border]]
==Block Diagram==
The following picture shows BoraEVB block diagram:
[[File:Boraevb-bd.png|thumb|center|600px|BoraEVB block diagram]]
== Features ==
* 10/100/1000 Ethernet #0 (PS)
* 10/100/1000 Ethernet #1 (Routed through EMIO)
* 1x USB 2.0 OTG(MicroAB connector)* 1x Serial port (RS232DB9)
* 1x MicroSD
* External DDR3 SDRAM bank
* XADC
** Some signals of Bank 35 can be configured as XADC signals. For this reason they can be routed alternatively to 2.54mm-pitch connectors, instead of DDR3 memory.
* JTAG port
* Trace port
* Socket for [[Wireless_Module_(DWM) | DWM Wireless Module]]
* Digilent Pmod™ Compatible expansion connectors
* Headers for external for NAND flash and SPI NOR flash
* 2.54mm-pitch pin-strip connectors for Bora PS and PL configurable peripherals (MIO and EMIO interfaces, GPIOs, custom IPs, ..)
* Jumpers for voltage selection of the PL banks
* +12V power connector
== Known limitations ==
Board version CS040713A has the following limitations:
{| class="wikitable"
|-
!Issue
!Description
|-
| ETH0 interface
| Mistake in the connection of the center tap pins. They should be separated from one another and connected through separate 0.1μF common-mode capacitors to ground (for further details (eg: connection and selection of the magnetics), please refer to the Micrel KSZ9031RNX datasheet).
|-
|External DDR3 bank
|The DDR3 SDRAM bank is not supported in BELK 2.0.0
|-
|ETH1 interface
|The additional Gigabit Ethernet interface (ETH1) is not supported in BELK 2.0.0
|-
|}
== Connectors pinout ==
=== J1 ,J2 and J3 ===The pinout of the J1 connector of the BoraEVB is the same of the J1 connector on BORA module === , J2 ===The pinout of the J2 connector of the BoraEVB is the same of the J2 connector on BORA module === and J3 ===The pinout of the J3 connector connectors of the BoraEVB Bora EVB is the same of the J3 connector [[Pinout (Bora)|counterpart connectors on BORA module]].
=== Power supply - J7 ===
|2 || DGND || Ground || -
|-
|}
=== Boot mode selection - S5 ===
S5 is a dip-switch for the boot mode selection. The following table reports the available options and the related configurations:
{| class="wikitable"
|-
! !! S5.1 !! S5.2 !! S5.3 !! S5.4 !! S5.5 !! S5.6 !! S5.7 !! S5.8
|-
| SPI-NOR || OFF || ON || OFF || ON || ON || ON || ON || OFF
|-
| SD-card || OFF || ON || OFF || ON || ON || OFF || ON || OFF
|-
| NAND || OFF || ON || OFF || ON || ON || OFF || ON || ON
|-
| JTAG || OFF || ON || OFF || ON || ON || ON || ON || ON
|}
=== WatchDog Settings - S1, S2 and S3 ===
S1, S2 and S3 are dip-switch to override the default startup delay and timeout of the Bora module watchdog.
For more details please refer to [[Watchdog_(Bora)|this page]].
{| class="wikitable"
|-
! !! S1.1 !! S1.2
|-
| WD_SET0 SOM default || OFF || OFF
|-
| WD_SET0 = '1' || ON || OFF
|-
| WD_SET0 = '0' || OFF || ON
|}
{| class="wikitable"
|-
! !! S2.1 !! S2.2
|-
| WD_SET1 SOM default || OFF || OFF
|-
| WD_SET1 = '1' || ON || OFF
|-
| WD_SET1 = '0' || OFF || ON
|}
{| class="wikitable"
|-
! !! S3.1 !! S3.2
|-
| WD_SET2 SOM default || OFF || OFF
|-
| WD_SET2 = '1' || ON || OFF
|-
| WD_SET2 = '0' || OFF || ON
|}
=== POWER GOOD signals selector - J10 ===
J10 is a 8-pin 4x2x2.54 pitch vertical headerused for the selection - through jumpers - of the POWER GOOD options. The following table reports the pinout of the connector:
{| class="wikitable"
|-
=== BANK35, BANK13 VDDIO selector - J11 ===
J11 is a 8-pin 4x2x2.54 pitch vertical headerused for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector:
{| class="wikitable"
The available configurations are:
# Jumper on 1-2 -> supply VDDIO_BANK35 with 3.3V('''requirerd when EVBB DDR3 device is used''')# Jumper on 3-4 -> ('''Not Available''') supply VDDIO_BANK35 with EVB_VDDQ_1V5 ('''requirerd when EVBB DDR3 device is used''')
# Jumper on 5-6 -> supply VDDIO_BANK13 with 3.3V
# Jumper on 7-8 -> supply VDDIO_BANK35 with EVB_VDDIO_BANK13 ('''requirerd when TRACE is used''')
The following rules must be observed:
* Because of a hardware limitation, VDDIO_BANK35 '''must be configured for 3.3V power supply (Jumper on 1-2)'''.
* The configuration 1. (Jumper on 1-2) excludes 2. (Jumper on 3-4) (and viceversa)
* The configuration 3. (Jumper on 5-6) excludes 4. (Jumper on 7-8) (and viceversa)
The DEFAULT configuration is:
* Jumper on 31-4 2 ('''please note that this jumper must not be removed''')
* Jumper on 5-6
!Notes
|-
|1, 112, 125,<br>6, 16|| DGND || Ground || -|-|3 || CLK125_NDO|| - || -|-|4 || ETH1_CLK125_NDO || - || -
|-
|2 7 || NAND_BUSYETH_MDC || - || -
|-
|3 8 || ZYNQ_NAND_CLE ETH1_MDC || - || -
|-
|4 9 || NAND_IO3 ETH_MDIO || - || -
|-
|5 10 || NAND_IO4 ETH1_MDIO || - || -
|-
|6 11 || NAND_IO5 ETH_INTn || - || -
|-
|7 12 || NAND_IO6 ETH1_INTn || - || -
|-
|8 13 || NAND_IO7 PS_MIO51_501 || - || -
|-
|9 14 || CONN_SPI_RSTn ETH1_RESETn || - || -
|-
|10 15 || MEM_WPn PS_MIO50_501 || - || -
|-
|}
==== SPI,NAND - JP19 ====
JP19 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
|-
!Notes
|-
|1, 211, 5,<br>6, 1612|| DGND || Ground || -
|-
|3 2 || CLK125_NDONAND_BUSY|| - || -
|-
|4 3 || ETH1_CLK125_NDO ZYNQ_NAND_CLE || - || -
|-
|7 4 || ETH_MDC NAND_IO3 || - || -
|-
|8 5 || ETH1_MDC NAND_IO4 || - || -
|-
|9 6 || ETH_MDIO NAND_IO5 || - || -
|-
|10 7 || ETH1_MDIO NAND_IO6 || - || -
|-
|11 8 ||ETH_INTn NAND_IO7 || - || -
|-
|12 9 || ETH1_INTn CONN_SPI_RSTn || - || -
|-
|13 10 || PS_MIO51_501 || - || -|-|14 || ETH1_RESETn || - || -|-|15 || PS_MIO50_501 MEM_WPn || - || -
|-
|}
=== PMODs Digilent Pmod™ Compatible headers ===
Please note that:
* PMOD interface Digilent Pmod™ Interface Specification - defined by Digilent Inc. - allows to quickly connect several pre-built I/O modules to PL:
** http://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,401&Cat=9&CFID=3145471&CFTOKEN=69407812
** http://www.maximintegrated.com/products/evkits/fpga-modules/
* Signals used to implement LVDS LCD interface can alternatively routed to PMOD Digilent Pmod™ Compatible compatible connector
==== PMOD Digilent Pmod™ Compatible - JP17 ====
JP17 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
==== PMOD Digilent Pmod™ Compatible - JP23 ====
JP23 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
|-
|}
==Schematics==
{{ImportantMessage|text=The following list details the schematic version/serial number association.
For more details about the serial number composition, please refer to [[Product_serial_number|this page]].
The following serial numbers were manufactured according to the schematics version 2.4.0:
*S-EVBBxyz 00E5
*S-EVBBxyz 00DF
*From S-EVBBxyz 00FC on (i.e. 00FC, 00FD, etc.)
The following serial numbers were manufactured according to the schematics version 2.2.0:
*From S-EVBBxyz 00AC to S-EVBBxyz 00E4
*From S-EVBBxyz 00E6 to 00DE
*From S-EVBBxyz 00E0 to 00FB.}}
=== Release 2.4.0 ===* ORCAD: [[mirror:bora/hw/BoraEVB/boraevb-2.4.0-BELK-dsn.zip|boraevb-2.4.0-BELK-dsn.zip]]* PDF : [[mirror:bora/hw/BoraEVB/boraevb_S.EVBB0000I1R_2.4.0_color.pdf|boraevb_S.EVBB0000I1R_2.4.0.pdf]]=== Release 2.2.1 ===* ORCAD: Coming soon[[mirror:bora/hw/BoraEVB/boraevb-2.2.1-BELK-dsn.zip|boraevb-2.2.1-BELK-dsn.zip]]* PDF : Coming soon[[mirror:bora/hw/BoraEVB/boraevb_S.EVBB0000I1R_2.2.1_color.pdf|boraevb_S.EVBB0000I1R_2.2.1.pdf]]
==BOM==
{{ImportantMessage|text=The following list details the BOM version/serial number association. For more details about the serial number composition, please refer to [[Product_serial_number|this page]]. The following serial numbers were manufactured according to the BOM version 2.4.0:*S-EVBBxyz 00E5*S-EVBBxyz 00DF*From S-EVBBxyz 00FC on (i.e. 00FC, 00FD, etc.).The following serial numbers were manufactured according to the BOM version 2.2.0:*From S-EVBBxyz 00AC to S-EVBBxyz 00E4*From S-EVBBxyz 00E6 to 00DE*From S-EVBBxyz 00E0 to 00FB.}}=== Release 2.4.0 ===* BoraEVB: Coming soon[[mirror:bora/hw/BoraEVB/BORAEVB_S.EVBB0000I1R.2.4.0.CSV.zip|BORAEVB_S.EVBB0000I1R.2.4.0.CSV.zip]]=== Release 2.2.0 ===* BoraEVB: https://www.dave.eu/system/files/area-riservata/boraevb_BOM_S.EVBB0000I1R.2.2.0.CSV_.zip
==Layout==
* Coming soonhttps://www.dave.eu/system/files/area-riservata/boraevb-CS040713A_assembly_view.pdf
==Mechanical==
* DXF: coming soonhttps://www.dave.eu/system/files/area-riservata/boraevb_2D_CS040713A.zip* IDF (3D): coming soonhttps://www.dave.eu/system/files/area-riservata/boraevb_3D_CS040713A.zip
