3,260
edits
Changes
m
== Functionalities overview ==
The following list details the devices and functionalities implemented:
* Gigabit Ethernet port (Ethernet #0)
** This is port is implemented by a RJ45 connector - incorporating magnetics - that is connected to Bora's PHY.
* Gigabit Ethernet port (Ethernet #1)
** This port in implemented by a RJ45 connector - incorporating magnetics - coupled with Micrel KSZ9031 PHY. This, in turn, ic connected to PL's bank 34 via RGMII interface. This is an example of EMIO routing showing how to route PS's MAC signals via PL subsystem. Thus, in case PL is not properly configured, this second Ethernet port will not work.
* USBOTG
** This is port is implemented by a MicroAB connector that is connected to Bora's PHY.
* UART1
** This is port is implemented by a DB9 connector plus RS232 xceiver that is connected to PS MIO signals.
* Micro SD
** This is port is implemented by a micro SD connector plus 1.8V/3.3V level shifter, connected to PS signals. Level shifter is required because MIO[49:48] are 1.8V.
* CAN connector
** This is directly connected to Bora's transceiver.
** This 2.5mm-pitch header is compatible with commonly available IDC-10/DB9 flat cables.
* LVDS LCD interface
** This interface shows how to implement a differential connection to an LCD screen.
** As known, Zynq does not implement an LCD controller, however this can be integrated in FPGA fabric as shown by this example: https://wiki.analog.com/resources/tools-software/linux-drivers/platforms/zynq.
* PMOD compliant connector
** Signals used to implement LVDS LCD interface can alternatively routed to PMOD compatible connector. PMOD interface - defined by Digilent Inc. - allows to quickly connect several pre-built I/O modules to PL:
*** http://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,401&Cat=9&CFID=3145471&CFTOKEN=69407812
*** http://www.maximintegrated.com/products/evkits/fpga-modules/
* Three devices are connected to I2C0 bus (this is level shifted from 1.8V to 3.3V):
** Silicon Labs Si571 programmable clock generator: this clock si connected to PL to allow the user to easily experiment his/her own peripherals and IPs on FPGA
** resistive touch screen controller for LCD screen
** consumption monitor: this is connected to shunt resistor put in series on Bora power rail, allowing to measure SoM consumption
* State-of-the-art programmable MEMS clock generator (Silicon Labs Si504): this is an alternative clock source to allow the user to easily experiment his/her own peripherals and IPs on FPGA
* DDR3 memory bank
** This memory bank is connected to bank 35 - powered @ 1.5V - that is optimized at PCB level to interface such devices.
** This bank is expressly available for peripherals and/or IPs implemented in FPGA fabric. This solution '''permits these blocks to work without impacting on Bora's DDR3 memory bandwidth'''. To access this bank, MIG (Memory Interface Generator) controller has to be implemented on PL.
*** MIG controller requires an external 200 MHz clock source.
* XADC
** Some signals of Bank 35 can be configured as XADC signals. For this reason they can be routed alternatively to 2.54mm-pitch connector, instead of DDR3 memory.
* DWM (WiFi/Bluetooth)
** DWM is a plug-in module integrating WiFi and Bluetooth connectivity (http://wiki.dave.eu/index.php/Wireless_Module_%28DWM%29)
** DMW is connected to bank 34.
* JTAG port
** This port is available as two different mechanical connectors:
*** 2.00mm-pitch 7x2 header (Xilinx standard)
*** 2.54mm-pitch 10x2 header (ARM standard): http://www2.lauterbach.com/pdf/arm_app_jtag.pdf
*** This port is connected to Zynq's native JTAG signals. Please note that Zynq's internal JTAG chain supports differents configurations, depending on bootstrap signals. In case split mode is selected, CPU JTAG can be routed separately via PL. For more details please refer to Zynq Technical Reference Manual.
* Trace port
** From the physical standpoint, trace port exploits the '''advanced routing of bank 13 signals implemented on Bora''', combined with the '''possibility to select the I/O voltage of bank itself'''. Connector is compatible with ETMv1/ETMv3 specification. Please refer to http://www.lauterbach.com/frames.html?adetmmipi60.html for more details.
** JTAG and trace signals are EMIO routed to I/O of bank 13
** About tracing, several differents schemes are possible, depending of debug requirements. For example one might be interested in CPU-only tracing via PTM or fabric-only tracing via FTM. For more details please refer to Zynq TRM and these links:
*** http://www.lauterbach.com/frames.html?icretm.html
*** http://www.lauterbach.com/frames.html?icretb.html
*** http://www.lauterbach.com/frames.html?autofocus.html
*** http://www.xilinx.com/products/intellectual-property/1-24W427.htm.
=== JTAG ARM - J18===
J18 is a 20-pin 10x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
|-
!Pin#
!Pin name
!Function
!Notes
|-
|1 || 3.3V|| - || -
|-
|2 || 3.3V|| - || -
|-
|3, 11, 17, 19 || N.C.|| - || -
|-
|4, 6 ,8 ,10 ,12,<br>14, 16, 18, 20|| DGND|| - || -
|-
|5 || JTAG_TDI|| - || -
|-
|7 || JTAG_TMS|| - || -
|-
|9 || JTAG_TCK|| - || -
|-
|13 || JTAG_TDO|| - || -
|-
|15 || JTAG_TRSTn|| - || -
|-
|}
no edit summary
* 1x MicroSD
* External DDR3 SDRAM bank
** This memory bank is connected to bank 35 - powered @ 1.5V - that is optimized at PCB level to interface such devices.
** This bank is expressly available for peripherals and/or IPs implemented in FPGA fabric. This solution '''permits these blocks to work without impacting on Bora's DDR3 memory bandwidth'''. To access this bank, MIG (Memory Interface Generator) controller has to be implemented on PL.
*** MIG controller requires an external 200 MHz clock source.
* State-of-the-art programmable MEMS clock generator (Silicon Labs Si504): this is an alternative clock source to allow the user to easily experiment his/her own peripherals and IPs on FPGA
* XADC
** Some signals of Bank 35 can be configured as XADC signals. For this reason they can be routed alternatively to 2.54mm-pitch connectors, instead of DDR3 memory.
* +12V power connector
* JTAG
== Known limitations ==
== Connectors pinout ==
|}
=== Ethernet port #0 (ETH0 ) - J8 ===
J8 is a RJ45 Gigabit Ethernet connector - incorporating magnetics - connected to the Bora integrated ethernet controller and PHY.
{| class="wikitable"
|}
=== Ethernet port #1 (ETH1 ) - J9 === J9 is a RJ45 Gigabit Ethernet connector - incorporating magnetics - connected to KSZ9031RNX Micrel KSZ9031 PHY (Gigabit Ethernet Transceiver). This, in turn, is connected to PL's bank 34 via RGMII interface. This is an example of EMIO routing showing how to route PS's MAC signals via PL subsystem. Please note that, in case PL is not properly configured, this second Ethernet port will not work.
{| class="wikitable"
* Jumper on 5-6
=== JTAG === JTAG port is available as two different mechanical connectors:* 2.00mm-pitch 7x2 header (Xilinx standard)* 2.54mm-pitch 10x2 header (ARM standard): http://www2.lauterbach.com/pdf/arm_app_jtag.pdf* This port is connected to Zynq's native JTAG signals. Please note that Zynq's internal JTAG chain supports differents configurations, depending on bootstrap signals. In case split mode is selected, CPU JTAG can be routed separately via PL. For more details please refer to Zynq Technical Reference Manual. ==== JTAG XILINX - J13 ====
J13 is a 14-pin 7x2x2 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
|-
|}
==== JTAG ARM - J18 ====
J18 is a 20-pin 10x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
|-
!Pin#
!Pin name
!Function
!Notes
|-
|1 || 3.3V|| - || -
|-
|2 || 3.3V|| - || -
|-
|3, 11, 17, 19 || N.C.|| - || -
|-
|4, 6 ,8 ,10 ,12,<br>14, 16, 18, 20|| DGND|| - || -
|-
|5 || JTAG_TDI|| - || -
|-
|7 || JTAG_TMS|| - || -
|-
|9 || JTAG_TCK|| - || -
|-
|13 || JTAG_TDO|| - || -
|-
|15 || JTAG_TRSTn|| - || -
|-
|}
=== UART1 - J17 ===
J17 is a standard DB9 connector for that routes the signals coming from the RS232 two-wires UART0 port. The following table reports transceiver that is connected to the pinout PS MIO signals of the connector:UART1 port.
{| class="wikitable"
|}
=== USB OTG - J19 ===
J19 is a standard USB MICRO AB connector. It is connected to the Bora USB 2.0 OTG peripheral. The following table reports the pinout of the connector:
=== MicroSD - J21 ===
J21 is a microSD memory card connector. It is connected to the Bora SOM through a bidirectional 1.8V/3.3V voltage-level translator mounted on the EVBBBoraEVB. Level shifter is required because MIO signals are 1.8V. The following table reports the pinout of the connector:
{| class="wikitable"
=== Trace Port - J22 ===
J22 is a QSH–060–01–L–D–A 0,50 mm Hi-speed socket. It is connected to the Debug Trace Port.From the physical standpoint, trace port exploits the '''advanced routing of bank 13 signals implemented on Bora''', combined with the '''possibility to select the I/O voltage of bank itself'''. Connector is compatible with ETMv1/ETMv3 specification. Please refer to http://www.lauterbach.com/frames.html?adetmmipi60.html for more details. Please note that: * JTAG and trace signals are EMIO routed to I/O of bank 13* About tracing, several differents schemes are possible, depending of debug requirements. For example one might be interested in CPU-only tracing via PTM or fabric-only tracing via FTM. For more details please refer to Zynq TRM and these links:** http://www.lauterbach.com/frames.html?icretm.html** http://www.lauterbach.com/frames.html?icretb.html** http://www.lauterbach.com/frames.html?autofocus.html** http://www.xilinx.com/products/intellectual-property/1-24W427.htm. The following table reports the pinout of the connector:
{| class="wikitable"
=== CAN - J24 ===
J24 is a 10-pin 5x2x2.54mm pitch vertical header. This connector allows the connection directly connected to Bora SoM's transceiver for the internal CAN bus interface of the BORA SoM. This 2.5mm-pitch header is compatible with commonly available IDC-10/DB9 flat cables. The following table reports the pinout of the connector:
{| class="wikitable"
=== LVDS - J26 ===
J26 is a vertical double row straight 20-pin 1.25mm pitch header. This socket allows the interface shows how to implement a differential connection of a LVDSto an LCD screen. As known, Zynq does not implement an LCD controller, however this can be integrated in FPGA fabric as shown by this example: https://wiki.analog.com/resources/tools-software/linux-LCD panel to the EVBdrivers/platforms/zynq. The following table reports the pinout of the connector:
{| class="wikitable"
|-
|}
Please note that:
* Signals used to implement LVDS LCD interface can alternatively routed to PMOD compatible connector
* PMOD interface - defined by Digilent Inc. - allows to quickly connect several pre-built I/O modules to PL:
** http://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,401&Cat=9&CFID=3145471&CFTOKEN=69407812
** http://www.maximintegrated.com/products/evkits/fpga-modules/
==== Ethernet GPIO - JP18 ====
|-
|}
Please note that:
* Three devices are connected to I2C0 bus (this is level shifted from 1.8V to 3.3V):
** Silicon Labs Si571 programmable clock generator: this clock si connected to PL to allow the user to easily experiment his/her own peripherals and IPs on FPGA
** resistive touch screen controller for LCD screen
** consumption monitor: this is connected to shunt resistor put in series on Bora power rail, allowing to measure SoM consumption
==== FPGA, WatchDog, RTC, RST - JP22 ====
