Changes

BoraEVB is a carrier board designed to host [[:Category:Bora|Bora]].

==Block Diagram==

[[File:Boraevb-bd.png|thumb|center|600px|BoraEVB block diagram]]

== Features ==

== Connectors pinout ==

=== J1,J2 and J3 ===

The pinout of the J1, J2 and J3 connectors of the Bora EVB is the same of the [[Pinout (Bora)|counterpart connectors on BORA module]].

=== Power supply - J7 ===

|-

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=== Boot mode selection - S5 ===

| JTAG || OFF || ON || OFF || ON || ON || ON || ON || ON

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=== WatchDog Settings - S1, S2 and S3 ===

S1, S2 and S3 are dip-switch to override the default startup delay and timeout of the Bora module watchdog.

| WD_SET2 = '0' || OFF || ON

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=== Ethernet port #0 (ETH0) - J8 ===

|-

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=== Ethernet port #1 (ETH1) - J9 ===

|-

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=== JTAG ===

|-

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=== UART1 - J17 ===

|-

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=== USB OTG - J19 ===

|-

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=== MicroSD - J21 ===

|-

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=== Trace Port - J22 ===

|-

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=== DWM (DAVE Wifi/BT module) socket - J23 ===

|-

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=== CAN - J24 ===

J24 is a 10-pin 5x2x2.54mm pitch vertical header directly connected to Bora SoM's transceiver for the CAN interface. This 2.5mm-pitch header is compatible with commonly available IDC-10/DB9 flat cables. The following table reports the pinout of the connector:

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=== Touch screen - J25===

J25 is a ZIF 4-pin 1.0mm pitch connector that connects the touchscreen drive lines to the touch screen controller on the BoraEVB. The following table reports the pinout of the connector:

|-

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=== LVDS - J26 ===

J26 is a vertical double row straight 20-pin 1.25mm pitch header. This interface shows how to implement a differential connection to an LCD screen. As known, Zynq does not implement an LCD controller, however this can be integrated in FPGA fabric as shown by this example: https://wiki.analog.com/resources/tools-software/linux-drivers/platforms/zynq. The following table reports the pinout of the connector:

|-

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=== Pin strip connectors ===

** resistive touch screen controller for LCD screen

** consumption monitor: this is connected to shunt resistor put in series on Bora power rail, allowing to measure SoM consumption

==== FPGA, WatchDog, RTC, RST - JP22 ====

JP22 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:

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=== Digilent Pmod™ Compatible headers ===

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==Schematics==

==Mechanical==