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==Introduction==
[[File:Boraevb-02.png|650px|frameless|border]]
==Block Diagram==
The following picture shows BoraEVB block diagram:
[[File:Boraevb-bd.png|thumb|center|600px|BoraEVB block diagram]] <section end=Block Diagram/>
== Features ==
* Trace port
* Socket for [[Wireless_Module_(DWM) | DWM Wireless Module]]
* PMOD Digilent Pmod™ Compatible expansion connectors
* Headers for external for NAND flash and SPI NOR flash
* 2.54mm-pitch pin-strip connectors for Bora PS and PL configurable peripherals (MIO and EMIO interfaces, GPIOs, custom IPs, ..)
Board version CS040713A has the following limitations:
== Connectors pinout ==
<section begin=== J1 CPU/>===The pinout of the J1 connector of the BoraEVB is the same of the J1 connector on BORA module === ,J2 and J3 ===The pinout of the J1, J2 connector and J3 connectors of the BoraEVB Bora EVB is the same of the J2 connector [[Pinout (Bora)|counterpart connectors on BORA module]].<section end=CPU/><section begin=== J3 ===The pinout of the J3 connector of the BoraEVB is the same of the J3 connector on BORA modulePower Supply/>
=== Power supply - J7 ===
|-
|}
==== POWER GOOD signals selector - J10 ====
J10 is a 8-pin 4x2x2.54 pitch vertical header used for the selection - through jumpers - of the POWER GOOD options. The following table reports the pinout of the connector:
{| class="wikitable"
|-
!Pin#
!Pin name
!Function
!Notes
|-
|1 || BOARD_PGOOD|| - || -
|-
|2, 4 || 3.3V_SOM|| - || -
|-
|3 || 1.5V_POWER_GOOD || - || -
|-
|5 || VREF_POWER_GOOD || - || -
|-
|6, 8 || 3.3V_SBY || - || -
|-
|7 || 1.8V_POWER_GOOD || - || -
|-
|}
The available configurations are:
* No jumpers mounted (DEFAULT)
* Jumper on 1-2 -> supply BOARD_PGOOD with 3.3V_SOM
* Jumper on 3-4 -> supply 1.5V_POWER_GOOD with 3.3V_SOM
* Jumper on 5-6 -> supply 1.5V_VREF_POWER_GOOD with 3.3V_SBY
* Jumper on 7-8 -> supply 1.8V_VREF_POWER_GOOD with 3.3V_SBY
==== BANK35, BANK13 VDDIO selector - J11 ====
J11 is a 8-pin 4x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector:
{| class="wikitable"
|-
!Pin#
!Pin name
!Function
!Notes
|-
|1, 5 || 3.3V|| - || -
|-
|2, 4 || VDDIO_BANK35|| - || -
|-
|3 || EVB_VDDQ_1V5 || - || -
|-
|6, 8 || VDDIO_BANK13|| - || -
|-
|7 || EVB_VDDIO_BANK13|| - || -
|-
|}
The available configurations are:
# Jumper on 1-2 -> supply VDDIO_BANK35 with 3.3V ('''requirerd when EVBB DDR3 device is used''')
# Jumper on 3-4 -> ('''Not Available''') supply VDDIO_BANK35 with EVB_VDDQ_1V5 ('''requirerd when EVBB DDR3 device is used''')
# Jumper on 5-6 -> supply VDDIO_BANK13 with 3.3V
# Jumper on 7-8 -> supply VDDIO_BANK35 with EVB_VDDIO_BANK13 ('''requirerd when TRACE is used''')
The following rules must be observed:
* Because of a hardware limitation, VDDIO_BANK35 '''must be configured for 3.3V power supply (Jumper on 1-2)'''.
* The configuration 1. (Jumper on 1-2) excludes 2. (Jumper on 3-4) (and viceversa)
* The configuration 3. (Jumper on 5-6) excludes 4. (Jumper on 7-8) (and viceversa)
The DEFAULT configuration is:
* Jumper on 1-2 ('''please note that this jumper must not be removed''')
* Jumper on 5-6
<section end=Power Supply/>
<section begin=Reset button/>
=== Reset button - S6 ===
S6 is the hardware reset button connected to the MRSTn signal (J2.16 SOM connector)
<section end=Reset button/>
<section begin=Boot Configurations/>
=== Boot mode selection - S5 ===
| JTAG || OFF || ON || OFF || ON || ON || ON || ON || ON
|}
<section end=Boot Configurations/>
<section begin=Watchdog/>
=== WatchDog Settings - S1, S2 and S3 ===
S1, S2 and S3 are dip-switch to override the default startup delay and timeout of the Bora module watchdog.
For more details please refer to [[Watchdog_(Bora)|this page]].
{| class="wikitable"
|-
! !! S1.1 !! S1.2
|-
| WD_SET0 SOM default || OFF || OFF
|-
| WD_SET0 = '1' || ON || OFF
|-
| WD_SET0 = '0' || OFF || ON
|}
{| class="wikitable"
|-
! !! S2.1 !! S2.2
|-
| WD_SET1 SOM default || OFF || OFF
|-
| WD_SET1 = '1' || ON || OFF
|-
| WD_SET1 = '0' || OFF || ON
|}
{| class="wikitable"
|-
! !! S3.1 !! S3.2
|-
| WD_SET2 SOM default || OFF || OFF
|-
| WD_SET2 = '1' || ON || OFF
|-
| WD_SET2 = '0' || OFF || ON
|}
<section end=Watchdog/>
<section begin=Ethernet0/>
=== Ethernet port #0 (ETH0) - J8 ===
|-
|}
<section end=Ethernet0/><section begin=Ethernet1/>
=== Ethernet port #1 (ETH1) - J9 ===
|-
|}
=== JTAG ===
|-
|}
<section end=JTAG/>
<section begin=Console/>
=== UART1 - J17 ===
|-
|}
<section end=Console/>
<section begin=USB OTG/>
=== USB OTG - J19 ===
|-
|}
<section end=USB OTG/><section begin=micro SD/>
=== MicroSD - J21 ===
|-
|}
<section end=micro SD/><section begin=TRACE/>
=== Trace Port - J22 ===
|-
|}
<section end=TRACE/>
<section begin=DWM/>
=== DWM (DAVE Wifi/BT module) socket - J23 ===
|-
|}
<section end=DWM/><section begin=CAN/>
=== CAN - J24 ===
J24 is a 10-pin 5x2x2.54mm pitch vertical header directly connected to Bora SoM's transceiver for the CAN interface. This 2.5mm-pitch header is compatible with commonly available IDC-10/DB9 flat cables. The following table reports the pinout of the connector:
|-
|}
<section end=CAN/><section begin=Touchscreen/>
=== Touch screen - J25===
J25 is a ZIF 4-pin 1.0mm pitch connector that connects the touchscreen drive lines to the touch screen controller on the BoraEVB. The following table reports the pinout of the connector:
|-
|}
<section end=Touchscreen/><section begin=LVDS/>
=== LVDS - J26 ===
J26 is a vertical double row straight 20-pin 1.25mm pitch header. This interface shows how to implement a differential connection to an LCD screen. As known, Zynq does not implement an LCD controller, however this can be integrated in FPGA fabric as shown by this example: https://wiki.analog.com/resources/tools-software/linux-drivers/platforms/zynq. The following table reports the pinout of the connector:
|-
|}
<section end=LVDS/><section begin=PinStrip/>
=== Pin strip connectors ===
!Notes
|-
|1, 112, 125,<br>6, 16|| DGND || Ground || -|-|3 || CLK125_NDO|| - || -|-|4 || ETH1_CLK125_NDO || - || -
|-
|2 7 || NAND_BUSYETH_MDC || - || -
|-
|3 8 || ZYNQ_NAND_CLE ETH1_MDC || - || -
|-
|4 9 || NAND_IO3 ETH_MDIO || - || -
|-
|5 10 || NAND_IO4 ETH1_MDIO || - || -
|-
|6 11 || NAND_IO5 ETH_INTn || - || -
|-
|7 12 || NAND_IO6 ETH1_INTn || - || -
|-
|8 13 || NAND_IO7 PS_MIO51_501 || - || -
|-
|9 14 || CONN_SPI_RSTn ETH1_RESETn || - || -
|-
|10 15 || MEM_WPn PS_MIO50_501 || - || -
|-
|}
==== SPI,NAND - JP19 ====
JP19 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
|-
!Notes
|-
|1, 211, 5,<br>6, 1612|| DGND || Ground || -
|-
|3 2 || CLK125_NDONAND_BUSY|| - || -
|-
|4 3 || ETH1_CLK125_NDO ZYNQ_NAND_CLE || - || -
|-
|7 4 || ETH_MDC NAND_IO3 || - || -
|-
|8 5 || ETH1_MDC NAND_IO4 || - || -
|-
|9 6 || ETH_MDIO NAND_IO5 || - || -
|-
|10 7 || ETH1_MDIO NAND_IO6 || - || -
|-
|11 8 ||ETH_INTn NAND_IO7 || - || -
|-
|12 9 || ETH1_INTn CONN_SPI_RSTn || - || -
|-
|13 10 || PS_MIO51_501 || - || -|-|14 || ETH1_RESETn || - || -|-|15 || PS_MIO50_501 MEM_WPn || - || -
|-
|}
** resistive touch screen controller for LCD screen
** consumption monitor: this is connected to shunt resistor put in series on Bora power rail, allowing to measure SoM consumption
<section begin=RTC/>
==== FPGA, WatchDog, RTC, RST - JP22 ====
JP22 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
|-
|}
<section end=RTC/><section end=PinStrip/><section begin=PMOD/>
=== Digilent Pmod™ Compatible headers ===
|-
|}
<section end=PMOD/>
<section begin=Schematics/>
==Schematics==
{{ImportantMessage|text=The following list details the schematic version/serial number association.
For more details about the serial number composition, please refer to [[Product_serial_number|this page]].
The following serial numbers were manufactured according to the schematics version 2.4.0:
*S-EVBBxyz 00E5
*S-EVBBxyz 00DF
*From S-EVBBxyz 00FC on (i.e. 00FC, 00FD, etc.)
The following serial numbers were manufactured according to the schematics version 2.2.0:
*From S-EVBBxyz 00AC to S-EVBBxyz 00E4
*From S-EVBBxyz 00E6 to 00DE
*From S-EVBBxyz 00E0 to 00FB.}}
{{ImportantMessage|text=U14 DDR3 chip can be populated alternatively with Micron MT41K64M16JT-15E or ISSI IS43TR16256BL-125KBLI}}
==== Release 2.4.0 ====* ORCAD: http[https://www.dave.eu/systemlinks/filesp/areaB6VMD9szrL0MSPlz boraevb-riservata2.4.0-BELK-dsn.zip]* PDF : [https://www.dave.eu/links/p/SKDqnaHRBVWwA0MV boraevb_S.EVBB0000I1R_2.4.0.pdf]==== Release 2.2.1 ====* ORCAD: [https://www.dave.eu/links/p/orPSBGIESKeGcy38 boraevb-2.02.31-BELK-dsn.zip]* PDF : http[https://www.dave.eu/systemlinks/files/area-riservatap/KTjZOWQBT1t66Umw boraevb_S.EVBB0000I1R_2.02.3_color1.pdf]===BOM==={{ImportantMessage|text=The following list details the BOM version/serial number association.
The following serial numbers were manufactured according to the BOM version 2.4.0:*S-EVBBxyz 00E5*S-EVBBxyz 00DF*From S-EVBBxyz 00FC on (i.e. 00FC, 00FD, etc.).The following serial numbers were manufactured according to the BOM version 2.2.0:*From S-EVBBxyz 00AC to S-EVBBxyz 00E4*From S-EVBBxyz 00E6 to 00DE*From S-EVBBxyz 00E0 to 00FB.}}==== Release 2.4.0 ====* BoraEVB: [https://www.dave.eu/links/p/ylcKMeQpKzgScnkz BORAEVB_S.EVBB0000I1R.2.4.0.CSV.zip]==== Release 2.2.0 ==Layout==* httpBoraEVB: [https://www.dave.eu/systemlinks/filesp/areahbJ8HyApBiva1qgl boraevb-riservataBOM_S.EVBB0000I1R.2.2.1.CSV_.zip]===Layout===* [https://www.dave.eu/links/p/AUBnjq9DoTC2gget boraevb-CS040713A_assembly_viewCS040713A_all_view.pdf]<section end=Schematics/><section begin=Mechanicals/>
==Mechanical==
* DXF: http[https://www.dave.eu/systemlinks/filesp/area-riservata/boraevb_2D_CS040713Andf9AsBgti3TnGRF boraevb_CS040713A.dxf.zip]* IDF (3D): http[https://www.dave.eu/systemlinks/filesp/area-riservatal2wRddTIcC3RSZb8 boraevb_CS040713A.emn]<section end=Mechanicals/boraevb_3D_CS040713A.zip>
