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[[File:Boraevb-02.png|650px|frameless|border]]
BoraEVB is a carrier board designed to host [[File:Category:Bora|400px|frameless|borderBora]].
<section begin==Introduction==BoraEVB is a carrier board designed to host [[Bora SOM|Bora system-on-module]].Block Diagram/>
==Block Diagram==
The following picture shows BoraBoraEVB block diagram: [[File:Boraevb-EVB bd.png|thumb|center|600px|BoraEVB block diagram: ]]
== Features ==
* 10/100/1000 Ethernet#0 (PS)* 10/100/1000 Ethernet #1 (Routed through EMIO)* 1x USB 2.0 OTG(MicroAB connector)* 1x Serial port (RS232DB9)
* 1x MicroSD
* External DDR3 SDRAM bank
** This memory bank is connected to bank 35 - powered @ 1.5V - that is optimized at PCB level to interface such devices.
** This bank is expressly available for peripherals and/or IPs implemented in FPGA fabric. This solution '''permits these blocks to work without impacting on Bora's DDR3 memory bandwidth'''. To access this bank, MIG (Memory Interface Generator) controller has to be implemented on PL.
*** MIG controller requires an external 200 MHz clock source.
* State-of-the-art programmable MEMS clock generator (Silicon Labs Si504): this is an alternative clock source to allow the user to easily experiment his/her own peripherals and IPs on FPGA
* XADC
** Some signals of Bank 35 can be configured as XADC signals. For this reason they can be routed alternatively to 2.54mm-pitch connectorconnectors, instead of DDR3 memory.* DWM (WiFi/Bluetooth)** DWM is a plug-in module integrating WiFi and Bluetooth connectivity (http://wiki.dave.eu/index.php/Wireless_Module_%28DWM%29)** DMW is connected to bank 34.
* JTAG port
* Trace port
** From the physical standpoint, trace port exploits the '''advanced routing of bank 13 signals implemented on Bora''', combined with the '''possibility to select the I/O voltage of bank itself'''. Connector is compatible with ETMv1/ETMv3 specification. Please refer to http://www.lauterbach.com/frames.html?adetmmipi60.html Socket for more details.[[Wireless_Module_(DWM) | DWM Wireless Module]]*Digilent Pmod™ Compatible expansion connectors* JTAG Headers for external for NAND flash and trace signals are EMIO routed to I/O of bank 13SPI NOR flash** About tracing, several differents schemes are possible, depending of debug requirements2. For example one might be interested in CPU54mm-only tracing via PTM or fabricpitch pin-only tracing via FTM. For more details please refer to Zynq TRM strip connectors for Bora PS and PL configurable peripherals (MIO and these links:*** http://wwwEMIO interfaces, GPIOs, custom IPs, .lauterbach.com/frames.html?icretm.html)*** http://www.lauterbach.com/frames.html?icretb.htmlJumpers for voltage selection of the PL banks*** http://www.lauterbach.com/frames.html?autofocus.html*** http://www.xilinx.com/products/intellectual-property/1-24W427.htm.+12V power connector
== Connectors pinout Known limitations ==
{| class=== J2 ==="wikitable" |-!Issue!Description|-| ETH0 interfaceThe pinout | Mistake in the connection of the J2 connector center tap pins. They should be separated from one another and connected through separate 0.1μF common-mode capacitors to ground (for further details (eg: connection and selection of the BoraEVB magnetics), please refer to the Micrel KSZ9031RNX datasheet).|-|External DDR3 bank |The DDR3 SDRAM bank is the same of the J2 connector on BORA modulenot supported in BELK 2.0.0|-|ETH1 interface|The additional Gigabit Ethernet interface (ETH1) is not supported in BELK 2.0.0|-|}
=== J3 =Connectors pinout ==The pinout of the J3 connector of the BoraEVB is the same of the J3 connector on BORA module
<section begin=CPU/>
=== J1,J2 and J3 ===
The pinout of the J1, J2 and J3 connectors of the Bora EVB is the same of the [[Pinout (Bora)|counterpart connectors on BORA module]].
<section end=CPU/>
<section begin=Power Supply/>
=== Power supply - J7 ===
|}
=== Ethernet port ETH0 = POWER GOOD signals selector - J8 J10 ====J10 is a 8-pin 4x2x2.54 pitch vertical header used for the selection - through jumpers - of the POWER GOOD options. The following table reports the pinout of the connector:{| class="wikitable" |-!Pin# !Pin name!Function!Notes|-|1 || BOARD_PGOOD|| - || -|-|2, 4 || 3.3V_SOM|| - || -|-|3 || 1.5V_POWER_GOOD || - || -|-|5 || VREF_POWER_GOOD || - || -|-|6, 8 || 3.3V_SBY || - || -|-|7 || 1.8V_POWER_GOOD || - || -|-|} The available configurations are:* No jumpers mounted (DEFAULT)* Jumper on 1-2 -> supply BOARD_PGOOD with 3.3V_SOM* Jumper on 3-4 -> supply 1.5V_POWER_GOOD with 3.3V_SOM* Jumper on 5-6 -> supply 1.5V_VREF_POWER_GOOD with 3.3V_SBY* Jumper on 7-8 -> supply 1.8V_VREF_POWER_GOOD with 3.3V_SBY
==== BANK35, BANK13 VDDIO selector - J11 ====J11 is a 8-pin 4x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector: {| class="wikitable" |-!Pin# !Pin name!Function!Notes|-|1, 5 || 3.3V|| - || -|-|2, 4 || VDDIO_BANK35|| - || -|-|3 || EVB_VDDQ_1V5 || - || -|-|6, 8 || VDDIO_BANK13|| - || -|-|7 || EVB_VDDIO_BANK13|| - || -|-|} The available configurations are:# Jumper on 1-2 -> supply VDDIO_BANK35 with 3.3V ('''requirerd when EVBB DDR3 device is used''')# Jumper on 3-4 -> ('''Not Available''') supply VDDIO_BANK35 with EVB_VDDQ_1V5 ('''requirerd when EVBB DDR3 device is used''')# Jumper on 5-6 -> supply VDDIO_BANK13 with 3.3V# Jumper on 7-8 -> supply VDDIO_BANK35 with EVB_VDDIO_BANK13 ('''requirerd when TRACE is used''') The following rules must be observed:* Because of a hardware limitation, VDDIO_BANK35 '''must be configured for 3.3V power supply (Jumper on 1-2)'''.* The configuration 1. (Jumper on 1-2) excludes 2. (Jumper on 3-4) (and viceversa)* The configuration 3. (Jumper on 5-6) excludes 4. (Jumper on 7-8) (and viceversa) The DEFAULT configuration is:* Jumper on 1-2 ('''please note that this jumper must not be removed''')* Jumper on 5-6<section end=Power Supply/><section begin=Reset button/>=== Reset button - S6 === S6 is the hardware reset button connected to the MRSTn signal (J2.16 SOM connector)<section end=Reset button/> <section begin=Boot Configurations/> === Boot mode selection - S5 === S5 is a dip-switch for the boot mode selection. The following table reports the available options and the related configurations: {| class="wikitable"|-! !! S5.1 !! S5.2 !! S5.3 !! S5.4 !! S5.5 !! S5.6 !! S5.7 !! S5.8|-| SPI-NOR || OFF || ON || OFF || ON || ON || ON || ON || OFF|-| SD-card || OFF || ON || OFF || ON || ON || OFF || ON || OFF|-| NAND || OFF || ON || OFF || ON || ON || OFF || ON || ON|-| JTAG || OFF || ON || OFF || ON || ON || ON || ON || ON|}<section end=Boot Configurations/><section begin=Watchdog/>=== WatchDog Settings - S1, S2 and S3 ===S1, S2 and S3 are dip-switch to override the default startup delay and timeout of the Bora module watchdog.For more details please refer to [[Watchdog_(Bora)|this page]]. {| class="wikitable"|-! !! S1.1 !! S1.2|-| WD_SET0 SOM default || OFF || OFF|-| WD_SET0 = '1' || ON || OFF|-| WD_SET0 = '0' || OFF || ON|} {| class="wikitable"|-! !! S2.1 !! S2.2|-| WD_SET1 SOM default || OFF || OFF|-| WD_SET1 = '1' || ON || OFF|-| WD_SET1 = '0' || OFF || ON|} {| class="wikitable"|-! !! S3.1 !! S3.2|-| WD_SET2 SOM default || OFF || OFF|-| WD_SET2 = '1' || ON || OFF|-| WD_SET2 = '0' || OFF || ON|}<section end=Watchdog/><section begin=Ethernet0/>=== Ethernet port #0 (ETH0) - J8 === J8 is a RJ45 Gigabit Ethernet connector - incorporating magnetics - connected to the Bora integrated ethernet controller and PHY.
{| class="wikitable"
|-
|}
<section end=Ethernet0/>
<section begin=Ethernet1/>
=== Ethernet port #1 (ETH1) - J9 ===
{| class="wikitable"
|-
|}
<section end=Ethernet1/>
<section begin=JTAG/>
=== JTAG ===
JTAG port is available as two different mechanical connectors:* 2.00mm-pitch 7x2 header (Xilinx standard)* 2.54mm-pitch 10x2 header (ARM standard): http://www2.lauterbach.com/pdf/arm_app_jtag.pdf* This port is connected to Zynq's native JTAG signals. Please note that Zynq's internal JTAG chain supports differents configurations, depending on bootstrap signals. In case split mode is selected, CPU JTAG can be routed separately via PL. For more details please refer to Zynq Technical Reference Manual. === POWER GOOD signals selector = JTAG XILINX - J10 J13 ====J10 J13 is a 814-pin 4x2x2.54 7x2x2 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
|-
!Notes
|-
|1 , 3, 5, 7, 9, 11, 13 || BOARD_PGOODDGND|| - || -
|-
|2, 4 || 3.3V_SOM3V|| - || -
|-
|3 4 || 1.5V_POWER_GOOD JTAG_TMS|| - || -
|-
|5 6 || VREF_POWER_GOOD JTAG_TCK|| - || -
|-
|6, 8 || 3.3V_SBY JTAG_TDO|| - || -
|-
|7 10 || 1.8V_POWER_GOOD JTAG_TDI|| - || -
|-
|} The available configurations are:* No jumpers mounted (DEFAULT)* Jumper on 1-2 -> supply BOARD_PGOOD with 312 || N.3V_SOM* Jumper on 3-4 -> supply 1C.5V_POWER_GOOD with 3.3V_SOM* Jumper on 5|| -6 -> supply 1.5V_VREF_POWER_GOOD with 3.3V_SBY* Jumper on 7-8 || -> supply 1.8V_VREF_POWER_GOOD with 3.3V_SBY === BANK35, BANK13 VDDIO selector - J11 ===J11 is a 8-pin 4x2x2.54 pitch vertical header. The following table reports the pinout of the connector: {| class="wikitable"
|-
|-
|}
{| class="wikitable"
|-
!Notes
|-
|1, 3, 5, 7, 9, 11, 13 || DGND3.3V|| - || -
|-
|2 || 3.3V|| - || -
|-
|3, 11, 17, 19 || N.C.|| - || -|-|4 , 6 ,8 ,10 ,12,<br>14, 16, 18, 20|| JTAG_TMSDGND|| - || -
|-
|6 5 || JTAG_TCKJTAG_TDI|| - || -
|-
|8 7 || JTAG_TDOJTAG_TMS|| - || -
|-
|10 9 || JTAG_TDIJTAG_TCK|| - || -
|-
|12 13 || N.C.JTAG_TDO|| - || -
|-
|14 15 || JTAG_TRSTn|| - || -
|-
|}
<section end=JTAG/>
<section begin=Console/>
=== UART1 - J17 ===
J17 is a standard DB9 connector for that routes the signals coming from the RS232 two-wires UART0 port. The following table reports transceiver that is connected to the pinout PS MIO signals of the connector:UART1 port.
{| class="wikitable"
|-
|}
<section end=Console/>
<section begin=USB OTG/>=== JTAG ARM USB OTG - J18=J19 ==J18 is a 20-pin 10x2x2.54 pitch vertical header. The following table reports the pinout of the connector:{| class="wikitable" |-!Pin# !Pin name!Function!Notes|-|1 || 3.3V|| - || -|-|2 || 3.3V|| - || -|-|3, 11, 17, 19 || N.C.|| - || -|-|4, 6 ,8 ,10 ,12,<br>14, 16, 18, 20|| DGND|| - || -|-|5 || JTAG_TDI|| - || -|-|7 || JTAG_TMS|| - || -|-|9 || JTAG_TCK|| - || -|-|13 || JTAG_TDO|| - || -|-|15 || JTAG_TRSTn|| - || -|-|}
J19 is a standard USB MICRO AB connector. It is connected to the Bora USB 2.0 OTG peripheral. The following table reports the pinout of the connector:
|-
|}
<section end=USB OTG/>
<section begin=micro SD/>
=== MicroSD - J21 ===
{| class="wikitable"
|-
|}
<section end=micro SD/>
<section begin=TRACE/>
=== Trace Port - J22 ===
{| class="wikitable"
|-
|}
<section end=TRACE/>
<section begin=DWM/>
=== DWM (DAVE Wifi/BT module) socket - J23 ===
J23 is a 52991-0308 connector type(30 pins, vertical, 0.50mm picth). This socket connects the [[Wireless_Module_(DWM) | DWM extension module Wireless Module]] (optional) to the EVBBoraEVB. The following table reports the pinout of the connector:
{| class="wikitable"
|-
|}
<section end=DWM/><section begin=CAN/>
=== CAN - J24 ===
J24 is a 10-pin 5x2x2.54mm pitch vertical header. This connector allows the connection directly connected to Bora SoM's transceiver for the internal CAN bus interface of the BORA SoM. This 2.5mm-pitch header is compatible with commonly available IDC-10/DB9 flat cables. The following table reports the pinout of the connector:
{| class="wikitable"
|-
|}
<section end=CAN/><section begin=Touchscreen/>
=== Touch screen - J25===
J25 is a ZIF 4-pin 1.0mm pitch connector that connects the touchscreen drive lines to the touch screen controller on the EVBBoraEVB. The following table reports the pinout of the connector:
{| class="wikitable"
|-
|}
<section end=Touchscreen/><section begin=LVDS/>
=== LVDS - J26 ===
J26 is a vertical double row straight 20-pin 1.25mm pitch header. This socket allows the interface shows how to implement a differential connection of a LVDSto an LCD screen. As known, Zynq does not implement an LCD controller, however this can be integrated in FPGA fabric as shown by this example: https://wiki.analog.com/resources/tools-software/linux-LCD panel to the EVBdrivers/platforms/zynq. The following table reports the pinout of the connector:
{| class="wikitable"
|-
|}
<section end=LVDS/><section begin=PinStrip/>
=== Pin strip connectors ===
|}
==== PMOD Ethernet GPIO - JP17 JP18 ====JP17 JP18 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
|-
!Notes
|-
|1 , 2, 5,<br>6, 16||PMOD_A0 DGND || Ground || -|-|3 || CLK125_NDO|| - || -|-|4 || ETH1_CLK125_NDO || - || -
|-
|2 7 ||PMOD_A4 ETH_MDC || - || -
|-
|3 8 ||PMOD_A1 ETH1_MDC || - || -
|-
|4 9 ||PMOD_A5 ETH_MDIO || - || -
|-
|5 10 ||PMOD_A2 ETH1_MDIO || - || -
|-
|6 11 ||PMOD_A6 ETH_INTn || - || -
|-
|7 12 ||PMOD_A3 ETH1_INTn || - || -
|-
|8 13 ||PMOD_A7 PS_MIO51_501 || - || -
|-
|9, 10 14 ||DGND ETH1_RESETn ||Ground - || -
|-
|11, 12 15 ||3.3V PS_MIO50_501 || - || -
|-
|}
==== Ethernet GPIO SPI,NAND - JP18 JP19 ====JP18 JP19 is a 1216-pin 6x2x28x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
|-
|10 || MEM_WPn || - || -
|-
|}
|}
Please note that:
* Three devices are connected to I2C0 bus (this is level shifted from 1.8V to 3.3V):
** Silicon Labs Si571 programmable clock generator: this clock si connected to PL to allow the user to easily experiment his/her own peripherals and IPs on FPGA
** resistive touch screen controller for LCD screen
** consumption monitor: this is connected to shunt resistor put in series on Bora power rail, allowing to measure SoM consumption
<section begin=RTC/>
==== FPGA, WatchDog, RTC, RST - JP22 ====
JP22 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
|-
|}
<section end=RTC/>
<section end=PinStrip/>
<section begin=PMOD/>
=== Digilent Pmod™ Compatible headers ===
Please note that: * Digilent Pmod™ Interface Specification - defined by Digilent Inc. - allows to quickly connect several pre-built I/O modules to PL:** http://www.digilentinc.com/Products/Catalog.cfm?NavPath=2,401&Cat=9&CFID=3145471&CFTOKEN= PMOD 69407812** http://www.maximintegrated.com/products/evkits/fpga-modules/* Signals used to implement LVDS LCD interface can alternatively routed to Digilent Pmod™ Compatible compatible connector ==== Digilent Pmod™ Compatible - JP17 ==== JP17 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector: {| class="wikitable" |-!Pin# !Pin name!Function!Notes|-|1 ||PMOD_A0 || || -|-|2 ||PMOD_A4 || || -|-|3 ||PMOD_A1 || || -|-|4 ||PMOD_A5 || || -|-|5 ||PMOD_A2 || || -|-|6 ||PMOD_A6 || || -|-|7 ||PMOD_A3 || || -|-|8 ||PMOD_A7 || || -|-|9, 10 ||DGND ||Ground || -|-|11, 12 ||3.3V || || -|-|} ==== Digilent Pmod™ Compatible - JP23 ====
JP23 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
{| class="wikitable"
|-
|}
<section end=PMOD/>
<section begin=Schematics/>
==Schematics==
{{ImportantMessage|text=The following list details the schematic version/serial number association.
For more details about the serial number composition, please refer to [[Product_serial_number|this page]].
The following serial numbers were manufactured according to the schematics version 2.4.0:
*S-EVBBxyz 00E5
*S-EVBBxyz 00DF
*From S-EVBBxyz 00FC on (i.e. 00FC, 00FD, etc.)
The following serial numbers were manufactured according to the schematics version 2.2.0:
*From S-EVBBxyz 00AC to S-EVBBxyz 00E4
*From S-EVBBxyz 00E6 to 00DE
*From S-EVBBxyz 00E0 to 00FB.}}
{{ImportantMessage|text=U14 DDR3 chip can be populated alternatively with Micron MT41K64M16JT-15E or ISSI IS43TR16256BL-125KBLI}}
==== Release 2.4.0 ====* ORCAD: [https://www.dave.eu/links/p/B6VMD9szrL0MSPlz boraevb-2.4.0-BELK-dsn.zip]* PDF : [https://www.dave.eu/links/p/SKDqnaHRBVWwA0MV boraevb_S.EVBB0000I1R_2.4.0.pdf]==== Release 2.2.1 ====* ORCAD: Coming soon[https://www.dave.eu/links/p/orPSBGIESKeGcy38 boraevb-2.2.1-BELK-dsn.zip]* PDF : Coming soon[https://www.dave.eu/links/p/KTjZOWQBT1t66Umw boraevb_S.EVBB0000I1R_2.2.1.pdf]===BOM==={{ImportantMessage|text=The following list details the BOM version/serial number association.
The following serial numbers were manufactured according to the BOM version 2.4.0:*S-EVBBxyz 00E5*S-EVBBxyz 00DF*From S-EVBBxyz 00FC on (i.e. 00FC, 00FD, etc.).The following serial numbers were manufactured according to the BOM version 2.2.0:*From S-EVBBxyz 00AC to S-EVBBxyz 00E4*From S-EVBBxyz 00E6 to 00DE*From S-EVBBxyz 00E0 to 00FB.}}==== Release 2.4.0 ====* BoraEVB: [https://www.dave.eu/links/p/ylcKMeQpKzgScnkz BORAEVB_S.EVBB0000I1R.2.4.0.CSV.zip]==== Release 2.2.0 ====* BoraEVB: [https://www.dave.eu/links/p/hbJ8HyApBiva1qgl boraevb-BOM_S.EVBB0000I1R.2.2.1.CSV_.zip]===Layout===* Coming soon[https://www.dave.eu/links/p/AUBnjq9DoTC2gget boraevb-CS040713A_all_view.pdf]<section end=Schematics/><section begin=Mechanicals/>
==Mechanical==
* DXF: coming soon[https://www.dave.eu/links/p/ndf9AsBgti3TnGRF boraevb_CS040713A.dxf.zip]* IDF (3D): coming soon[https://www.dave.eu/links/p/l2wRddTIcC3RSZb8 boraevb_CS040713A.emn]<section end=Mechanicals/>
