Changes

mettere The VTM is able to verify all the video interfaces at the same time thanks to the BoraX SOM resources disponibility, in evidenza l'accessibilità ai registri da PS e da I2Cterm of PL logic resource and pinout. The high pin count permits to connect 3 RGB parallel videos with 24 bit of data.

There are two ways The Checksum/CRC test logic can elaborate up to access 60 frames per second on a Full-HD video flux. This reduces the ATE test time because on a time windows of few seconds the VTM can elaborate several hundred video frames. All the PL block logic registerare connected to the AXI bus, from the and we have also implemented a I2C slave to AXI bridge.

1) stand-alone device - a dedicated sw SW (bare metal or linux Linux OS) that runs on PS can setup the PL logic and verify the video streams

2) slave device of the ATE - an external master I2C can setup the PL logic and verify the video streams through a an I2C bridge (implemented on PL logic)

This is possible with a single PL configuration bitstream thanks to use using of Xilinx® LogiCORE™ IP AXI Interconnect core. It permits to connect one or more AXI memory-mapped master devices to one or more memory-mapped slave devices.