The ATE tests the functionalities of the product–also known as device under test (DUT)–by exchanging data over its numerous interfaces. In this case, the DUT integrates some video outputs (namely HDMI, LVDS0, and LVDS1) that consist of differential pairs. These outputs usually drive LCD screens or HDMI monitors. In order to test them, the easiest solution is to connect such displays and to verify that the test images are visualized properly. Even though this approach is straightforward, it is very economically inefficient from the economic standpoint because it is slow and error-prone, as it requires a human operator to visually inspect the displays.

The VTM is able to verify all On this specific implementation, the DUT has 3 video output interfaces at the same time thanks to the BoraX SOM resources disponibility: HDMI, LVDS0, in term of PL logic resource and pinout. The high pin count permits to connect 3 RGB parallel videos with 24 bit of dataLVDS1.

The Checksum/CRC test logic can elaborate up VTM is able to 60 frames per second on a Full-HD verify all the video flux. This reduces interfaces at the ATE test same time because on a time windows thanks to the BoraX SOM resources availability, in terms of few seconds the VTM can elaborate several hundred PL logic resources and pinout. The high pin count permits to connect 3 RGB parallel video framesstreams with 24 bit of data.

All the PL block The Checksum/CRC test logic are connected can elaborate up to 60 frames per second on a Full-HD video stream. This reduces the AXI bus, and we have also implemented ATE test time because on a I2C slave to AXI bridgetime windows of few seconds the VTM can elaborate several hundreds of video frames.

This allows All the VTM PL logic blocks are connected to works as:the AXI bus. Also, an I2C slave to AXI bridge was implemented.

1) stand-alone device - a dedicated SW (bare metal or Linux OS) that runs on PS can setup This allows the PL logic and verify the video streamsVTM to work as:

2#Stand-alone device - a dedicated software (bare metal or Linux OS based) slave running on the PS can setup the PL logic and verify the video streams. In this case, the PS access the configurations register through the AXI bus.#Slave device of the ATE - an external I2C master I2C can setup set up the PL logic and verify the video streams through an the I2C -to-AXI bridge (implemented on PL logic).

This is possible with a single PL configuration bitstream thanks to using of Xilinx® LogiCORE™ IP AXI Interconnect core. It permits to connect which allows connecting one or more AXI memory-mapped master devices to one or more memory-mapped slave devices.