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{{Applies To BoraX}}
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== History ==
[[File:TBDBXELK-TN-003-bd.png|thumb|center|600px|captionSimplified block diagram of the entire ATE]]
The ATE tests the functionalities of the product–also known as device under test (DUT)–by exchanging data over its numerous interfaces. In this case, the DUT integrates some video outputs (namely HDMI, LVDS0, and LVDS1) that consist of differential pairs. These outputs usually drive LCD screens or HDMI monitors. In order to test them, the easiest solution is to connect such displays and to verify that the test images are visualized properly. Even though this approach is straightforward, it is very economically inefficient from the economic standpoint because it is slow and error-prone, as it requires a human operator to visually inspect the displays.
The solution described in this technical note addresses this issue. By implementing an automatic test system, it fully releases the operator from this task. Also, the test is much quicker and much more reliable, as it implements a 100% coverage of the pixels the test frames are composed of.
The video streams are connected to the deserializers which populate the carrier board. They convert the streams into parallel single-ended busses which are fed to the Programmable Logic (PL) of BoraX.
===Programmable Logic===
The PL integrates the actual test logic, which is depicted in the following image.
[[File:Borax_DMTRGB_block_design.png|thumb|center|600px|Video Test PL Block Diagram]]
On this specific implementation, the DUT has 3 video output interfaces: HDMI, LVDS0, and LVDS1. The VTM is able to verify all the video interfaces at the same time thanks to the BoraX SOM resources availability, in terms of PL logic resources and pinout. The high pin count permits to connect 3 RGB parallel video streams with 24 bit of data. The Checksum/CRC test logic can elaborate up to 60 frames per second on a Full-HD video stream. This reduces the ATE test time because on a time windows of few seconds the VTM can elaborate several hundreds of video frames. All the PL logic blocks are connected to the AXI bus. Also, an I2C slave to AXI bridge was implemented. This allows the VTM to work as: #Stand-alone device - a dedicated software (bare metal or Linux OS based) running on the PS can setup the PL logic and verify the video streams. In this case, the PS access the configurations register through the AXI bus.#Slave device of the ATE - an external I2C master can set up the PL logic and verify the video streams through the I2C-to-AXI bridge. This is possible with a single PL configuration bitstream thanks to using of Xilinx® LogiCORE™ IP AXI Interconnect core which allows connecting one or more AXI memory-mapped master devices to one or more memory-mapped slave devices. ===The automatic test procedure===The automatic test procedure consist consists of the following steps:
*The master test module computes the CRC32 of the test frame (Ref_CRC)
** The frame is considered as a data sequence where every pixel is composed of 3 bytes: the R-G-B data
**For each stream, it computes the CRC32 for every received frame in real-time. In case the computed value matches Ref_CRC, the counter of valid frames is incremented. Otherwise, the frame of the corrupted frames is increased.
*After a while, the master test module stops the video test and verify the counters. If all of the transmitted frames are good, the test is passed.
===Future work===
The acquisition of the LVDS/HDMI video streams can be optimized by using the built-in hard SerDes blocks provided by the Zynq SOC. This implementation would allow avoiding the use of the external deserializers.