Difference between revisions of "BORA SOM/BORA Hardware/Power and Reset/System boot"

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== System boot ==
 
== System boot ==
  
−
The boot process begins at Power On Reset (POR) where the hardware reset logic forces the ARM core to begin execution starting from the on-chip boot ROM. The boot ROM:
+
The boot process begins at Power On Reset (POR) where the hardware reset logic forces the ARM core to begin execution starting from the on-chip boot ROM.  
−
* determines whether the boot is secure or non-secure
+
 
−
* performs some initialization of the system and clean-ups
+
=== Boot options ===
−
* reads the mode pins to determine the primary boot device
+
 
−
* once it is satisfied, it executes the boot code
+
The boot ROM supports configuration from four different slave interfaces:
 +
* Quad-SPI
 +
* NAND
 +
* NOR flash (not available on BORA)
 +
* SD card
  
 +
Boot mode is selectable via five mode pins (BOOT_MODE[4:0]), and two voltage mode signals, (VMODE[1:0]). The BOOT_MODE pins are MIO[6:2] and the VMODE pins are MIO[8:7]. The pins are used as follows:
  
 +
{|class="wikitable" style="text-align: center;"
 +
|-
 +
!Function
 +
!Boot signals
 +
!Available options
 +
|-
 +
| JTAG mode || BOOT_MODE[3]<br>MIO[2]|| 0: Cascaded JTAG<br>1: Independent JTAG
 +
|-
 +
| Boot mode || BOOT_MODE[0-2-1]<br>MIO[5:3] || 000: JTAG<br>010: NAND<br>100: Quad-SPI<br>110: SD card
 +
|-
 +
| PLLs enable || BOOT_MODE[4]<br>MIO[6] || 0: PLL used<br>1: PLL bypassed
 +
|-
 +
| MIO Bank 0 Voltage || VMODE[0]<br>MIO[7] || 0: 2.5 V, 3.3 V<br>1: 1.8 V
 +
|-
 +
|MIO Bank 0 Voltage || VMODE[1]<br>MIO[8] || 0: 2.5 V, 3.3 V<br>1: 1.8 V
 +
|-
 +
|}
  
−
''TBD: le sezioni di seguito sono valide - come esempio per AXEL Lite - da rivedere per gli altri prodotti ''
+
In order to fully understand how boot works on BORA platform, please refer to chapter 6 ("Boot and configuration") of the Zynq7000 Technical Reference Manual.
  
 +
=== Default boot configuration ===
  
−
== Boot options ==
+
Default configuration for BORA module is:
 +
* Mode[0..3] = 1000: Quad-SPI mode
 +
* Mode[4] = 0: PLL not bypassed
 +
* VCFG[0] = 0: 2.5V, 3.3V operations for bank 0
 +
* VCFG[1] = 1: 1.8 operations for bank 1
  
−
Two options are available related to system boot. They are identified by the Boot field of the ordering code as follows:
+
Assuming that:
−
* 0: SPI NOR / SD option (SOM code: DXLxxxx0xxR)
+
* default configuration is not changed,
−
* 1: NAND / SD option (SOM code: DXLxxxx1xxR)
+
* there's a valid boot code programmed in SPI flash memory the actual boot sequence performed by ARM core will be:
−
For both options the selection of primary boot device is determined by the BOOT_MODE_SEL signal as described in the following sections. BOOT_MODE_SEL is latched when processor reset is released.
+
# Bootrom is executed from internal ROM code memory
 +
# FSBL is copied from on-board NOR flash memory connected to SPI0 port to on-chip SRAM by bootrom
 +
# FSBL is executed from on-chip SRAM
 +
# U-Boot bootloader (2nd stage) is copied by FSBL from NOR flash memory connected to Quad-SPI port to SDRAM
 +
# U-boot (2nd stage) is executed from SDRAM
  
−
In any case, boot process is managed by on-chip boot ROM code that is described in detail in processor's Reference Manual.
+
If no boot code is available in SPI NOR flash, the bootrom tries JTAG peripheral booting.
  
−
=== SPI NOR / SD option ===
+
=== Boot sequence customization ===
−
Selection of primary boot device is determined by the BOOT_MODE_SEL signal as follows:
 
−
* BOOT_MODE_SEL = 0
 
−
** primary boot device is SD1
 
−
* boot ROM will try to boot a valid image from the SD card first, and then from the SPI NOR. In case no valid image is found, boot ROM shall enable USB serial download mode automatically
 
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* BOOT_MODE_SEL = 1 or floating
 
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** primary boot device is SPI NOR flash connected to eCSPI1
 
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** in case no valid image is found in NOR flash, boot ROM shall enable USB serial download mode automatically
 
  
−
=== NAND / SD option ===
+
BOOT_MODE[4:0] are routed to the J1 connector, enabling for the customization of the boot sequence through a simple resistor network that can be implemented on carrier board hosting BORA module.
−
Selection of primary boot device is determined by the BOOT_MODE_SEL signal as follows:
 
−
* BOOT_MODE_SEL = 0
 
−
** primary boot device is SD1
 
−
** in case no valid image is found in SD card, boot ROM shall enable USB serial download mode automatically
 
−
* BOOT_MODE_SEL = 1 or floating
 
−
** primary boot device is NAND flash
 
−
** in case no valid image is found in NAND flash, boot ROM shall enable USB serial download mode automatically
 
  
−
===Important note for DualLite/Solo based products (''manufacture mode'' management)===
+
{|class="wikitable" style="text-align: center;"
−
When Dual Lite or Solo processor are used, GPIO_1 and GPIO_4 signals need to be kept high during bootstrap stage in order to prevent the intervention of bootrom's ''manufacture mode''. Bootstrap stage has to be intended as the time elapsing between the release of hardware reset (CPU_PORn) and the execution of the first instruction of user code (typically this is the reset vector of U-Boot boot loader). Please note that, in case GPIO_1 signal is used to implement [[Reset_scheme_(AxelLite)#Handling_CPU-initiated_software_reset|software reset circuit]], it is high during bootstrap stage by design.
+
|-
 +
!Mode signal
 +
!J1 pin
 +
!Pin name
 +
|-
 +
| BOOT_MODE[4] || J1.129 || SPI0_SCLK/MODE4/NAND_IO1
 +
|-
 +
| BOOT_MODE[3] || J1.125 || SPI0_DQ0/MODE3/NAND_ALE
 +
|-
 +
| BOOT_MODE[2] || J1.121 || SPI0_DQ2/MODE2/NAND_IO2
 +
|-
 +
| BOOT_MODE[1] || J1.123 || SPI0_DQ1/MODE1/NAND_WE
 +
|-
 +
| BOOT_MODE[0] || J1.119 || SPI0_DQ3/MODE0/NAND_IO0
 +
|}
  
 
----
 
----
  
 
[[Category:BORA]]
 
[[Category:BORA]]

Revision as of 09:29, 28 October 2021

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History
Version Issue Date Notes
1.0.0 Oct 2021 New documentation layout


System boot[edit | edit source]

The boot process begins at Power On Reset (POR) where the hardware reset logic forces the ARM core to begin execution starting from the on-chip boot ROM.

Boot options[edit | edit source]

The boot ROM supports configuration from four different slave interfaces:

  • Quad-SPI
  • NAND
  • NOR flash (not available on BORA)
  • SD card

Boot mode is selectable via five mode pins (BOOT_MODE[4:0]), and two voltage mode signals, (VMODE[1:0]). The BOOT_MODE pins are MIO[6:2] and the VMODE pins are MIO[8:7]. The pins are used as follows:

Function Boot signals Available options
JTAG mode BOOT_MODE[3]
MIO[2]		 0: Cascaded JTAG
1: Independent JTAG
Boot mode BOOT_MODE[0-2-1]
MIO[5:3]		 000: JTAG
010: NAND
100: Quad-SPI
110: SD card
PLLs enable BOOT_MODE[4]
MIO[6]		 0: PLL used
1: PLL bypassed
MIO Bank 0 Voltage VMODE[0]
MIO[7]		 0: 2.5 V, 3.3 V
1: 1.8 V
MIO Bank 0 Voltage VMODE[1]
MIO[8]		 0: 2.5 V, 3.3 V
1: 1.8 V

In order to fully understand how boot works on BORA platform, please refer to chapter 6 ("Boot and configuration") of the Zynq7000 Technical Reference Manual.

Default boot configuration[edit | edit source]

Default configuration for BORA module is:

  • Mode[0..3] = 1000: Quad-SPI mode
  • Mode[4] = 0: PLL not bypassed
  • VCFG[0] = 0: 2.5V, 3.3V operations for bank 0
  • VCFG[1] = 1: 1.8 operations for bank 1

Assuming that:

  • default configuration is not changed,
  • there's a valid boot code programmed in SPI flash memory the actual boot sequence performed by ARM core will be:
  1. Bootrom is executed from internal ROM code memory
  2. FSBL is copied from on-board NOR flash memory connected to SPI0 port to on-chip SRAM by bootrom
  3. FSBL is executed from on-chip SRAM
  4. U-Boot bootloader (2nd stage) is copied by FSBL from NOR flash memory connected to Quad-SPI port to SDRAM
  5. U-boot (2nd stage) is executed from SDRAM

If no boot code is available in SPI NOR flash, the bootrom tries JTAG peripheral booting.

Boot sequence customization[edit | edit source]

BOOT_MODE[4:0] are routed to the J1 connector, enabling for the customization of the boot sequence through a simple resistor network that can be implemented on carrier board hosting BORA module.

Mode signal J1 pin Pin name
BOOT_MODE[4] J1.129 SPI0_SCLK/MODE4/NAND_IO1
BOOT_MODE[3] J1.125 SPI0_DQ0/MODE3/NAND_ALE
BOOT_MODE[2] J1.121 SPI0_DQ2/MODE2/NAND_IO2
BOOT_MODE[1] J1.123 SPI0_DQ1/MODE1/NAND_WE
BOOT_MODE[0] J1.119 SPI0_DQ3/MODE0/NAND_IO0
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