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{{Applies To BoraLite}}
{{AppliesToBORA Lite TN}}
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__FORCETOC__
==Testbed==
From the hardware perspective, the testbed is like the one shown [[BELK/BXELK_Quick_Start_Guide#BoraX-BoraXEVB-Lite|here]]. It consists of a BoraXEVB carrier board, a Bora Lite Adapter, and a single-core Bora Lite SoM(equipped with XC7Z007 SoC).
The BoraXEVB carrier board is set up to make the SoM boot from the microSD card.
==Running the application==
There are several ways to run the application on the target. For instance, a JTAG debugging tool can be used. The following is a script in PRACTICE language used to set up a debugging session with [https://www.lauterbach.com/ Lauterbach TRACE32 PowerView]:
<syntaxhighlight line="line"pre>
SYStem.CPU ZYNQ-7000CORE0
enddo
</syntaxhighlightpre>
Another way to download and run the application is by using the <code>tftpboot</code> and <code>bootelf</code> commands as shown in the following example(*):
<pre class="board-terminal">
Bora> tftpboot ${loadaddr} boralite/freertos_hello_world.elf
FreeRTOS Hello World Example PASSED
</pre>
(*) It seems that the message ''CACHE: Misaligned operation at range [x, y]'' is [https://forums.xilinx.com/t5/Embedded-Linux/CACHE-Misaligned-operation-at-range-1ffed120-1ffed276/td-p/963278 not a real problem].
==Related links==
*
* [[BELK-AN-001: Asymmetric Multiprocessing (AMP) on Bora – Linux FreeRTOS]]
* [[BELK-AN-002: Trace on the Bora AMP (Linux + FreeRTOS) system]]
* [[BELK-AN-007: Asymmetric Multiprocessing (AMP) on Bora/BoraX with OpenAMP]]