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{{Applies To BoraX}}
{{Applies To BoraLite}}
{{AppliesToBORA_AN}}
{{AppliesToBORA_Xpress_AN}}
{{AppliesToBORA Lite AN}}
{{InfoBoxBottom}}
{{WarningMessage|text=This application note was validated against specific versions of the kit only. It may not work with other versions. Supported versions are listed in the ''History'' section.}}
{{ImportantMessage|text=It is assumed to use ZYNQ SOC with <b><i>speed grade -1</i></b> (even using command line script or GUI).In any case, there are no issues using <b><i>speed grade -3</i></b> SOC provided with BELK kit}}
|}
Since bank #34 is powered at 3.3V (High Range I/O mode), RGMII duty cycle distortion specification is not matched. In case of carrier board designed for production environments, <u>it is recommended to use a lower voltage levels and thus a different PL bank</u>. For more details please see section ''I/O Standard and Placement'' of [httphttps://xgoogledocs.xilinx.com/search?output=xml_no_dtd&ie=UTFr/en-US/pg160-gmii-8&oe=UTFto-8&getfields=*&filter=0&site=EntireSite&num=200&client=xilinx&proxystylesheet=xilinx&show_dynamic_navigation=0&allVersions=rgmii/GMII-to-RGMII-v4.1&sort=meta:Last%2520Modified%2520Date%3AD%3AED&q=+inmeta:Document%2520Class%3DDocument+inmeta:-LogiCORE-IP-Product%2520Type%3DIP%2520Cores+inmeta:IP%3DGMII%2520to%2520RGMII -Guide ''PG160 GMII to RGMII LogiCORE IP Product Guide''] and [[Power_(Bora)|this page]].
The Vivado project can also be build with the procedure explained [[Creating_and_building_example_Vivado_project_(BELK/BXELK)#Command_line_based_procedure|here]].
* For Bora SoM use:
** [http://mirror.dave.eu/bora/belk-4.1.0/belk-4.1.1_bora_mmc_an006_boot.bin u-boot (SPL)]
** [http://mirror.dave.eu/bora/belk-4.1.0/belk-4.1.1_bora_mmc_an006_boot1_bora_mmc_an006_u-boot.img u-boot (img)]
** [http://mirror.dave.eu/bora/belk-4.1.0/belk-4.1.0_uImage uImage]
** [http://mirror.dave.eu/bora/belk-4.1.0/belk-4.1.0_bora-an006.dtb dtb]
** [http://mirror.dave.eu/bora/belk-4.1.0/belk-4.1.0_bora_ETH1_fpga.bin bit fpga]
* For BoraLite SoM use:
** [http://mirror.dave.eu/bora/belk-4.1.0/belk-4.1.1_bora_mmc_an006_boot.bin u-boot (SPL)]
** [http://mirror.dave.eu/bora/belk-4.1.0/belk-4.1.1_bora_mmc_an006_boot1_bora_mmc_an006_u-boot.img u-boot (img)]
** [http://mirror.dave.eu/bora/belk-4.1.0/belk-4.1.0_uImage uImage]
** [http://mirror.dave.eu/bora/belk-4.1.0/belk-4.1.0_bora-an006.dtb dtb]
** [http://mirror.dave.eu/bora/belk-4.1.0/belk-4.1.0_boralite_ETH1_fpga.bin bit fpga]
* For BoraX SoM use:
** [http://mirror.dave.eu/bora/belk-4.1.0/belk-4.1.1_borax_mmc_an006_boot.bin u-boot (SPL)]
** [http://mirror.dave.eu/bora/belk-4.1.0/belk-4.1.0_uImage uImage]
** [http://mirror.dave.eu/bora/belk-4.1.0/belk-4.1.0_bora-an006.dtb dtb]
** [http://mirror.dave.eu/bora/belk-4.1.0/belk-4.1.0_borax_ETH1_fpga.bin bit fpga]
===Performance tests===