!BELK /BXELK version

|September 2015

Thanks to the migration to linux kernel 3.10.17, [[Bora_Embedded_Linux_Kit_(BELK)#BELK_software_components|BELK 2.2.0]] and [[Bora_Embedded_Linux_Kit_(BELK)#BELK_software_components|BELK 3.0.0]] allows to cleanly support dual Gigabit Ethernet configuration on BoraEVBand BoraXEVB. This application note describes how to implement such configuration, providing a reference design for Vivado 2014.4 and linux kernel configuration instructions.

First Ethernet port refers to J8 connector of BoraEVB and BoraXEVB carrier board and is based on Zynq's Gigabit Ethernet Controller 0 (Gem0). This controller is mapped at physical address 0xE000B000.

Second Ethernet port refers to J9 connector of BoraEVB and BoraXEVB carrier board and is based on Zynq's Gigabit Ethernet Controller 1 (Gem1). This controller is mapped at physical address 0xE000C000.

The fundamental difference between the two interfaces is the PHY interfacing. In case of Gem0, PHY is mounted on Bora and BoraX SoM and it is interfaced directly to Processor Subsystem (PS) via MIO pads. In case of Gem1 instead, PHY is populated on BoraEVB and BoraXEVB (U9) and it is interfaced to Programmable Logic (PL) pads that belong to bank #34. Thus it is necessary to enable EMIO routing and to instantiate a GMII to RGMII bridge in PL as per PHY's interface requirement. Since bank #34 About MII bus (MDIO, MDC), two different busses are used:*Bora PHY is powered connected to the signals <code>ETH_MDC</code> and <code>ETH_MDIO</code> (available on BoraEVB at 3JP18.3V (High Range I/O mode7 and JP18.9 respectively), RGMII duty cycle distortion specification **this MII bus is not matched. In case of carrier board designed for production environments, associated to <code>gem0<u/code>it *BoraEVB PHY is recommended connected to use a lower voltage levels and thus a different PL bank's <code>IO_L9N_T1_DQS_34</ucode> (<code>. For more details please see section ''IETH1_MDC</O Standard code>) and Placement'' of [http:<code>IO_L9P_T1_DQS_34</code> (<code>ETH1_MDIO</xgooglecode>); these signals are available on BoraEVB at JP18.xilinx8 and JP18.com10 respectively**this MII bus is associated to <code>gem1</search?output=xml_no_dtd&ie=UTF-8&oe=UTF-8&getfields=code>**&filter=0&site=EntireSite&num=200&client=xilinx&proxystylesheet=xilinx&show_dynamic_navigation=0&allVersions=1&sort=meta:Last%2520Modified%2520Date%3AD%3AED&q=+inmeta:Document%2520Class%3DDocument+inmeta:Product%2520Type%3DIP%2520Cores+inmeta:IP%3DGMII%2520to%2520RGMII ''PG160 GMII it is worth to RGMII LogiCORE IP Product Guide''] and [[Power_remember that a virtual PHY (Borawhose address is 8)|is connected to this page]]bus as well; this PHY is implemented in the GMII/RGMII bridge and it is used to configure the bridge at runtime, depending on operating parameters such as the Ethernet physical link speed.

The project archive ===Bora + BoraEVB===On BoraEVB PHY1 is interfaced to Programmable Logic (PL) pads that belong to bank #34. '''WARNING:''' due to a restraint introduced, from Vivado version 2017.1 onwards, the signal ETH1_TXCK can be downloaded routed only to a pad that is MRCC or SRCC input. As result from BELK 4.0.0 an hardware rework is needed on the BoraEVB board:* Remove R183* Remove R232* Connect R183.2 with R232.1 This rework prevents the use of the PL SDRAM onboard of the BoraEVB (by default this ram is not mounted). Here is the pinout assignment for the PHY1 on BoraEVB:{| class="wikitable" | | align="center" style="background:#f0f0f0;"|'''PHY1 Signal'''| align="center" style="background:#f0f0f0;"|'''BORA SOM Signal'''|-| ETH1_TXD0||IO_L24P_T3_34|-| ETH1_TXD1||IO_L24N_T3_34|-| ETH1_TXD2||IO_L23P_T3_34|-| ETH1_TXD3||IO_L23N_T3_34|-| ETH1_TXCK||IO_L20P_T3_34|-| ETH1_TXCTL||IO_L20N_T3_34|-| ETH1_RXD0||IO_L5N_T0_34|-| ETH1_RXD1||IO_L5P_T0_34|-| ETH1_RXD2||IO_L7N_T1_34|-| ETH1_RXD3||IO_L7P_T1_34|-| ETH1_RXCK||<span style="text-decoration: line-through;">IO_L4N_T0_34</span> IO_L13P_T1_MRCC_34|-| ETH1_RXCTL||IO_L4P_T0_34|-| ETH1_MDC||IO_L9N_T1_DQS_34|-| ETH1_MDIO||IO_L9P_T1_DQS_34|-|} Since bank #34 is powered at 3.3V (High Range I/O mode), RGMII duty cycle distortion specification is not matched. In case of carrier board designed for production environments, <u>it is recommended to use a lower voltage levels and thus a different PL bank</u>. For more details please see section ''I/O Standard and Placement'' of [httphttps://wwwdocs.davexilinx.eucom/systemr/filesen-US/areapg160-gmii-to-rgmii/GMII-to-RGMII-v4.1-LogiCORE-IP-Product-Guide ''PG160 GMII to RGMII LogiCORE IP Product Guide''] and [[Power_(Bora)|this page]]. The Vivado project can also be build with the procedure explained [[Creating_and_building_example_Vivado_project_(BELK/BXELK)#Command_line_based_procedure|here]]. ===BoraLite + Adapter + BoraXEVB===On BoraXEVB PHY1 is interfaced to Programmable Logic (PL) pads that belong to bank #13. The BoraLite Adapter take care of rerouting the ETH1_RXCK to meet the Vivado requirements. Here is the pinout assignment for the PHY1 on BoraXEVB:{| class="wikitable" | | align="center" style="background:#f0f0f0;"|'''PHY1 Signal'''| align="center" style="background:#f0f0f0;"|'''BORAX SOM Signal'''|-| ETH1_TXD0||IO_L19P_T3_13|-| ETH1_TXD1||IO_L19N_T3_VREF_13|-| ETH1_TXD2||IO_L20P_T3_13|-| ETH1_TXD3||IO_L20N_T3_13|-| ETH1_TXCK||IO_L16P_T2_13|-| ETH1_TXCTL||IO_L16N_T2_13|-| ETH1_RXD0||IO_L17P_T2_13|-| ETH1_RXD1||IO_L17N_T2_13|-| ETH1_RXD2||IO_L18P_T2_13|-| ETH1_RXD3||IO_L18N_T2_13|-| ETH1_RXCK||IO_L14P_T2_SRCC_13|-| ETH1_RXCTL||IO_L14N_T2_SRCC_13|-| ETH1_MDC||IO_L21N_T3_DQS_13|-| ETH1_MDIO||IO_L21P_T3_DQS_13|-riservata|} I/ANO voltage of bank 13 must be set to 2.5V by configuring [[BoraXEVB#BANK13_VDDIO_selector_-_JP25|JP25 ]] as shown in the following table.{| class="wikitable" border="1"!Pins!Setting|-|1-2|closed|-|3-4|open|-|5-6|closed|-|7-8|open|-|9-10|open|-|11-12|open|-|} The Vivado project can also be build with the procedure explained [[Creating_and_building_example_Vivado_project_(BELK/BXELK)#Command_line_based_procedure|here]]. ===Borax + BoraXEVB===On BoraXEVB PHY1 is interfaced to Programmable Logic (PL) pads that belong to bank #13. '''WARNING:''' due to a restraint introduced, from Vivado version 2017.1 onwards, the signal ETH1_TXCK can be routed only to a pad that is MRCC or SRCC input. As result from BXELK 2.0.0 an hardware rework is needed on the BoraXEVB board:* Remove RP84* Remove R232* Connect RP84.2 with R232.1 This rework prevents the use of the LVDS connector on BoraXEVB (J26). Here is the pinout assignment for the PHY1 on BoraXEVB:{| class="wikitable" | | align="center" style="background:#f0f0f0;"|'''PHY1 Signal'''| align="center" style="background:#f0f0f0;"|'''BORAX SOM Signal'''|-006| ETH1_TXD0||IO_L19P_T3_13|-sw | ETH1_TXD1||IO_L19N_T3_VREF_13|-| ETH1_TXD2||IO_L20P_T3_13|-| ETH1_TXD3||IO_L20N_T3_13|-| ETH1_TXCK||IO_L16P_T2_13|-| ETH1_TXCTL||IO_L16N_T2_13|-| ETH1_RXD0||IO_L17P_T2_13|-| ETH1_RXD1||IO_L17N_T2_13|-| ETH1_RXD2||IO_L18P_T2_13|-| ETH1_RXD3||IO_L18N_T2_13|-| ETH1_RXCK||<span style="text-decoration: line-through;">IO_L15P_T2_DQS_13</span> IO_L12P_T1_MRCC_13|-| ETH1_RXCTL||IO_L15N_T2_DQS_13|-| ETH1_MDC||IO_L21N_T3_DQS_13|-| ETH1_MDIO||IO_L21P_T3_DQS_13|-|} I/O voltage of bank 13 must be set to 2.5V by configuring [[BoraXEVB#BANK13_VDDIO_selector_-_JP25|JP25 ]] as shown in the following table.{| class="wikitable" border="1"!Pins!Setting|-|1-2|closed|-|3-4|open|-|5-6|closed|-|7-8|open|-|9-10|open|-|11-12|open|-|} The Vivado project can also be build with the procedure explained [[Creating_and_building_example_Vivado_project_(BELK/BXELK)#Command_line_based_procedure|here]].

To enable dual Ethernet user needs to get the pre-built binaries from this [http://www.dave.eu/system/files/area[BELK-riservata/AN-BELK-006:_Enabling_dual_Gigabit_Ethernet_support_on_BoraEVB/BoraXEVB#Pre-sw.zip linkbuilt_binaries |here]].

* update Bora kernel repository (as described [[Bora_Embedded_Linux_Kit_(BELK)/BXELK_software_components#Updating_the_repositories_from_BELK_2.1.0_to_BELK_2.2.0Updating_git_repositories|here]])* apply build the patch <code>0001-dts-bora-add-ETH1-phy-supportan006.patchdtb</code> included in the pre-build binaries packagedevicetree

Here is the patch to enable dual Ethernet:<pre>diff --git a/arch/arm/boot/dts/bora.dts b/arch/arm/boot/dts/bora.dtsindex 654770e..35697cd 100644--- a/arch/arm/boot/dts/bora.dts+++ b/arch/arm/boot/dts/bora.dts@@ -59,6 +59,25 @@ }; }; +&gem1 {+ status = "okay";+ phy-mode = "rgmii-id";+ phy-handle = <&phy1>;+ gmii2rgmii-phy-handle = <&phy2>;++ phy1: phy@6 {+ compatible = "micrel,ksz9031";+ device_type = "ethernet-phy";+ rxc-skew-ps = <1860>;+ txc-skew-ps = <1860>;+ reg = <6>;+ };++ phy2: phy@8 {+ reg = <8>;+ };+};+ &sdhci0 { status = "okay"; broken-cd = <0x1>;</pre> Put the binaries on the first (FAT32) partition of your BELK 2.2.0 SD card, overwriting the original one if needed. Please note that you need the following files:

Insert the SD card into BoraEVB or BoraXEVB and turn on the board.