Bureaucrats, dave_user, Administrators
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{{Applies To Bora}}
{{Applies To BoraX}}
{{Applies To BoraLite}}
{{AppliesToBORA_AN}}
{{AppliesToBORA_Xpress_AN}}
{{AppliesToBORA Lite AN}}
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{{WarningMessage|text=This application note was validated against specific versions of the kit only. It may not work with other versions. Supported versions are listed in the ''History'' section.}}
{{ImportantMessage|text=It is assumed to use ZYNQ SOC with <b><i>speed grade -1</i></b> (even using command line script or GUI). In any case, there are no issues using <b><i>speed grade -3</i></b> SOC provided with BELK kit}}
==History==
{| class="wikitable" border="1"
!Version
!Date
!BELK /BXELK version
!Notes
|-
|1.0.0
|September 2015
|[[Bora_Embedded_Linux_Kit_(BELK)#BELK_software_components|2.2.0]]
|First release
|-
|1.1.0
|January 2016
|[[Bora_Embedded_Linux_Kit_(BELK)#BELK_software_components|2.2.0, 3.0.0]]
|Added support for BoraX/BoraXEVB platform
|-
|{{oldid|8290|1.1.1}}
|September 2016
|[[Bora_Embedded_Linux_Kit_(BELK)#BELK_software_components|2.2.0, 3.0.0]]
|Added more information about MII buses organization
|-
|2.0.0
|January 2020
|[[Bora_Embedded_Linux_Kit_(BELK)#BELK_software_components|4.1.0 / 2.1.0]]
|AN migration to BELK 4.1.0 / BXELK 2.1.0
|-
|}
==Introduction==
Thanks to the migration to linux kernel 3.10.17, [[Bora_Embedded_Linux_Kit_(BELK)#BELK_software_components|BELK 2.2.0]] and [[Bora_Embedded_Linux_Kit_(BELK)#BELK_software_components|BELK 3.0.0]] allows to cleanly support dual Gigabit Ethernet configuration on BoraEVBand BoraXEVB. This application note describes how to implement such configuration, providing a reference design for Vivado 2014.4 and linux kernel configuration instructions. ==Block diagram==Simplified block diagram of dual Ethernet configuration is shown in the following picture.
[[File:An-belk-006-bd.png|thumb|center|600px]]
[[File:an-belk-006-boralite-01.png|thumb|center|600px]]
Second Ethernet port refers to J9 connector of BoraEVB and BoraXEVB carrier board and is based on Zynq's Gigabit Ethernet Controller 1 (Gem1). This controller is mapped at physical address 0xE000C000.
The fundamental difference between the two interfaces is the PHY interfacing. In case of Gem0, PHY is mounted on Bora and BoraX SoM and it is interfaced directly to Processor Subsystem (PS) via MIO pads.
In case of Gem1 instead, PHY is populated on BoraEVB and BoraXEVB (U9) and it is interfaced to Programmable Logic (PL). Thus it is necessary to enable EMIO routing and to instantiate a GMII to RGMII bridge in PL as per PHY's interface requirement. About MII bus (MDIO, MDC), two different busses are used:
*Bora PHY is connected to the signals <code>ETH_MDC</code> and <code>ETH_MDIO</code> (available on BoraEVB at JP18.7 and JP18.9 respectively)
**this MII bus is associated to <code>gem0</code>
*BoraEVB PHY is connected to PL's <code>IO_L9N_T1_DQS_34</code> (<code>ETH1_MDC</code>) and <code>IO_L9P_T1_DQS_34</code> (<code>ETH1_MDIO</code>); these signals are available on BoraEVB at JP18.8 and JP18.10 respectively
**this MII bus is associated to <code>gem1</code>
**it is worth to remember that a virtual PHY (whose address is 8) is connected to this bus as well; this PHY is implemented in the GMII/RGMII bridge and it is used to configure the bridge at runtime, depending on operating parameters such as the Ethernet physical link speed.
==Vivado design==
The following picture shows the block diagram of the Vivado project:
[[File:An-belk-005006-0201.png|800px]] ===Bora + BoraEVB===On BoraEVB PHY1 is interfaced to Programmable Logic (PL) pads that belong to bank #34. '''WARNING:''' due to a restraint introduced, from Vivado version 2017.1 onwards, the signal ETH1_TXCK can be routed only to a pad that is MRCC or SRCC input. As result from BELK 4.0.0 an hardware rework is needed on the BoraEVB board:* Remove R183* Remove R232* Connect R183.2 with R232.1 This rework prevents the use of the PL SDRAM onboard of the BoraEVB (by default this ram is not mounted). Here is the pinout assignment for the PHY1 on BoraEVB:{| class="wikitable" | | align="center" style="background:#f0f0f0;"|'''PHY1 Signal'''| align="center" style="background:#f0f0f0;"|'''BORA SOM Signal'''|-| ETH1_TXD0||IO_L24P_T3_34|-| ETH1_TXD1||IO_L24N_T3_34|-| ETH1_TXD2||IO_L23P_T3_34|-| ETH1_TXD3||IO_L23N_T3_34|-| ETH1_TXCK||IO_L20P_T3_34|-| ETH1_TXCTL||IO_L20N_T3_34|-| ETH1_RXD0||IO_L5N_T0_34|-| ETH1_RXD1||IO_L5P_T0_34|-| ETH1_RXD2||IO_L7N_T1_34|-| ETH1_RXD3||IO_L7P_T1_34|-| ETH1_RXCK||<span style="text-decoration: line-through;">IO_L4N_T0_34</span> IO_L13P_T1_MRCC_34|-| ETH1_RXCTL||IO_L4P_T0_34|-| ETH1_MDC||IO_L9N_T1_DQS_34|-| ETH1_MDIO||IO_L9P_T1_DQS_34|-|} Since bank #34 is powered at 3.3V (High Range I/O mode), RGMII duty cycle distortion specification is not matched. In case of carrier board designed for production environments, <u>it is recommended to use a lower voltage levels and thus a different PL bank</u>. For more details please see section ''I/O Standard and Placement'' of [https://docs.xilinx.com/r/en-US/pg160-gmii-to-rgmii/GMII-to-RGMII-v4.1-LogiCORE-IP-Product-Guide ''PG160 GMII to RGMII LogiCORE IP Product Guide''] and [[Power_(Bora)|this page]]. The Vivado project can also be build with the procedure explained [[Creating_and_building_example_Vivado_project_(BELK/BXELK)#Command_line_based_procedure|here]]. ===BoraLite + Adapter + BoraXEVB===On BoraXEVB PHY1 is interfaced to Programmable Logic (PL) pads that belong to bank #13. The BoraLite Adapter take care of rerouting the ETH1_RXCK to meet the Vivado requirements. Here is the pinout assignment for the PHY1 on BoraXEVB:{| class="wikitable" | | align="center" style="background:#f0f0f0;"|'''PHY1 Signal'''| align="center" style="background:#f0f0f0;"|'''BORAX SOM Signal'''|-| ETH1_TXD0||IO_L19P_T3_13|-| ETH1_TXD1||IO_L19N_T3_VREF_13|-| ETH1_TXD2||IO_L20P_T3_13|-| ETH1_TXD3||IO_L20N_T3_13|-| ETH1_TXCK||IO_L16P_T2_13|-| ETH1_TXCTL||IO_L16N_T2_13|-| ETH1_RXD0||IO_L17P_T2_13|-| ETH1_RXD1||IO_L17N_T2_13|-| ETH1_RXD2||IO_L18P_T2_13|-| ETH1_RXD3||IO_L18N_T2_13|-| ETH1_RXCK||IO_L14P_T2_SRCC_13|-| ETH1_RXCTL||IO_L14N_T2_SRCC_13|-| ETH1_MDC||IO_L21N_T3_DQS_13|-| ETH1_MDIO||IO_L21P_T3_DQS_13|-|} I/O voltage of bank 13 must be set to 2.5V by configuring [[BoraXEVB#BANK13_VDDIO_selector_-_JP25|JP25 ]] as shown in the following table.{| class="wikitable" border="1"!Pins!Setting|-|1-2|closed|-|3-4|open|-|5-6|closed|-|7-8|open|-|9-10|open|-|11-12|open|-|} The Vivado project can also be build with the procedure explained [[Creating_and_building_example_Vivado_project_(BELK/BXELK)#Command_line_based_procedure|here]]. ===Borax + BoraXEVB===On BoraXEVB PHY1 is interfaced to Programmable Logic (PL) pads that belong to bank #13. '''WARNING:''' due to a restraint introduced, from Vivado version 2017.1 onwards, the signal ETH1_TXCK can be routed only to a pad that is MRCC or SRCC input. As result from BXELK 2.0.0 an hardware rework is needed on the BoraXEVB board:* Remove RP84* Remove R232* Connect RP84.2 with R232.1 This rework prevents the use of the LVDS connector on BoraXEVB (J26). Here is the pinout assignment for the PHY1 on BoraXEVB:{| class="wikitable" | | align="center" style="background:#f0f0f0;"|'''PHY1 Signal'''| align="center" style="background:#f0f0f0;"|'''BORAX SOM Signal'''|-| ETH1_TXD0||IO_L19P_T3_13|-| ETH1_TXD1||IO_L19N_T3_VREF_13|-| ETH1_TXD2||IO_L20P_T3_13|-| ETH1_TXD3||IO_L20N_T3_13|-| ETH1_TXCK||IO_L16P_T2_13|-| ETH1_TXCTL||IO_L16N_T2_13|-| ETH1_RXD0||IO_L17P_T2_13|-| ETH1_RXD1||IO_L17N_T2_13|-| ETH1_RXD2||IO_L18P_T2_13|-| ETH1_RXD3||IO_L18N_T2_13|-| ETH1_RXCK||<span style="text-decoration: line-through;">IO_L15P_T2_DQS_13</span> IO_L12P_T1_MRCC_13|-| ETH1_RXCTL||IO_L15N_T2_DQS_13|-| ETH1_MDC||IO_L21N_T3_DQS_13|-| ETH1_MDIO||IO_L21P_T3_DQS_13|-|} I/O voltage of bank 13 must be set to 2.5V by configuring [[BoraXEVB#BANK13_VDDIO_selector_-_JP25|JP25 ]] as shown in the following table.{| class="wikitable" border="1"!Pins!Setting|-|1-2|closed|-|3-4|open|-|5-6|closed|-|7-8|open|-|9-10|open|-|11-12|open|-|} The Vivado project can also be build with the procedure explained [[Creating_and_building_example_Vivado_project_(BELK/BXELK)#Command_line_based_procedure|here]].
==Enabling dual Ethernet configuration in linux kernel==
To enable frame buffer driver dual Ethernet user need needs to:* get the pre-built binaries from this [http[BELK-AN-006:_Enabling_dual_Gigabit_Ethernet_support_on_BoraEVB//www.dave.eu/system/files/areaBoraXEVB#Pre-riservatabuilt_binaries |here]] Alternatively kernel and device tree can be built from sources with the following procedure:* update Bora kernel repository (as described [[BELK/AN-BELK-005BXELK_software_components#Updating_git_repositories|here]])* build the <code>bora-swan006.zip link]dtb</code> devicetree* build the updated kernel source as usual.
eth1 Link encap:Ethernet HWaddr 66:94:55:CB:B1:3E
BROADCAST MULTICAST MTU:1500 Metric:1
RX packets:0 errors:0 dropped:0 overruns:0 frame:0
TX packets:0 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:1000
RX bytes:0 (0.0 B) TX bytes:0 (0.0 B)
Interrupt:77 Base address:0xc000
lo Link encap:Local Loopback
inet addr:127.0.0.1 Mask:255.0.0.0
UP LOOPBACK RUNNING MTU:65536 Metric:1
RX packets:11 errors:0 dropped:0 overruns:0 frame:0
TX packets:11 errors:0 dropped:0 overruns:0 carrier:0
collisions:0 txqueuelen:0
RX bytes:788 (788.0 B) TX bytes:788 (788.0 B)
root@bora:~# ifconfig eth1 192.168.12.209
root@bora:~# [ 228.492886] xemacps e000c000.ethernet: Set clk to 0 Hz
[ 228.498079] xemacps e000c000.ethernet: link up (1000/FULL)
root@bora:~#
</pre>
=== Pre-built binaries ===
* For Bora SoM use:
** [http://mirror.dave.eu/bora/belk-4.1.0/belk-4.1.1_bora_mmc_an006_boot.bin u-boot (SPL)]
** [http://mirror.dave.eu/bora/belk-4.1.0/belk-4.1.1_bora_mmc_an006_u-boot.img u-boot (img)]
** [http://mirror.dave.eu/bora/belk-4.1.0/belk-4.1.0_uImage uImage]
** [http://mirror.dave.eu/bora/belk-4.1.0/belk-4.1.0_bora-an006.dtb dtb]
** [http://mirror.dave.eu/bora/belk-4.1.0/belk-4.1.0_bora_ETH1_fpga.bit fpga]
* For BoraLite SoM use:
** [http://mirror.dave.eu/bora/belk-4.1.0/belk-4.1.1_bora_mmc_an006_boot.bin u-boot (SPL)]
** [http://mirror.dave.eu/bora/belk-4.1.0/belk-4.1.1_bora_mmc_an006_u-boot.img u-boot (img)]
** [http://mirror.dave.eu/bora/belk-4.1.0/belk-4.1.0_uImage uImage]
** [http://mirror.dave.eu/bora/belk-4.1.0/belk-4.1.0_bora-an006.dtb dtb]
** [http://mirror.dave.eu/bora/belk-4.1.0/belk-4.1.0_boralite_ETH1_fpga.bit fpga]
* For BoraX SoM use:
** [http://mirror.dave.eu/bora/belk-4.1.0/belk-4.1.1_borax_mmc_an006_boot.bin u-boot (SPL)]
** [http://mirror.dave.eu/bora/belk-4.1.0/belk-4.1.1_borax_mmc_an006_u-boot.img u-boot (img)]
** [http://mirror.dave.eu/bora/belk-4.1.0/belk-4.1.0_uImage uImage]
** [http://mirror.dave.eu/bora/belk-4.1.0/belk-4.1.0_bora-an006.dtb dtb]
** [http://mirror.dave.eu/bora/belk-4.1.0/belk-4.1.0_borax_ETH1_fpga.bit fpga]
===Performance tests===
To test the performances of the second Ethernet interface <code>iperf</code> based tests have been executed.
====Test #1====
In this test bed the two interfaces are connected on the same host machine (a PC running linux) via a Gigabit switch but are associated to two different subnets:
* ETH0: 192.168.0.xxx
* ETH1: 192.168.12.xxx
On the linux host machine <code>iperf</code> application is run in server mode:
<pre>
</pre>