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!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History
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The following picture shows the simplified block diagram of reset scheme and voltage monitoring.
[[File:AXEL LiteAxel-lite-reset-scheme-BOOT MODE SEL.png | 800px]] ''TBD: qui di seguito vanno inserite le sezioni che includano la descrizione dei segnali coinvolti nella fase di Reset, ad esempio: * MRST* POR* SNVS* SYSRST* ...''' '''TBD: indicare le connessioni del segnale di reset verso altri device interni (come per esempio la NOR SPI''' ''TBD: di seguito la pagina di AXEL Lite da rivedere nel caso di altri SOM''
=== PMIC_VSNVS ===
For these reasons, it is strongly recommended to use a different approach that, in combination with the use of a processor's watchdog timer (WDT), provides a full hardware reset in case a software reset is issued.
This technique is implemented in [[DESK-MX6-L]]. At software level, U-Boot and Linux kernel software reset routines make use of processor's WDT #2 to assert the WDOG2_B reset signal. This signal in turn is routed to GPIO_1 pad (MUX mode = 1). At hardware level, this signal is AC-coupled to a 3-state output buffer (please refer to U22 U46 chip of [[AxelEVB-AXEL_Lite_SOM/AXEL_Lite_Evaluation_Kit/Electrical_and_Mechanical_Documents/Schematics#Schematics | AXEL LiteEvaluation_Kit]] carrier board), driving PMIC_PWRON.
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[[Category:AXEL Lite]]