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AXEL Lite SOM/AXEL Lite Hardware/Pinout Table

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<section begin="History" />
{| style="border-collapse:collapse; "
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Version
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
|-
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |1.0.0{{oldid| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" 13761|Sep 2020/12/18}}
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |New documentation layout
|-
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |{{oldid|15218|2021/11/17}}| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |More details about BOOT_MODE_SEL signal|-! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |2021/11/26! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |Voltage domains legend added. Fixed the "Type" field of ETH0_LED1 and ETH0_LED2.
|}
<section end="History" /><section begin="Body" />
==Connectors and Pinout Table==
|TE Connectivity 2-2013289-1
|}
The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to MITO 8M AXEL Lite pinout specifications. See the images below for reference: [[File:AXEL_Lite-top.png|500px|thumb|AXEL Lite TOP view|none]][[File:AXEL_Lite-bottom.png|500px|thumb|AXEL Lite BOTTOM view|none]]
[[File:AXEL_Lite-top-pin1-203.png|500px|thumb|AXEL Lite TOP view|none]]
[[File:AXEL_Lite-bottom-pin2-204.png|500px|thumb|AXEL Lite BOTTOM view|none]]
===Pinout table naming conventions ===
Each row in the pinout tables contains the following information:
{| class="wikitable" style="width:50%;"
|-
|'''Pin'''
| Component ball/pin number connected to signal
|-
|'''Voltagedomain''' || I/O The voltage levels domain the pin belongs to
|-
|'''Type'''
* Pin ALT-7
* Pin ALT-8
|-
|}
 
===Voltage domains ===
 
{| class="wikitable"
! latexfontsize="scriptsize" | Voltage domain
! latexfontsize="scriptsize" | Nominal voltage [V]
! latexfontsize="scriptsize" | Notes
|-
|3.3VIN
|3.3
|See [[AXEL_Lite_SOM/AXEL_Lite_Hardware/Electrical_Thermal_and_Mechanical_Features/Operational_characteristics#Recommended_ratings|Operational_characteristics]] of the SoM wiki page
|-
|VCC_ENET_1V8
|1.8
|Voltage generated by the internal PSU. See [[AXEL_Lite_SOM/AXEL_Lite_Hardware/Power_and_Reset/Power_Supply_Unit_(PSU)_and_recommended_power-up_sequence | Power Supply Unit (PSU)]] wiki page
|-
|AXEL_IO_3V3
|3.3
|Voltage generated by the internal PSU. See [[AXEL_Lite_SOM/AXEL_Lite_Hardware/Power_and_Reset/Power_Supply_Unit_(PSU)_and_recommended_power-up_sequence | Power Supply Unit (PSU)]] wiki page
|-
|GEN_2V5
|2.5
|Voltage generated by the internal PSU. See [[AXEL_Lite_SOM/AXEL_Lite_Hardware/Power_and_Reset/Power_Supply_Unit_(PSU)_and_recommended_power-up_sequence | Power Supply Unit (PSU)]] wiki page
|-
|}
! latexfontsize="scriptsize" | Internal Connections
! latexfontsize="scriptsize" | Ball/pin #
! latexfontsize="scriptsize" |<nowiki> Voltage|domain</nowiki>
! latexfontsize="scriptsize" | Type
! latexfontsize="scriptsize" | Notes
|17
|VCC_ENET_1V8
|DO| This signal is @ 1.8V and should be |Internal 10k pull-up to 1.8VThis signal requires voltage level translated shifters if used @ 3V3at 3.3V
|
|
|15
|VCC_ENET_1V8
|DO| This signal is @ 1.8V and should be |Internal 10k pull-up to 1.8VThis signal requires voltage level translated shifters if used @ 3V3at 3.3V
|
|
|
|
* If this power supply is not used, the pin can be left open.
* Even if this power supply is not used, NXP recommends to connect a capacitor. A 100nF capacitor is connected on the SoM.
|
|
|
|
|This is a pulled-up input. Leave unconnected to select "1". Connect to ground to select "0". For more details, please see also the following pages:* [[AXEL_Lite_SOM/AXEL_Lite_Hardware/Power_and_Reset/Reset_scheme_and_control_signals | Reset scheme and control signals]]* [[AXEL_Lite_SOM/AXEL_Lite_Hardware/Power_and_Reset/System_boot | System boot]]
|
|
|-
|J2.22
|CPU_PORNCPU_PORn|CPU.CPU_PORNCPU_PORn
|C11
|
| rowspan="7" |AXEL_IO_3V3
| rowspan="7" |IO
| rowspan="7" |[[AXEL_Lite_SOM/AXEL_Lite_Hardware/Power_and_Reset/Reset_scheme_and_control_signals#Handling_CPU-initiated_software_reset | Reset_scheme_and_control_signals#Handling_CPU-initiated_software_reset]]
|Pin ALT-0
|ESAI_RX_CLK
|KEY_COL5
|-
|Pin ALT-21
|ENET_1588_EVENT0_OUT
|-
|Pin ALT-32
|SPDIF_OUT
|-
|Pin ALT-43
|CCM_CLKO1
|-
|Pin ALT-54
|ECSPI1_RDY
|-
|Pin ALT-65
|GPIO4_IO05
|-
|????????????Pin ALT-6
|ENET_TX_ER
|-
|ARM_TRACE_CLK
|-
| rowspan="87" |J2.66| rowspan="87" |CSI0_DAT4| rowspan="87" |CPU.CSI0_DAT4| rowspan="87" |N1| rowspan="87" |AXEL_IO_3V3| rowspan="87" |IO| rowspan="87" |
|Pin ALT-0
|IPU1_CSI0_DATA04
|Pin ALT-5
|GPIO5_IO22
|-
|Pin ALT-6
|?????????????
|-
|Pin ALT-7
|
|-
| rowspan="4" |J2.124| rowspan="4" |DI0_PIN15| rowspan="4" |CPU.DI0_PIN15| rowspan="4" |N21| rowspan="4" |AXEL_IO_3V3| rowspan="4" |IO| rowspan="4" ||Pin ALT-0|IPU1_DI0_PIN15
|-
|J2.126|DI0_PIN4|CPU.DI0_PIN4|P25|AXEL_IO_3V3|IO||Pin ALT-1|IPU2_DI0_PIN15
|-
|J2.128|DI0_PIN3|CPU.DI0_PIN3|N20|AXEL_IO_3V3|IO||Pin ALT-2|AUD6_TXC
|-
|J2.130|DI0_PIN2|CPU.DI0_PIN2|N25|AXEL_IO_3V3|IO||Pin ALT-5|GPIO4_IO17
|-
| rowspan="4" |J2.132126|DI0_DISP_CLKrowspan="4" |DI0_PIN4| rowspan="4" |CPU.DI0_DISP_CLKDI0_PIN4|N19rowspan="4" |P25| rowspan="4" |AXEL_IO_3V3| rowspan="4" |IO| rowspan="4" ||Pin ALT-0|IPU1_DI0_PIN04
|-
|J2.134Pin ALT-1|DISP0_DAT0|CPU.DISP0_DAT0|P24|AXEL_IO_3V3|IOIPU2_DI0_PIN04|-|Pin ALT-2|AUD6_RXD
|-
|J2.136|DISP0_DAT1|CPU.DISP0_DAT1|P22|AXEL_IO_3V3|IO||Pin ALT-5|GPIO4_IO20
|-
| rowspan="4" |J2.138128|DISP0_DAT2rowspan="4" |DI0_PIN3| rowspan="4" |CPU.DISP0_DAT2DI0_PIN3|P23rowspan="4" |N20| rowspan="4" |AXEL_IO_3V3| rowspan="4" |IO| rowspan="4" ||Pin ALT-0|IPU1_DI0_PIN03
|-
|J2.140|DISP0_DAT3|CPU.DISP0_DAT3|P21|AXEL_IO_3V3|IO||Pin ALT-1|IPU2_DI0_PIN03
|-
|J2.142|DISP0_DAT4|CPU.DISP0_DAT4|P20|AXEL_IO_3V3|IO||Pin ALT-2|AUD6_TXFS
|-
|J2.144|DISP0_DAT5|CPU.DISP0_DAT5|R25|AXEL_IO_3V3|IO||Pin ALT-5|GPIO4_IO19
|-
| rowspan="4" |J2.146130|DGNDrowspan="4" |DI0_PIN2|DGNDrowspan="4" |CPU.DI0_PIN2| -rowspan="4" |N25| rowspan="4" |AXEL_IO_3V3| rowspan="4" |IO| rowspan="4" || Pin ALT-0|GIPU1_DI0_PIN02|-|Pin ALT-1|IPU2_DI0_PIN02
|-
|J2.148|DISP0_DAT6|CPU.DISP0_DAT6|R23|AXEL_IO_3V3|IO||Pin ALT-2|AUD6_TXD
|-
|J2.150|DISP0_DAT7|CPU.DISP0_DAT7|R24|AXEL_IO_3V3|IO||Pin ALT-5|GPIO4_IO18
|-
| rowspan="3" |J2.152132|DISP0_DAT8rowspan="3" |DI0_DISP_CLK| rowspan="3" |CPU.DISP0_DAT8DI0_DISP_CLK|R22rowspan="3" |N19| rowspan="3" |AXEL_IO_3V3| rowspan="3" |IO| rowspan="3" ||Pin ALT-0|IPU1_DI0_DISP_CLK
|-
|J2.154|DISP0_DAT9|CPU.DISP0_DAT9|T25|AXEL_IO_3V3|IO||Pin ALT-1|IPU2_DI0_DISP_CLK
|-
|J2.156|DISP0_DAT10|CPU.DISP0_DAT10|R21|AXEL_IO_3V3|IO||Pin ALT-5|GPIO4_IO16
|-
| rowspan="4" |J2.158134|DISP0_DAT11rowspan="4" |DISP0_DAT0| rowspan="4" |CPU.DISP0_DAT11DISP0_DAT0|T23rowspan="4" |P24| rowspan="4" |AXEL_IO_3V3| rowspan="4" |IO| rowspan="4" ||Pin ALT-0|IPU1_DISP0_DATA00
|-
|J2.160|DISP0_DAT12|CPU.DISP0_DAT12|T24|AXEL_IO_3V3|IO||Pin ALT-1|IPU2_DISP0_DATA00
|-
|J2.162|DISP0_DAT13|CPU.DISP0_DAT13|R20|AXEL_IO_3V3|IO||Pin ALT-2|ECSPI3_SCLK
|-
|J2.164|DGND|DGND| Pin ALT-5| -|G|||GPIO4_IO21
|-
| rowspan="4" |J2.166136|DISP0_DAT14rowspan="4" |DISP0_DAT1| rowspan="4" |CPU.DISP0_DAT14DISP0_DAT1|U25rowspan="4" |P22| rowspan="4" |AXEL_IO_3V3| rowspan="4" |IO| rowspan="4" ||Pin ALT-0|IPU1_DISP0_DATA01
|-
|J2.168|DISP0_DAT15|CPU.DISP0_DAT15|T22|AXEL_IO_3V3|IO||Pin ALT-1|IPU2_DISP0_DATA01
|-
|J2.170|DISP0_DAT16|CPU.DISP0_DAT16|T21|AXEL_IO_3V3|IO||Pin ALT-2|ECSPI3_MOSI
|-
|J2.172|DISP0_DAT17|CPU.DISP0_DAT17|U24|AXEL_IO_3V3|IO||Pin ALT-5|GPIO4_IO22
|-
| rowspan="4" |J2.174138|DISP0_DAT18rowspan="4" |DISP0_DAT2| rowspan="4" |CPU.DISP0_DAT18DISP0_DAT2|V25rowspan="4" |P23| rowspan="4" |AXEL_IO_3V3| rowspan="4" |IO| rowspan="4" ||Pin ALT-0|IPU1_DISP0_DATA02
|-
|J2.176|DISP0_DAT19|CPU.DISP0_DAT19|U23|AXEL_IO_3V3|IO||Pin ALT-1|IPU2_DISP0_DATA02
|-
|J2.178|DISP0_DAT20|CPU.DISP0_DAT20|U22|AXEL_IO_3V3|IO||Pin ALT-2|ECSPI3_MISO
|-
|J2.180|DISP0_DAT21|CPU.DISP0_DAT21|T20|AXEL_IO_3V3|IO||Pin ALT-5|GPIO4_IO23
|-
| rowspan="4" |J2.182140|DISP0_DAT22rowspan="4" |DISP0_DAT3| rowspan="4" |CPU.DISP0_DAT22DISP0_DAT3|V24rowspan="4" |P21| rowspan="4" |AXEL_IO_3V3| rowspan="4" |IO| rowspan="4" ||Pin ALT-0|IPU1_DISP0_DATA03
|-
|J2.184|DISP0_DAT23|CPU.DISP0_DAT23|W24|AXEL_IO_3V3|IO||Pin ALT-1|IPU2_DISP0_DATA03
|-
|J2.186|USB_OTG_VBUS|CPU.USB_OTG_VBUS|E9||||Pin ALT-2|ECSPI3_SS0
|-
|J2.188|USB_H1_VBUS|CPU.USB_H1_VBUS|D10||||Pin ALT-5|GPIO4_IO24
|-
| rowspan="4" |J2.190142| rowspan="4" |DISP0_DAT4| rowspan="4" |CPU.DISP0_DAT4| rowspan="4" |P20| rowspan="4" |AXEL_IO_3V3| rowspan="4" |IO| rowspan="4" ||Pin ALT-0|IPU1_DISP0_DATA04|-|Pin ALT-1|IPU2_DISP0_DATA04|-|Pin ALT-2|ECSPI3_SS1|-|Pin ALT-5|GPIO4_IO25|-| rowspan="5" |J2.144| rowspan="5" |DISP0_DAT5| rowspan="5" |CPU.DISP0_DAT5| rowspan="5" |P24| rowspan="5" |AXEL_IO_3V3| rowspan="5" |IO| rowspan="5" ||Pin ALT-0|IPU1_DISP0_DATA05|-|Pin ALT-1|IPU2_DISP0_DATA05|-|Pin ALT-2|ECSPI3_SS2|-|Pin ALT-3|AUD6_RXFS|-|Pin ALT-5|GPIO4_IO26|-|J2.146
|DGND
|DGND
| -
| -
|G
|
|
|-
| rowspan="5" |J2.192148|ENET_RX_ERrowspan="5" |DISP0_DAT6| rowspan="5" |CPU.ENET_RX_ERDISP0_DAT6|W23rowspan="5" |R23|VCC_ENET_1V8rowspan="5" |AXEL_IO_3V3| rowspan="5" |IO|This pin is 1V8 tolerant (i.e. must be connected to a 1V8 power domain)rowspan="5" ||Pin ALT-0|IPU1_DISP0_DATA06
|-
|Pin ALT-1|IPU2_DISP0_DATA06|-|Pin ALT-2|ECSPI3_SS3|-|Pin ALT-3|AUD6_RXC|-|Pin ALT-5|GPIO4_IO27|-| rowspan="4" |J2.150| rowspan="4" |DISP0_DAT7| rowspan="4" |CPU.DISP0_DAT7| rowspan="4" |R24| rowspan="4" |AXEL_IO_3V3| rowspan="4" |IO| rowspan="4" ||Pin ALT-0|IPU1_DISP0_DATA07|-|Pin ALT-1|IPU2_DISP0_DATA07|-|Pin ALT-2|ECSPI3_RDY|-|Pin ALT-5|GPIO4_IO28|-| rowspan="5" |J2.152| rowspan="5" |DISP0_DAT8| rowspan="5" |CPU.DISP0_DAT8| rowspan="5" |R22| rowspan="5" |AXEL_IO_3V3| rowspan="5" |IO| rowspan="5" ||Pin ALT-0|IPU1_DISP0_DATA08|-|Pin ALT-1|IPU2_DISP0_DATA08|-|Pin ALT-2|PWM1_OUT|-|Pin ALT-3|WDOG1_B|-|Pin ALT-5|GPIO4_IO29|-| rowspan="5" |J2.194154|ENET_RXD0rowspan="5" |DISP0_DAT9| rowspan="5" |CPU.ENET_RXD0DISP0_DAT9|W21rowspan="5" |T25|VCC_ENET_1V8rowspan="5" |AXEL_IO_3V3| rowspan="5" |IO|This pin is 1V8 tolerant (irowspan="5" ||Pin ALT-0|IPU1_DISP0_DATA09|-|Pin ALT-1|IPU2_DISP0_DATA09|-|Pin ALT-2|PWM2_OUT|-|Pin ALT-3|WDOG2_B|-|Pin ALT-5|GPIO4_IO30|-| rowspan="3" |J2.e156| rowspan="3" |DISP0_DAT10| rowspan="3" |CPU. must be connected to a 1V8 power domain)DISP0_DAT10| rowspan="3" |R21| rowspan="3" |AXEL_IO_3V3| rowspan="3" |IO| rowspan="3" ||Pin ALT-0|IPU1_DISP0_DATA10|-|Pin ALT-1|IPU2_DISP0_DATA10|-|Pin ALT-5|GPIO4_IO31|-| rowspan="3" |J2.158| rowspan="3" |DISP0_DAT11| rowspan="3" |CPU.DISP0_DAT11| rowspan="3" |T23| rowspan="3" |AXEL_IO_3V3| rowspan="3" |IO| rowspan="3" ||Pin ALT-0|IPU1_DISP0_DATA11|-|Pin ALT-1|IPU2_DISP0_DATA11|-|Pin ALT-5|GPIO5_IO05|-| rowspan="3" |J2.160| rowspan="3" |DISP0_DAT12| rowspan="3" |CPU.DISP0_DAT12| rowspan="3" |T24| rowspan="3" |AXEL_IO_3V3| rowspan="3" |IO| rowspan="3" ||Pin ALT-0|IPU1_DISP0_DATA12|-|Pin ALT-1|IPU2_DISP0_DATA12|-|Pin ALT-5|GPIO5_IO06|-| rowspan="4" |J2.162| rowspan="4" |DISP0_DAT13| rowspan="4" |CPU.DISP0_DAT13| rowspan="4" |R20| rowspan="4" |AXEL_IO_3V3| rowspan="4" |IO| rowspan="4" ||Pin ALT-0|IPU1_DISP0_DATA13|-|Pin ALT-1|IPU2_DISP0_DATA13|-|Pin ALT-3|AUD5_RXFS|-|Pin ALT-5|GPIO5_IO07|-|J2.164|DGND|DGND| -| -|G
|
|
|
|-
| rowspan="4" |J2.166
| rowspan="4" |DISP0_DAT14
| rowspan="4" |CPU.DISP0_DAT14
| rowspan="4" |U25
| rowspan="4" |AXEL_IO_3V3
| rowspan="4" |IO
| rowspan="4" |
|Pin ALT-0
|IPU1_DISP0_DATA14
|-
|Pin ALT-1
|IPU2_DISP0_DATA14
|-
|Pin ALT-3
|AUD5_RXC
|-
|Pin ALT-5
|GPIO5_IO08
|-
| rowspan="5" |J2.168
| rowspan="5" |DISP0_DAT15
| rowspan="5" |CPU.DISP0_DAT15
| rowspan="5" |T22
| rowspan="5" |AXEL_IO_3V3
| rowspan="5" |IO
| rowspan="5" |
|Pin ALT-0
|IPU1_DISP0_DATA15
|-
|Pin ALT-1
|IPU2_DISP0_DATA15
|-
|Pin ALT-2
|ECSPI1_SS1
|-
|Pin ALT-3
|ECSPI2_SS1
|-
|Pin ALT-5
|GPIO5_IO09
|-
| rowspan="6" |J2.170
| rowspan="6" |DISP0_DAT16
| rowspan="6" |CPU.DISP0_DAT16
| rowspan="6" |T21
| rowspan="6" |AXEL_IO_3V3
| rowspan="6" |IO
| rowspan="6" |
|Pin ALT-0
|IPU1_DISP0_DATA16
|-
|Pin ALT-1
|IPU2_DISP0_DATA16
|-
|Pin ALT-2
|ECSPI2_MOSI
|-
|Pin ALT-3
|AUD5_TXC
|-
|Pin ALT-4
|SDMA_EXT_EVENT0
|-
|Pin ALT-5
|GPIO5_IO10
|-
| rowspan="6" |J2.172
| rowspan="6" |DISP0_DAT17
| rowspan="6" |CPU.DISP0_DAT17
| rowspan="6" |U24
| rowspan="6" |AXEL_IO_3V3
| rowspan="6" |IO
| rowspan="6" |
|Pin ALT-0
|IPU1_DISP0_DATA17
|-
|Pin ALT-1
|IPU2_DISP0_DATA17
|-
|Pin ALT-2
|ECSPI2_MISO
|-
|Pin ALT-3
|AUD5_TXD
|-
|Pin ALT-4
|SDMA_EXT_EVENT1
|-
|Pin ALT-5
|GPIO5_IO11
|-
| rowspan="6" |J2.174
| rowspan="6" |DISP0_DAT18
| rowspan="6" |CPU.DISP0_DAT18
| rowspan="6" |V25
| rowspan="6" |AXEL_IO_3V3
| rowspan="6" |IO
| rowspan="6" |
|Pin ALT-0
|IPU1_DISP0_DATA18
|-
|Pin ALT-1
|IPU2_DISP0_DATA18
|-
|Pin ALT-2
|ECSPI2_SS0
|-
|Pin ALT-3
|AUD5_TXFS
|-
|Pin ALT-4
|AUD4_RXFS
|-
|Pin ALT-5
|GPIO5_IO12
|-
| rowspan="6" |J2.176
| rowspan="6" |DISP0_DAT19
| rowspan="6" |CPU.DISP0_DAT19
| rowspan="6" |U23
| rowspan="6" |AXEL_IO_3V3
| rowspan="6" |IO
| rowspan="6" |
|Pin ALT-0
|IPU1_DISP0_DATA19
|-
|Pin ALT-1
|IPU2_DISP0_DATA19
|-
|Pin ALT-2
|ECSPI2_SCLK
|-
|Pin ALT-3
|AUD5_RXD
|-
|Pin ALT-4
|AUD4_RXC
|-
|Pin ALT-5
|GPIO5_IO13
|-
| rowspan="5" |J2.178
| rowspan="5" |DISP0_DAT20
| rowspan="5" |CPU.DISP0_DAT20
| rowspan="5" |U22
| rowspan="5" |AXEL_IO_3V3
| rowspan="5" |IO
| rowspan="5" |
|Pin ALT-0
|IPU1_DISP0_DATA20
|-
|Pin ALT-1
|IPU2_DISP0_DATA20
|-
|Pin ALT-2
|ECSPI1_SCLK
|-
|Pin ALT-3
|AUD4_TXC
|-
|Pin ALT-5
|GPIO5_IO14
|-
| rowspan="5" |J2.180
| rowspan="5" |DISP0_DAT21
| rowspan="5" |CPU.DISP0_DAT21
| rowspan="5" |T20
| rowspan="5" |AXEL_IO_3V3
| rowspan="5" |IO
| rowspan="5" |
|Pin ALT-0
|IPU1_DISP0_DATA21
|-
|Pin ALT-1
|IPU2_DISP0_DATA21
|-
|Pin ALT-2
|ECSPI1_MOSI
|-
|Pin ALT-3
|AUD4_TXD
|-
|Pin ALT-5
|GPIO5_IO15
|-
| rowspan="5" |J2.182
| rowspan="5" |DISP0_DAT22
| rowspan="5" |CPU.DISP0_DAT22
| rowspan="5" |V24
| rowspan="5" |AXEL_IO_3V3
| rowspan="5" |IO
| rowspan="5" |
|Pin ALT-0
|IPU1_DISP0_DATA22
|-
|Pin ALT-1
|IPU2_DISP0_DATA22
|-
|Pin ALT-2
|ECSPI1_MISO
|-
|Pin ALT-3
|AUD4_TXFS
|-
|Pin ALT-5
|GPIO5_IO16
|-
| rowspan="5" |J2.184
| rowspan="5" |DISP0_DAT23
| rowspan="5" |CPU.DISP0_DAT23
| rowspan="5" |W24
| rowspan="5" |AXEL_IO_3V3
| rowspan="5" |IO
| rowspan="5" |
|Pin ALT-0
|IPU1_DISP0_DATA23
|-
|Pin ALT-1
|IPU2_DISP0_DATA23
|-
|Pin ALT-2
|ECSPI1_SS0
|-
|Pin ALT-3
|AUD4_RXD
|-
|Pin ALT-5
|GPIO5_IO17
|-
|J2.186
|USB_OTG_VBUS
|CPU.USB_OTG_VBUS
|E9
|
|
|
|
|
|-
|J2.188
|USB_H1_VBUS
|CPU.USB_H1_VBUS
|D10
|
|
|
|
|
|-
|J2.190
|DGND
|DGND
| -
| -
|G
|
|
|
|-
| rowspan="6" |J2.192
| rowspan="6" |ENET_RX_ER
| rowspan="6" |CPU.ENET_RX_ER
| rowspan="6" |W23
| rowspan="6" |VCC_ENET_1V8
| rowspan="6" |IO
| rowspan="6" |This pin is 1V8 tolerant (i.e. must be connected to a 1V8 power domain)
|Pin ALT-0
|USB_OTG_ID
|-
|Pin ALT-1
|ENET_RX_ER
|-
|Pin ALT-2
|ESAI_RX_HF_CLK
|-
|Pin ALT-3
|SPDIF_IN
|-
|Pin ALT-4
|ENET_1588_EVENT2_OUT
|-
|Pin ALT-5
|GPIO1_IO24
 
|-
| rowspan="4" |J2.194
| rowspan="4" |ENET_RXD0
| rowspan="4" |CPU.ENET_RXD0
| rowspan="4" |W21
| rowspan="4" |VCC_ENET_1V8
| rowspan="4" |IO
| rowspan="4" |This pin is 1V8 tolerant (i.e. must be connected to a 1V8 power domain)
|Pin ALT-1
|ENET_RX_DATA0
|-
|Pin ALT-2
|ESAI_TX_HF_CLK
|-
|Pin ALT-3
|SPDIF_OUT
|-
|Pin ALT-5
|GPIO1_IO27
|-
|J2.196
U0007
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