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<section end=History/>
__FORCETOC__
<section begin=Body/>
The Inter IC (I2C) provides functionality of a standard I2C slave and master. The I2C is designed to be compatible with the standard NXP I2C bus protocol.
'''The iMX6 SOC has four I2C bus interfaces, but there is some limitation about''':
* The I2C2 bus is internally used for PMIC and this should be taken into account if using pads J2.101 and J2.103. See Pin mapping tables for connection details.
=== Description ===
* Multimaster operation
* Interrupt-driven, byte-by-byte data transfer
* Arbitration-lost interrupt with automatic mode switching from master to slave
* Start and stop signal generation/detection
** Repeated Start signal generation
* Acknowledge bit generation/detection
* Bus-busy detection
==== Modes and operations ====
The I2C operates primarily in two functional modes: Standard mode and Fast mode.
* In Standard mode, I2C supports the data transfer rates up to 100 kbits/s.
* In Fast mode, data transfer rates up to 400 kbits/s can be achieved. Per block operation, there is no special configuration required for Fast or Standard mode. It is the data transfer rate that distinguishes Standard and Fast mode.
===Pin mapping===