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<section begin="History" />
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This page illustrates the characteristics of the AURA's boot subsystem. Reading of the chapter ''System Boot'' of the ''i.MX 93 Applications Processor Reference Manual'' is highly recommended [[File:TBD1], though. i.MX93 SOC features several options in terms of booting. Such options are detailed in that document.png | center | 400px]]
It is worth remembering that, by default, AURA supports ''Single Boot'' modes (i.e. the Cortex-A55 is the boot core) as detailed in the rest of the document. Other options are available on-demand, however, allowing to implement different configurations. DAVE Embedded Systems' team is available for additional information on this matter. If necessary, please contact [mailto:sales@dave.eu sales@dave.eu].<section end="History" />__FORCETOC__<section begin="Body" />
== System boot ==
The boot process begins at Power On Reset (POR) where the hardware reset logic forces the ARM Cortex-A55 core to begin execution starting from the on-chip boot ROM. The boot ROM:
* determines whether the boot is secure or non-secure
* performs some initialization of the system and clean-ups
=== Boot options ===
* 0: SPI NOR / SD option (SOM code: DAUxxx0xxxxR)
* 1: eMMC / SD option (SOM code: DAUxxx2xxxxRDAUxxx1xxxxR)* 2: SPI NAND / SD option (SOM code: DAUxxx1xxxxRDAUxxx2xxxxR)For both options the selection of an alternative primary boot device from SD/MMC card is determined provided, selectable by driving low the BOOT_MODE_SEL signal as described in . Bootable SD/MMC card connects via the following sections. BOOT_MODE_SEL is latched when processor reset is releasedSD2 (USDHC2) bus.
All boot modes provide 'single boot' mode, meaning that the Cortex-A55 is the first core to boot. In any case, boot process is managed by on-chip boot ROM code that is described in detail in processor's Reference Manual.{| class="wikitable"!Ordering code 'Boot Mode' fileld==== SPI NOR / SD option ====!BOOT_MODE_SELSelection of primary !Primary boot device is determined by the BOOT_MODE_SEL signal as follows:* BOOT_MODE_SEL |-| rowspan= "2" |0|0** primary boot device is SD2 (|SD/MMC card on USDHC2)* boot ROM will try to boot a valid image from the |-|1|FlexSPI NOR on FLEXSPI1|-| rowspan="2" |1|0|SD /MMC card first, and then from the SPI NOR. In case no valid image is found, boot ROM shall enable USB serial download mode automaticallyon USDHC2|-|1|eMMC on USDHC1|-* BOOT_MODE_SEL | rowspan= "2" |2|0|SD/MMC card on USDHC2|-|1 or floating** primary boot device is SPI NOR flash connected to FLEXSPI|FlexSPI NAND on FLEXSPI1** in case no valid image is found in SPI NOR flash, boot ROM shall enable USB serial download mode automatically|}
==== eMMC / SD option =Note on boot signals ===Selection of primary boot device is determined by the BOOT_MODE_SEL signal as follows:* BOOT_MODE_SEL = 0** primary boot device is SD2 (USDHC2)** in case no valid image latched when processor reset CPU_PORn is found in SD cardreleased. Inside the SOM, boot ROM shall enable USB serial download mode automatically * BOOT_MODE_SEL = 1 or floatingis pulled-up with 10 kohm.** primary The iMX93x SoC uses some GPIOs to read the boot device configuration set on the SOM: for this reason the SOM's ports UART1_TXD, UART2_TXD, SAI1_TXFS and SAI1_TXD0 are floating (high impedance) while CPU_PORn signal is eMMC connected to USDHC1low.** in case no valid image is found in eMMC flash, [[File:AURA-boot ROM shall enable USB serial download mode automatically-opt.png | 800px]]
===Note on boot = SPI NAND / SD option ====Selection of primary boot device is determined by the BOOT_MODE_SEL signal as follows:* BOOT_MODE_SEL = 0** primary boot device is SD2 (USDHC2)** in In case no valid image is found in SD card, boot ROM shall enable USB serial download mode automatically * BOOT_MODE_SEL = 1 or floating** primary boot device is SPI NAND flash connected to FLEXSPI** in case no valid image is found in SPI NAND flash, boot ROM shall enable USB serial download mode automaticallyon USB OTG1.
===Important note for ''manufacture mode'' management===
Bootstrap stage has to be intended as the time elapsing between the release of hardware reset (CPU_PORn) and the execution of the first instruction of user code (typically this is the reset vector of U-Boot boot loader).
== References ==[1] NXP, i.MX 93 Applications Processor Reference Manual <section end="Body" />
[[Category:AURA]]