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This page illustrates the characteristics of the AURA's boot subsystem. Reading of the chapter ''System Boot'' of the ''i.MX 93 Applications Processor Reference Manual'' is highly recommended [[File:TBD1], though. i.MX93 SOC features several options in terms of booting. Such options are detailed in that document.png | center | 400px]]
It is worth remembering that, by default, AURA supports ''Single Boot'' modes, i.e. the Cortex-A55 is the boot core. Other options are available on-demand, however, allowing to implement other configurations. DAVE Embedded Systems' team is available for additional information on this matter. If necessary, please contact [mailto:sales@dave.eu sales@dave.eu].<section end="History" />__FORCETOC__<section begin="Body" />
== System boot ==
The boot process begins at Power On Reset (POR) where the hardware reset logic forces the ARM Cortex-A55 core to begin execution starting from the on-chip boot ROM. The boot ROM:
* determines whether the boot is secure or non-secure
* performs some initialization of the system and clean-ups
=== Boot options ===
The default primary boot device is defined at the factory and identified by the 'Boot Mode' fileld field of the ordering code as follows:
* 0: SPI NOR / SD option (SOM code: DAUxxx0xxxxR)
* 1: eMMC / SD option (SOM code: DAUxxx1xxxxR)
|FlexSPI NAND on FLEXSPI1
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=== Note on boot signals ===
Bootstrap stage has to be intended as the time elapsing between the release of hardware reset (CPU_PORn) and the execution of the first instruction of user code (typically this is the reset vector of U-Boot boot loader).
== References ==
[1] NXP, i.MX 93 Applications Processor Reference Manual
<section end="Body" />
[[Category:AURA]]
