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AURA SOM/AURA Hardware/Pinout Table

1,213 bytes added, 25 March
→‎Pinout Table ODD pins declaration: ETH1 controller clarification
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|-
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The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to AURA pinout specifications. See the images below for reference:
[[File:AURA-topSOM_top-pin1-203.png|500px|thumb|AURA TOP view|none]][[File:AURA-bottomSOM_bottom-pin2-204.png|500px|thumb|AURA BOTTOM view|none]]
===Pinout table naming conventions ===
|3.3VIN
|3.3
|See [[AURA_SOM/AXEL_Lite_HardwareAURA_Hardware/Electrical_Thermal_and_Mechanical_Features/Operational_characteristics#Recommended_ratings|Operational_characteristics]] of the SoM wiki page
|-
|NVCC_3V3
|3.3
|Voltage generated by the internal PSU. See [[AURA_SOM/AXEL_Lite_HardwareAURA_Hardware/Power_and_Reset/Power_Supply_Unit_(PSU)_and_recommended_power-up_sequence | Power Supply Unit (PSU)]] wiki page
|-
|VDD_ANA_1V8
|-
|}
 
===Pinout table XLS file ===
For your convenience, please find a spreadsheet with the AURA/MIMX935x pinout and pinmux table [https://www.dave.eu/links/p/hdTvHz4xQ811bdtb here].
==Pinout Table ODD pins declaration ==
|NVCC_3V3
|D
|Connected to ENET_QOS controller
|
|
|NVCC_3V3
|D
|Connected to ENET_QOS controller
|
|
|NVCC_3V3
|D
|Connected to ENET_QOS controller
|
|
|NVCC_3V3
|D
|Connected to ENET_QOS controller
|
|
|NVCC_3V3
|D
|Connected to ENET_QOS controller
|
|
|NVCC_3V3
|D
|Connected to ENET_QOS controller
|
|
|NVCC_3V3
|D
|Connected to ENET_QOS controller
|
|
|NVCC_3V3
|D
|Connected to ENET_QOS controller
|
|
|-
|Pin ALT-1
|TMP5.CH0TPM5_CH0
|-
|Pin ALT-2
|PDM.BIT_STREAM[1]PDM_BIT_STREAM01
|-
|Pin ALT-3
|LCDIF.D[2]DISP_DATA02
|-
|Pin ALT-4
|SPI7.SOUTSPI7_SOUT
|-
|Pin ALT-5
|UART6.CTS_BUART6_CTS_B
|-
|Pin ALT-6
|I2C7.SDAI2C7_SDA
|-
|Pin ALT-7
|FLEXIO1.FLEXIO[6]FLEXIO1_FLEXIO06
|-
| rowspan="8" |J1.45
|-
|Pin ALT-1
|SAI3.RX_BCLKSAI3_RX_BCLK
|-
|Pin ALT-2
|ISI.D[9]CAM_DATA09
|-
|Pin ALT-3
|LCDIF.D[14]DISP_DATA14
|-
|Pin ALT-4
|SPI5.PCS0SPI5_PCS0
|-
|Pin ALT-5
|SPI4.PCS0SPI4_PCS0
|-
|Pin ALT-6
|TMP5.CH2TPM5_CH2
|-
|Pin ALT-7
|FLEXIO1.FLEXIO[18]FLEXIO1_FLEXIO18
|-
| rowspan="8" |J1.47
|-
|Pin ALT-1
|SPI3.SINSPI3_SIN
|-
|Pin ALT-2
|ISI.D[3]CAM_DATA03
|-
|Pin ALT-3
|LCDIF.D[5]DISP_DATA05
|-
|Pin ALT-4
|TMP3.EXTCLKTPM3_EXTCLK
|-
|Pin ALT-5
|UART7.RXUART7_RX
|-
|Pin ALT-6
|I2C7.SCLI2C7_SCL
|-
|Pin ALT-7
|FLEXIO1.FLEXIO[9]FLEXIO1_FLEXIO09
|-
| rowspan="8" |J1.49
|-
|Pin ALT-1
|SPI3.SPCS0SPI3_SPCS0
|-
|Pin ALT-2
|ISI.D[2]CAM_DATA02
|-
|Pin ALT-3
|LCDIF.D[4]DISP_DATA04
|-
|Pin ALT-4
|TMP6.CH0TPM6_CH0
|-
|Pin ALT-5
|UART7.TXUART7_TX
|-
|Pin ALT-6
|I2C7.SDAI2C7_SDA
|-
|Pin ALT-7
|FLEXIO1.FLEXIO[8]FLEXIO1_FLEXIO08
|-
|J1.51
| rowspan="6" |
|Pin ALT-0
|SAI1.TX_SYNCSAI1_TX_SYNC
|-
|Pin ALT-1
|SAI1.TX_DATA[1]SAI1_TX_DATA01
|-
|Pin ALT-2
|SPI1.PCS0SPI1_PCS0
|-
|Pin ALT-3
|-
|Pin ALT-4
|MQS1.LEFTMQS1_LEFT
|-
|Pin ALT-5
|-
|Pin ALT-1
|SPI3.SOUTSPI3_SOUT
|-
|Pin ALT-2
|ISI.D[4]CAM_DATA04
|-
|Pin ALT-3
|LCDIF.D[6]DISP_DATA06
|-
|Pin ALT-4
|TMP4.EXTCLKTPM4_EXTCLK
|-
|Pin ALT-5
|UART7.CTS_BUART7_CTS_B
|-
|Pin ALT-6
|I2C8.SDAI2C8_SDA
|-
|Pin ALT-7
|FLEXIO1.FLEXIO[10]FLEXIO1_FLEXIO10
|-
|J1.57
| rowspan="8" |
|Pin ALT-0
|GPIO2_IO10GPIO2_IO11
|-
|Pin ALT-1
|SPI3.SCLKSPI3_SCLK
|-
|Pin ALT-2
|ISI.D[5]CAM_DATA05
|-
|Pin ALT-3
|LCDIF.D[7]DISP_DATA07
|-
|Pin ALT-4
|TMP5.EXTCLKTPM5_EXTCLK
|-
|Pin ALT-5
|UART7.RTS_BUART7_RTS_B
|-
|Pin ALT-6
|I2C8.SCLI2C8_SCL
|-
|Pin ALT-7
|FLEXIO1.FLEXIO[11]FLEXIO1_FLEXIO11
|-
| rowspan="4" |J1.61
| rowspan="4" |Optionally connected to internal Flex SPI (NOR or NAND option)
|Pin ALT-0
|USDHC3.DATA0USDHC3_DATA0
|-
|Pin ALT-1
|FLEX_SPI.A_DATA[0]FLEXSPI1_A_DATA00
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[22]FLEXIO1_FLEXIO22
|-
|Pin ALT-5
| rowspan="4" |Optionally connected to internal Flex SPI (NOR or NAND option)
|Pin ALT-0
|USDHC3.DATA1USDHC3_DATA1
|-
|Pin ALT-1
|FLEX_SPI.A_DATA[1]FLEXSPI1_A_DATA01
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[23]FLEXIO1_FLEXIO23
|-
|Pin ALT-5
| rowspan="4" |Optionally connected to internal Flex SPI (NOR or NAND option)
|Pin ALT-0
|USDHC3.DATA2USDHC3_DATA2
|-
|Pin ALT-1
|FLEX_SPI.A_DATA[2]FLEXSPI1_A_DATA02
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[24]FLEXIO1_FLEXIO24
|-
|Pin ALT-5
| rowspan="4" |Optionally connected to internal Flex SPI (NOR or NAND option)
|Pin ALT-0
|USDHC3.DATA3USDHC3_DATA3
|-
|Pin ALT-1
|FLEX_SPI.A_DATA[3]FLEXSPI1_A_DATA03
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[25]FLEXIO1_FLEXIO25
|-
|Pin ALT-5
| rowspan="4" |Optionally connected to internal Flex SPI (NOR or NAND option)
|Pin ALT-0
|USDHC3.CMDUSDHC3_CMD
|-
|Pin ALT-1
|FLEX_SPI.A_SS0_BFLEXSPI1_A_SS0_B
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[21]FLEXIO1_FLEXIO21
|-
|Pin ALT-5
| rowspan="4" |Optionally connected to internal Flex SPI (NOR or NAND option)
|Pin ALT-0
|USDHC3.CLKUSDHC3_CLK
|-
|Pin ALT-1
|FLEX_SPI.A_SCLKFLEXSPI1_A_SCLK
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[20]FLEXIO1_FLEXIO20
|-
|Pin ALT-5
| rowspan="5" |
|Pin ALT-0
|USDHC2.DATA0USDHC2_DATA0
|-
|Pin ALT-1
|ENET2.1588_EVENT0_OUTENET1_1588_EVENT0_OUT
|-
|Pin ALT-2
|CAN2.TXCAN2_TX
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[3]FLEXIO1_FLEXIO03
|-
|Pin ALT-5
| rowspan="5" |
|Pin ALT-0
|USDHC2.DATA1USDHC2_DATA1
|-
|Pin ALT-1
|ENET2.1588_EVENT1_INENET1_1588_EVENT1_IN
|-
|Pin ALT-2
|CAN2.RXCAN2_RX
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[4]FLEXIO1_FLEXIO04
|-
|Pin ALT-5
| rowspan="5" |
|Pin ALT-0
|USDHC2.DATA2USDHC2_DATA2
|-
|Pin ALT-1
|ENET2.1588_EVENT1_OUTENET1_1588_EVENT1_OUT
|-
|Pin ALT-2
|MQS1.RIGHTMQS1_RIGHT
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[5]FLEXIO1_FLEXIO05
|-
|Pin ALT-5
| rowspan="5" |
|Pin ALT-0
|USDHC2.DATA3USDHC2_DATA3
|-
|Pin ALT-1
|LPTMR2.ALT1LPTMR2_ALT1
|-
|Pin ALT-2
|MQS1.LEFTMQS1_LEFT
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[6]FLEXIO1_FLEXIO06
|-
|Pin ALT-5
| rowspan="6" |
|Pin ALT-0
|USDHC2.CMDUSDHC2_CMD
|-
|Pin ALT-1
|ENET2.1588_EVENT0_INENET1_1588_EVENT0_IN
|-
|Pin ALT-2
|I3C2.PURI3C2_PUR
|-
|Pin ALT-3
|I3C2.PUR_BI3C2_PUR_B
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[2]FLEXIO1_FLEXIO02
|-
|Pin ALT-5
| rowspan="5" |
|Pin ALT-0
|USDHC2.CLKUSDHC2_CLK
|-
|Pin ALT-1
|ENET_QOS.1588_EVENT0_OUTENET_QOS_1588_EVENT0_OUT
|-
|Pin ALT-2
|I3C2.SDAI3C2_SDA
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[1]FLEXIO1_FLEXIO01
|-
|Pin ALT-5
|-
|Pin ALT-1
|UART3.TXUART3_TX
|-
|Pin ALT-2
|ISI.D[6]CAM_DATA06
|-
|Pin ALT-3
|LCDIF.D[10]DISP_DATA10
|-
|Pin ALT-4
|SPI8.SOUTSPI8_SOUT
|-
|Pin ALT-5
|UART8.CTS_BUART8_CTS_B
|-
|Pin ALT-6
|UART4.TXUART4_TX
|-
|Pin ALT-7
|FLEXIO1.FLEXIO[14]FLEXIO1_FLEXIO14
|-
| rowspan="8" |J1.91
|-
|Pin ALT-1
|UART3.RXUART3_RX
|-
|Pin ALT-2
|ISI.D[7]CAM_DATA07
|-
|Pin ALT-3
|LCDIF.D[11]DISP_DATA11
|-
|Pin ALT-4
|SPI8.SCKSPI8_SCK
|-
|Pin ALT-5
|UART8.RTS_BUART8_RTS_B
|-
|Pin ALT-6
|UART4.RXUART4_RX
|-
|Pin ALT-7
|FLEXIO1.FLEXIO[15]FLEXIO1_FLEXIO15
|-
| rowspan="5" |J1.93
|-
|Pin ALT-1
|UART1.RTS_BUART1_RTS_B
|-
|Pin ALT-2
|SPI2.SCKSPI2_SCK
|-
|Pin ALT-3
|TMP1.CH3TPM1_CH3
|-
|Pin ALT-5
|-
|Pin ALT-1
|UART1.CTS_BUART1_CTS_B
|-
|Pin ALT-2
|SPI2.SOUTSPI2_SOUT
|-
|Pin ALT-3
|TMP1.CH2TPM1_CH2
|-
|Pin ALT-4
|SAI1.MCLKSAI1_MCLK
|-
|Pin ALT-5
| rowspan="5" |
|Pin ALT-0
|USDHC2.VSELECTUSDHC2_VSELECT
|-
|Pin ALT-1
|USHDC2.WPUSHDC2_WP
|-
|Pin ALT-2
|LPTMR2.ALT3LPTMR2_ALT3
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[19]FLEXIO1_FLEXIO19
|-
|Pin ALT-5
| rowspan="4" |
|Pin ALT-0
|USDHC2.RESET_BUSDHC2_RESET_B
|-
|Pin ALT-1
|LPTMR2.ALT2LPTMR2_ALT2
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[7]FLEXIO1_FLEXIO07
|-
|Pin ALT-5
| rowspan="5" |
|Pin ALT-0
|I2C1.SCLI2C1_SCL
|-
|Pin ALT-1
|I3C1.SCLI3C1_SCL
|-
|Pin ALT-2
|UART1.DCB_BUART1_DCB_B
|-
|Pin ALT-3
|TMP2.CH0TPM2_CH0
|-
|Pin ALT-5
| rowspan="5" |
|Pin ALT-0
|I2C1.SDAI2C1_SDA
|-
|Pin ALT-1
|I3C1.SDAI3C1_SDA
|-
|Pin ALT-2
|UART1.RIN_BUART1_RIN_B
|-
|Pin ALT-3
|TMP2.CH1TPM2_CH1
|-
|Pin ALT-5
| rowspan="6" |
|Pin ALT-0
|SAI1.TX_DATA[0]SAI1_TX_DATA00
|-
|Pin ALT-1
|UART2.RTS_BUART2_RTS_B
|-
|Pin ALT-2
|SPI1.SCKSPI1_SCK
|-
|Pin ALT-3
|UART1.DTR_BUART1_DTR_B
|-
|Pin ALT-4
|CAN1.TXCAN1_TX
|-
|Pin ALT-5
| rowspan="6" |
|Pin ALT-0
|SAI1.TX_BCLKSAI1_TX_BCLK
|-
|Pin ALT-1
|UART2.CTS_BUART2_CTS_B
|-
|Pin ALT-2
|SPI1.SINSPI1_SIN
|-
|Pin ALT-3
|UART1.DSR_BUART1_DSR_B
|-
|Pin ALT-4
|CAN1.RXCAN1_RX
|-
|Pin ALT-5
| rowspan="1" |
|Pin ALT-0
|ANAMIX.ADC_IN0
|-
| rowspan="1" |J1.113
| rowspan="1" |
|Pin ALT-0
|ANAMIX.ADC_IN1
|-
| rowspan="1" |J1.115
| rowspan="1" |
|Pin ALT-0
|ANAMIX.ADC_IN2
|-
| rowspan="1" |J1.117
| rowspan="1" |
|Pin ALT-0
|ANAMIX.ADC_IN3
|-
|J1.119
| rowspan="5" |
|Pin ALT-0
|I2C2.SDAI2C2_SDA
|-
|Pin ALT-3
|UART2.RIN_BUART2_RIN_B
|-
|Pin ALT-4
|TMP2.CH3TPM2_CH3
|-
|Pin ALT-5
|SAI1.RX_BCLKSAI1_RX_BCLK
|-
|Pin ALT-5
| rowspan="7" |
|Pin ALT-0
|I2C2.SCLI2C2_SCL
|-
|Pin ALT-1
|I3C1.PURI3C1_PUR
|-
|Pin ALT-3
|UART2.DCB_BUART2_DCB_B
|-
|Pin ALT-4
|TMP2.CH2TPM2_CH2
|-
|Pin ALT-5
|SAI1.RX_SYNCSAI1_RX_SYNC
|-
|Pin ALT-5
|-
|Pin ALT-6
|I3C1.PUR_BI3C1_PUR_B
|-
|J1.131
| rowspan="5" |
|Pin ALT-0
|USDHC2.CD_BUSDHC2_CD_B
|-
|Pin ALT-1
|ENET_QOS.1588_EVENT0_INENET_QOS_1588_EVENT0_IN
|-
|Pin ALT-2
|I2C3.SCLI2C3_SCL
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[0]FLEXIO1_FLEXIO00
|-
|Pin ALT-5
|-
|Pin ALT-1
|I2C3.SDAI2C3_SDA
|-
|Pin ALT-2
|ISI.PCLKCAM_CLK
|-
|Pin ALT-3
|LCDIF.PCLKDISP_CLK
|-
|Pin ALT-4
|SPI6.PCS0SPI6_PCS0
|-
|Pin ALT-5
|UART5.TXUART5_TX
|-
|Pin ALT-6
|I2C5.SDAI2C5_SDA
|-
|Pin ALT-7
|FLEXIO1.FLEXIO[0]FLEXIO1_FLEXIO00
|-
| rowspan="8" |J1.181
|-
|Pin ALT-1
|I2C4.SCLI2C4_SCL
|-
|Pin ALT-2
|ISI.LINE_VALIDCAM_HSYNC
|-
|Pin ALT-3
|LCDIF.HSYNCDISP_HSYNC
|-
|Pin ALT-4
|SPI6.SCKSPI6_SCK
|-
|Pin ALT-5
|UART5.RTS_BUART5_RTS_B
|-
|Pin ALT-6
|I2C6.SCLI2C6_SCL
|-
|Pin ALT-7
|FLEXIO1.FLEXIO[3]FLEXIO1_FLEXIO03
|-
| rowspan="8" |J1.183
|-
|Pin ALT-1
|I2C3.SCLI2C3_SCL
|-
|Pin ALT-2
|ISI.D[0]CAM_DATA00
|-
|Pin ALT-3
|LCDIF.DEDISP_DE
|-
|Pin ALT-4
|SPI6.SINSPI6_SIN
|-
|Pin ALT-5
|UART5.RXUART5_RX
|-
|Pin ALT-6
|I2C5.SCLI2C5_SCL
|-
|Pin ALT-7
|FLEXIO1.FLEXIO[1]FLEXIO1_FLEXIO01
|-
|J1.185
|-
|Pin ALT-1
|SECO.TXSECO_UART_TX
|-
|Pin ALT-2
|SPI2.PCS0SPI2_PCS0
|-
|Pin ALT-3
|TPM1.CH1TPM1_CH1
|-
|Pin ALT-5
|-
|Pin ALT-1
|SECO.RXSECO_UART_RX
|-
|Pin ALT-2
|SPI2.SINSPI2_SIN
|-
|Pin ALT-3
|TPM1.CH0TPM1_CH0
|-
|Pin ALT-5
|-
|Pin ALT-1
|TPM3.CH2TPM3_CH2
|-
|Pin ALT-2
|PDM.BIT_STREAM[2]PDM_BIT_STREAM02
|-
|Pin ALT-3
|LCDIF.D[8]DISP_DATA08
|-
|Pin ALT-4
|SPI8.PCS0SPI8_PCS0
|-
|Pin ALT-5
|UART8.TXUART8_TX
|-
|Pin ALT-6
|I2C8.SDAI2C8_SDA
|-
|Pin ALT-7
|SAI3.RX_SYNCSAI3_RX_SYNC
|-
| rowspan="8" |J1.193
|-
|Pin ALT-1
|TPM4.CH2TPM4_CH2
|-
|Pin ALT-2
|PDM.BIT_STREAM[3]PDM_BIT_STREAM03
|-
|Pin ALT-3
|LCDIF.D[9]DISP_DATA09
|-
|Pin ALT-4
|SPI8.SINSPI8_SIN
|-
|Pin ALT-5
|UART8.RXUART8_RX
|-
|Pin ALT-6
|I2C8.SCLI2C8_SCL
|-
|Pin ALT-7
|FLEXIO1.FLEXIO[13]FLEXIO1_FLEXIO13
|-
| rowspan="8" |J1.195
|-
|Pin ALT-1
|I2C4.SDAI2C4_SDA
|-
|Pin ALT-2
|ISI.FRAME_VALIDCAM_VSYNC
|-
|Pin ALT-3
|LCDIF.VSYNCDISP_VSYNC
|-
|Pin ALT-4
|SPI6.SOUTSPI6_SOUT
|-
|Pin ALT-5
|UART5.CTS_BUART5_CTS_B
|-
|Pin ALT-6
|I2C6.SDAI2C6_SDA
|-
|Pin ALT-7
|FLEXIO1.FLEXIO[2]FLEXIO1_FLEXIO02
|-
|J1.197
| rowspan="7" |
|Pin ALT-0
|PDM.BIT_STREAM[0]PDM_BIT_STREAM00
|-
|Pin ALT-1
|MQS1.RIGHTMQS1_RIGHT
|-
|Pin ALT-2
|SPI1.PCS1SPI1_PCS1
|-
|Pin ALT-3
|TPM1.EXTCLKTPM1_EXTCLK
|-
|Pin ALT-4
|LPTMR1.ALT2LPTMR1_ALT2
|-
|Pin ALT-5
|GPIO1.IO09GPIO1_IO09
|-
|Pin ALT-6
|CAN1.RXCAN1_RX
|-
| rowspan="5" |J1.201
|-
|Pin ALT-1
|MQS1.LEFTMQS1_LEFT
|-
|Pin ALT-4
|LPTMR1.ALT1LPTMR1_ALT1
|-
|Pin ALT-5
|GPIO1.IO08GPIO1_IO08
|-
|Pin ALT-6
|CAN1.TXCAN1_TX
|-
|J1.203
| rowspan="6" |
|Pin ALT-0
|PDM.BIT_STREAM[1]PDM_BIT_STREAM01
|-
|Pin ALT-1
|M33.NMINMI_GLUE_NMI
|-
|Pin ALT-2
|SPI2.PCS1SPI2_PCS1
|-
|Pin ALT-3
|TPM2.EXTCLKTPM2_EXTCLK
|-
|Pin ALT-4
|LPTMR1.ALT3LPTMR1_ALT3
|-
|Pin ALT-5
|GPIO1.IO10GPIO1_IO10
|-
| rowspan="2" |J1.28
| rowspan="2" |
|Pin ALT-0
|WDOG1.WDOG_ANYWDOG1_WDOG_ANY
|-
|Pin ALT-5
|GPIO1.IO15GPIO1_IO15
|-
|J1.30
|-
|Pin ALT-1
|SAI3.MCLKSAI3_MCLK
|-
|Pin ALT-2
|ISI.D[8]CAM_DATA08
|-
|Pin ALT-3
|LCDIF.D[13]DISP_DATA13
|-
|Pin ALT-4
|UART3.RTS_BUART3_RTS_B
|-
|Pin ALT-5
|SPI4.PCS1SPI4_PCS1
|-
|Pin ALT-6
|UART4.RTS_BUART4_RTS_B
|-
|Pin ALT-7
|FLEXIO1.FLEXIO[17]FLEXIO1_FLEXIO17
|-
| rowspan="8" |J1.36
|-
|Pin ALT-1
|SAI3.TX_DATA[0]SAI3_TX_DATA00
|-
|Pin ALT-2
|PDM.CLKPDM_CLK
|-
|Pin ALT-3
|LCDIF.D[17]DISP_DATA17
|-
|Pin ALT-4
|SPI5.SCKSPI5_SCK
|-
|Pin ALT-5
|SPI4.SCKSPI4_SCK
|-
|Pin ALT-6
|TMP4.CH1TPM4_CH1
|-
|Pin ALT-7
|SAI3.RX_BCLKSAI3_RX_BCLK
|-
| rowspan="3" |J1.38
|-
|Pin ALT-1
|I2C3.SCLI2C3_SCL
|-
|Pin ALT-7
|FLEXIO1.FLEXIO[29]FLEXIO1_FLEXIO29
|-
| rowspan="8" |J1.40
|-
|Pin ALT-1
|SPI3.PCS1SPI3_PCS1
|-
|Pin ALT-2
|ISI.D[1]CAM_DATA01
|-
|Pin ALT-3
|LCDIF.D[3]DISP_DATA03
|-
|Pin ALT-4
|SPI7.SCKSPI7_SCK
|-
|Pin ALT-5
|UART6.RTS_BUART6_RTS_B
|-
|Pin ALT-6
|I2C7.SCLI2C7_SCL
|-
|Pin ALT-7
|FLEXIO1.FLEXIO[7]FLEXIO1_FLEXIO07
|-
| rowspan="8" |J1.42
|-
|Pin ALT-1
|USDHC3.DATA1USDHC3_DATA1
|-
|Pin ALT-2
|CAN2.TXCAN2_TX
|-
|Pin ALT-3
|LCDIF.D[21]DISP_DATA21
|-
|Pin ALT-4
|TMP4.CH3TPM4_CH3
|-
|Pin ALT-5
|DAP.TCLK_SWCLKJTAG_MUX_TCK
|-
|Pin ALT-6
|SPI7.PCS1SPI7_PCS1
|-
|Pin ALT-7
|FLEXIO1.FLEXIO[25]FLEXIO1_FLEXIO25
|-
| rowspan="8" |J1.44
|-
|Pin ALT-1
|USDHC3.DATA3USDHC3_DATA3
|-
|Pin ALT-2
|CAN2.RXCAN2_RX
|-
|Pin ALT-3
|LCDIF.D[23]DISP_DATA23
|-
|Pin ALT-4
|TMP6.CH3TPM6_CH3
|-
|Pin ALT-5
|DAP.TMS_SWDIOJTAG_MUX_TMS
|-
|Pin ALT-6
|SPI5.PCS1SPI5_PCS1
|-
|Pin ALT-7
|FLEXIO1.FLEXIO[27]FLEXIO1_FLEXIO27
|-
| rowspan="7" |J1.46
|-
|Pin ALT-1
|USDHC3.DATA0USDHC3_DATA0
|-
|Pin ALT-3
|LCDIF.D[20]DISP_DATA20
|-
|Pin ALT-4
|TMP3.CH3TPM3_CH3
|-
|Pin ALT-5
|DAP.TDO_TRACESWOJTAG_MUX_TDO
|-
|Pin ALT-6
|SPI6.PSC1SPI6_PSC1
|-
|Pin ALT-7
|FLEXIO1.FLEXIO[24]FLEXIO1_FLEXIO24
|-
| rowspan="3" |J1.48
|-
|Pin ALT-1
|I2C3.SDAI2C3_SDA
|-
|Pin ALT-7
|FLEXIO1.FLEXIO[28]FLEXIO1_FLEXIO28
|-
| rowspan="3" |J1.50
| rowspan="3" |
|Pin ALT-0
|CCMSRCGPCMIX.CLK01CCMSRCGPCMIX_CLK01
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[26]FLEXIO1_FLEXIO26
|-
|Pin ALT-5
| rowspan="3" |
|Pin ALT-0
|CCMSRCGPCMIX.CLK02CCMSRCGPCMIX_CLK02
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[27]FLEXIO1_FLEXIO27
|-
|Pin ALT-5
| rowspan="3" |
|Pin ALT-0
|CCMSRCGPCMIX.CLK01CCMSRCGPCMIX_CLK01
|-
|Pin ALT-4
|FLEXIO2.FLEXIO[28]FLEXIO2_FLEXIO28
|-
|Pin ALT-5
| rowspan="6" |
|Pin ALT-0
|SAI1.RX_DATA[0]SAI1_RX_DATA00
|-
|Pin ALT-1
|SAI1.MCLKSAI1_MCLK
|-
|Pin ALT-2
|SPI1.SOUTSPI1_SOUT
|-
|Pin ALT-3
|UART2.DSR_BUART2_DSR_B
|-
|Pin ALT-4
|MQS1.RIGHTMQS1_RIGHT
|-
|Pin ALT-5
|GPIO1.IO14GPIO1_IO14
|-
| rowspan="3" |J1.64
| rowspan="3" |
|Pin ALT-0
|CCMSRCGPCMIX.CLK04CCMSRCGPCMIX_CLK04
|-
|Pin ALT-4
|FLEXIO2.FLEXIO[29]FLEXIO2_FLEXIO29
|-
|Pin ALT-5
|-
|Pin ALT-1
|SAI3.TX_BCLKSAI3_TX_BCLK
|-
|Pin ALT-2
|PDM.BIT_STREAM[2]PDM_BIT_STREAM02
|-
|Pin ALT-3
|LCDIF.D[12]DISP_DATA12
|-
|Pin ALT-4
|UART3.CTS_BUART3_CTS_B
|-
|Pin ALT-5
|SPI4.PCS2SPI4_PCS2
|-
|Pin ALT-6
|UART4.CTS_BUART4_CTS_B
|-
|Pin ALT-7
|FLEXIO1.FLEXIO[16]FLEXIO1_FLEXIO16
|-
| rowspan="8" |J1.68
|-
|Pin ALT-1
|SAI3.RX_SYNCSAI3_RX_SYNC
|-
|Pin ALT-2
|PDM.BIT_STREAM[3]PDM_BIT_STREAM03
|-
|Pin ALT-3
|LCDIF.D[15]DISP_DATA15
|-
|Pin ALT-4
|SPI5.SINSPI5_SIN
|-
|Pin ALT-5
|SPI4.SINSPI4_SIN
|-
|Pin ALT-6
|TMP4.CH2TPM4_CH2
|-
|Pin ALT-7
|SAI3.TX_DATA[0]SAI3_TX_DATA00
|-
| rowspan="8" |J1.70
|-
|Pin ALT-1
|USDHC3.DATA2USDHC3_DATA2
|-
|Pin ALT-2
|PDM.BIT_STREAM[1]PDM_BIT_STREAM01
|-
|Pin ALT-3
|LCDIF.D[22]DISP_DATA22
|-
|Pin ALT-4
|TMP3.CH3TPM3_CH3
|-
|Pin ALT-5
|DAP-TDIJTAG_MUX_TDI
|-
|Pin ALT-6
|SPI8.PCS1SPI8_PCS1
|-
|Pin ALT-7
|SAI3.TX_SYNCSAI3_TX_SYNC
|-
| rowspan="8" |J1.72
|-
|Pin ALT-1
|SAI3.RX_DATA[0]SAI3_RX_DATA00
|-
|Pin ALT-2
|PDM.BIT_STREAM[0]PDM_BIT_STREAM00
|-
|Pin ALT-3
|LCDIF.D[16]DISP_DATA16
|-
|Pin ALT-4
|SPI5.SOUTSPI5_SOUT
|-
|Pin ALT-5
|SPI4.SOUTSPI4_SOUT
|-
|Pin ALT-6
|TMP3.CH1TPM3_CH1
|-
|Pin ALT-7
|FLEXIO1.FLEXIO[20]FLEXIO1_FLEXIO20
|-
| rowspan="8" |J1.74
|-
|Pin ALT-1
|USDHC3.CLKUSDHC3_CLK
|-
|Pin ALT-2
|SPDIF1.INSPDIF_IN
|-
|Pin ALT-3
|LCDIF.D[18]DISP_DATA18
|-
|Pin ALT-4
|TMP5.CH1TPM5_CH1
|-
|Pin ALT-5
|TMP6.EXTCLKTPM6_EXTCLK
|-
|Pin ALT-6
|I2C5.SDAI2C5_SDA
|-
|Pin ALT-7
|FLEXIO1.FLEXIO[22]FLEXIO1_FLEXIO22
|-
| rowspan="7" |J1.76
|-
|Pin ALT-1
|USDHC3.CMDUSDHC3_CMD
|-
|Pin ALT-2
|SPDIF1.OUTSPDIF_OUT
|-
|Pin ALT-3
|LCDIF.D[19]DISP_DATA19
|-
|Pin ALT-4
|TMP6.CH1TPM6_CH1
|-
|Pin ALT-6
|I2C5.SCLI2C5_SCL
|-
|Pin ALT-7
|FLEXIO1.FLEXIO[23]FLEXIO1_FLEXIO23
|-
| rowspan="8" |J1.78
|-
|Pin ALT-1
|TMP4.CH0TPM4_CH0
|-
|Pin ALT-2
|PDM.BIT_STREAM[0]PDM_BIT_STREAM00
|-
|Pin ALT-3
|LCDIF.D[1]DISP_DATA01
|-
|Pin ALT-4
|SPI7.SINSPI7_SIN
|-
|Pin ALT-5
|UART6.RXUART6_RX
|-
|Pin ALT-6
|I2C6.SCLI2C6_SCL
|-
|Pin ALT-7
|FLEXIO1.FLEXIO[5]FLEXIO1_FLEXIO05
|-
| rowspan="8" |J1.80
|-
|Pin ALT-1
|TMP3.CH0TPM3_CH0
|-
|Pin ALT-2
|PDM.CLKPDM_CLK
|-
|Pin ALT-3
|LCDIF.D[0]DISP_DATA00
|-
|Pin ALT-4
|SPI7.PCS0SPI7_PCS0
|-
|Pin ALT-5
|UART6.TXUART6_TX
|-
|Pin ALT-6
|I2C6.SDAI2C6_SDA
|-
|Pin ALT-7
|FLEXIO1.FLEXIO[4]FLEXIO1_FLEXIO04
|-
|J1.82
| rowspan="6" |
|Pin ALT-0
|DAP.TDIJTAG_MUX_TDI
|-
|Pin ALT-1
|MQS2.LEFTMQS2_LEFT
|-
|Pin ALT-3
|CAN2.TXCAN2_TX
|-
|Pin ALT-4
|FLEXIO2.FLEXIO[30]FLEXIO2_FLEXIO30
|-
|Pin ALT-5
|GPIO3.IO28GPIO3_IO28
|-
|Pin ALT-6
|UART5.RXUART5_RX
|-
| rowspan="4" |J1.94
| rowspan="4" |
|Pin ALT-0
|DAP.TMS_SWDIOJTAG_MUX_TMS
|-
|Pin ALT-4
|FLEXIO2.FLEXIO[31]FLEXIO2_FLEXIO31
|-
|Pin ALT-5
|GPIO3.IO29GPIO3_IO29
|-
|Pin ALT-6
|UART5.RTS_BUART5_RTS_B
|-
| rowspan="4" |J1.96
| rowspan="4" |
|Pin ALT-0
|DAP.TCLK_SWCLKJTAG_MUX_TCK
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[30]FLEXIO1_FLEXIO30
|-
|Pin ALT-5
|GPIO3.IO30GPIO3_IO30
|-
|Pin ALT-6
|UART5.CTS_BUART5_CTS_B
|-
| rowspan="6" |J1.98
| rowspan="6" |
|Pin ALT-0
|DAP.TDO_TRACESWOJTAG_MUX_TDO
|-
|Pin ALT-1
|MQS2.RIGHTMQS2_RIGHT
|-
|Pin ALT-3
|CAN2.RXCAN2_RX
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[31]FLEXIO1_FLEXIO31
|-
|Pin ALT-5
|GPIO3.IO31GPIO3_IO31
|-
|Pin ALT-6
|UART5.TXUART5_TX
|-
|J1.100
| rowspan="6" |
|Pin ALT-0
|ENET_QOS.MDCENET_QOS_MDC
|-
|Pin ALT-1
|UART3.DCR_BUART3_DCR_B
|-
|Pin ALT-2
|I3C2.SCLI3C2_SCL
|-
|Pin ALT-3
|USB1.OTG_IDUSB1_OTG_ID
|-
|Pin ALT-4
|FLEXIO2.FLEXIO[0]FLEXIO2_FLEXIO00
|-
|Pin ALT-5
|GPIO4.IO00GPIO4_IO00
|-
| rowspan="6" |J1.126
| rowspan="6" |
|Pin ALT-0
|ENET_QOS.MDIOENET_QOS_MDIO
|-
|Pin ALT-1
|UART3.RIN_BUART3_RIN_B
|-
|Pin ALT-2
|I3C2.SDAI3C2_SDA
|-
|Pin ALT-3
|USB1.OTG_PWRUSB1_OTG_PWR
|-
|Pin ALT-4
|FLEXIO2.FLEXIO[1]FLEXIO2_FLEXIO01
|-
|Pin ALT-5
|GPIO4.IO01GPIO4_IO01
|-
| rowspan="3" |J1.128
| rowspan="3" |
|Pin ALT-0
|USDHC1.CLKUSDHC1_CLK
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[8]FLEXIO1_FLEXIO08
|-
|Pin ALT-5
| rowspan="3" |
|Pin ALT-0
|USDHC1.CMDUSDHC1_CMD
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[9]FLEXIO1_FLEXIO09
|-
|Pin ALT-5
| rowspan="4" |
|Pin ALT-0
|USDHC1.CLKUSDHC1_CLK
|-
|Pin ALT-1
|FLEXSPI.A_DQSFLEXSPI1_A_DQS
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[18]FLEXIO1_FLEXIO18
|-
|Pin ALT-5
| rowspan="3" |
|Pin ALT-0
|USDHC1.DATA0USDHC1_DATA0
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[10]FLEXIO1_FLEXIO10
|-
|Pin ALT-5
| rowspan="3" |
|Pin ALT-0
|USDHC1.DATA1USDHC1_DATA1
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[11]FLEXIO1_FLEXIO11
|-
|Pin ALT-5
| rowspan="3" |
|Pin ALT-0
|USDHC1.DATA2USDHC1_DATA2
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[12]FLEXIO1_FLEXIO12
|-
|Pin ALT-5
| rowspan="3" |
|Pin ALT-0
|USDHC1.DATA3USDHC1_DATA3|-|Pin ALT-1|FLEXSPI1_A_SS1_B
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[13]FLEXIO1_FLEXIO13
|-
|Pin ALT-5
| rowspan="4" |
|Pin ALT-0
|USDHC1.DATA4USDHC1_DATA4
|-
|Pin ALT-1
|FLEXSPI.A_DATA[4]FLEXSPI1_A_DATA04
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[14]FLEXIO1_FLEXIO14
|-
|Pin ALT-5
| rowspan="4" |
|Pin ALT-0
|USDHC1.DATA5USDHC1_DATA5
|-
|Pin ALT-1
|FLEXSPI.A_DATA[5]FLEXSPI1_A_DATA05
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[15]FLEXIO1_FLEXIO15
|-
|Pin ALT-5
| rowspan="4" |
|Pin ALT-0
|USDHC1.DATA6USDHC1_DATA6
|-
|Pin ALT-1
|FLEXSPI.A_DATA[6]FLEXSPI1_A_DATA06
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[16]FLEXIO1_FLEXIO16
|-
|Pin ALT-5
| rowspan="4" |
|Pin ALT-0
|USDHC1.DATA7USDHC1_DATA7
|-
|Pin ALT-1
|FLEXSPI.A_DATA[7]FLEXSPI1_A_DATA07
|-
|Pin ALT-4
|FLEXIO1.FLEXIO[17]FLEXIO1_FLEXIO17
|-
|Pin ALT-5
| rowspan="4" |
|Pin ALT-0
|ENET2.RGMII_TD3ENET1_RGMII_TD3
|-
|Pin ALT-2
|SAI2.RX_DATA[0]SAI2_RX_DATA00
|-
|Pin ALT-4
|FLEXIO2.FLEXIO[16]FLEXIO2_FLEXIO16
|-
|Pin ALT-5
|GPIO4.IO16GPIO4_IO16
|-
| rowspan="5" |J1.158
| rowspan="5" |
|Pin ALT-0
|ENET2.RGMII_TD2ENET1_RGMII_TD2
|-
|Pin ALT-1
|ENET2.TX_CLK ENET1_TX_CLK // CCMSRCGPMCMIX.ENET_REF_CLK_ROOT
|-
|Pin ALT-2
|SAI2.RX_DATA[1]SAI2_RX_DATA01
|-
|Pin ALT-4
|FLEXIO2.FLEXIO[17]FLEXIO2_FLEXIO17
|-
|Pin ALT-5
|GPIO4.IO17GPIO4_IO17
|-
| rowspan="5" |J1.160
| rowspan="5" |
|Pin ALT-0
|ENET2.RGMII_TD1ENET1_RGMII_TD1
|-
|Pin ALT-1
|UART4.RTS_BUART4_RTS_B
|-
|Pin ALT-2
|SAI2.RX_DATA[2]SAI2_RX_DATA02
|-
|Pin ALT-4
|FLEXIO2.FLEXIO[18]FLEXIO2_FLEXIO18
|-
|Pin ALT-5
|GPIO4.IO18GPIO4_IO18
|-
| rowspan="5" |J1.162
| rowspan="5" |
|Pin ALT-0
|ENET2.RGMII_TD0ENET1_RGMII_TD0
|-
|Pin ALT-1
|UART4.TXUART4_TX
|-
|Pin ALT-2
|SAI2.RX_DATA[3]SAI2_RX_DATA03
|-
|Pin ALT-4
|FLEXIO2.FLEXIO[19]FLEXIO2_FLEXIO19
|-
|Pin ALT-5
|GPIO4.IO19GPIO4_IO19
|-
|J1.164
| rowspan="5" |
|Pin ALT-0
|ENET2.RGMI_TXCENET1_RGMI_TXC
|-
|Pin ALT-1
|ENET2.TX_ERENET1_TX_ER
|-
|Pin ALT-2
|SAI2.TX_BCLKSAI2_TX_BCLK
|-
|Pin ALT-4
|FLEXIO2.FLEXIO[21]FLEXIO2_FLEXIO21
|-
|Pin ALT-5
|GPIO4.IO21GPIO4_IO21
|-
| rowspan="5" |J1.168
| rowspan="5" |
|Pin ALT-0
|ENET2.RGMI_TX_CTLENET1_RGMI_TX_CTL
|-
|Pin ALT-1
|UART4.DTR_BUART4_DTR_B
|-
|Pin ALT-2
|SAI2.TX_SYNCSAI2_TX_SYNC
|-
|Pin ALT-4
|FLEXIO2.FLEXIO[20]FLEXIO2_FLEXIO20
|-
|Pin ALT-5
|GPIO4.IO20GPIO4_IO20
|-
| rowspan="5" |J1.170
| rowspan="5" |
|Pin ALT-0
|ENET2.MDCENET1_MDC
|-
|Pin ALT-1
|UART4.DCR_BUART4_DCR_B
|-
|Pin ALT-2
|SAI2.RX_SYNCSAI2_RX_SYNC
|-
|Pin ALT-4
|FLEXIO2.FLEXIO[14]FLEXIO2_FLEXIO14
|-
|Pin ALT-5
|GPIO4.IO14GPIO4_IO14
|-
| rowspan="5" |J1.172
| rowspan="5" |
|Pin ALT-0
|ENET2.MDIOENET1_MDIO
|-
|Pin ALT-1
|UART4.RIN_BUART4_RIN_B
|-
|Pin ALT-2
|SAI2.RX_BCLKSAI2_RX_BCLK
|-
|Pin ALT-4
|FLEXIO2.FLEXIO[15]FLEXIO2_FLEXIO15
|-
|Pin ALT-5
|GPIO4.IO15GPIO4_IO15
|-
| rowspan="5" |J1.174
| rowspan="5" |
|Pin ALT-0
|ENET2.RGMII_RX_CTLENET1_RGMII_RX_CTL
|-
|Pin ALT-1
|UART4.DSR_BUART4_DSR_B
|-
|Pin ALT-2
|SAI2.TX_DATA[0]SAI2_TX_DATA00
|-
|Pin ALT-4
|FLEXIO2.FLEXIO[22]FLEXIO2_FLEXIO22
|-
|Pin ALT-5
|GPIO4.IO22GPIO4_IO22
|-
| rowspan="5" |J1.176
| rowspan="5" |
|Pin ALT-0
|ENET2.RGMII_RD0ENET1_RGMII_RD0
|-
|Pin ALT-1
|UART4.RXUART4_RX
|-
|Pin ALT-2
|SAI2.TX_DATA[2]SAI2_TX_DATA02
|-
|Pin ALT-4
|FLEXIO2.FLEXIO[24]FLEXIO2_FLEXIO24
|-
|Pin ALT-5
|GPIO4.IO24GPIO4_IO24
|-
| rowspan="5" |J1.178
| rowspan="5" |
|Pin ALT-0
|ENET2.RGMII_RD1ENET1_RGMII_RD1
|-
|Pin ALT-1
|SPDIF1.INSPDIF_IN
|-
|Pin ALT-2
|SAI2.TX_DATA[3]SAI2_TX_DATA03
|-
|Pin ALT-4
|FLEXIO2.FLEXIO[25]FLEXIO2_FLEXIO25
|-
|Pin ALT-5
|GPIO4.IO25GPIO4_IO25
|-
| rowspan="6" |J1.180
| rowspan="6" |
|Pin ALT-0
|ENET2.RGMII_RD1ENET1_RGMII_RD1
|-
|Pin ALT-1
|UART4.CTS_BUART4_CTS_B
|-
|Pin ALT-2
|SAI2.MCLKSAI2_MCLK
|-
|Pin ALT-3
|MQS2.RIGHTMQS2_RIGHT
|-
|Pin ALT-4
|FLEXIO2.FLEXIO[26]FLEXIO2_FLEXIO26
|-
|Pin ALT-5
|GPIO4.IO26GPIO4_IO26
|-
| rowspan="6" |J1.182
| rowspan="6" |
|Pin ALT-0
|ENET2.RGMII_RD3ENET1_RGMII_RD3
|-
|Pin ALT-1
|SPDIF1.OUTSPDIF_OUT
|-
|Pin ALT-2
|SPDIF1.NSPDIF_IN
|-
|Pin ALT-3
|MQS2.LEFTMQS2_LEFT
|-
|Pin ALT-4
|FLEXIO2.FLEXIO[27]FLEXIO2_FLEXIO27
|-
|Pin ALT-5
|GPIO4.IO27GPIO4_IO27
|-
| rowspan="5" |J1.184
| rowspan="5" |
|Pin ALT-0
|ENET2.RGMII_RXCENET1_RGMII_RXC
|-
|Pin ALT-1
|ENET2.RX_ERENET1_RX_ER
|-
|Pin ALT-2
|SAI2.TX_DATA[1]SAI2_TX_DATA01
|-
|Pin ALT-4
|FLEXIO2.FLEXIO[23]FLEXIO2_FLEXIO23
|-
|Pin ALT-5
|GPIO4.IO23GPIO4_IO23
|-
|J1.186
U0016
a000298_approval, dave_user
551
edits
Retrieved from "https://wiki.dave.eu/index.php/Special:MobileDiff/17942...20284"