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AURA SOM/AURA Hardware/Pinout Table

6,112 bytes removed, 25 March
→‎Pinout Table ODD pins declaration: ETH1 controller clarification
<section begin="History" />
{| style="border-collapse:collapse; "
!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History
|-
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|ID#!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes
|-
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|{{oldid|1789118728|178912023/05/15}}|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|15Preliminary version|-| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |{{oldid|18879|2023/0510/23}}| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Final SOM release|-| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |{{oldid|18983|2023/12/01}}|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Preliminary versionPinmux label fix|-! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |2023/12/20! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |Pin labels renaming<br>Add pinmux spreadsheet download
|-
|}
<section end="History" /><section begin="Body" />
==Connectors and Pinout Table==
|TE Connectivity 2013289-1
|}
The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to ORCA AURA pinout specifications. See the images below for reference:
[[File:AURA-topSOM_top-pin1-203.png|500px|thumb|AURA TOP view|none]][[File:AURA-bottomSOM_bottom-pin2-204.png|500px|thumb|AURA BOTTOM view|none]]
===Pinout table naming conventions ===
This chapter contains the pinout description of the AURA module, grouped in two tables (odd and even pins) that report the pin mapping of the ''TBD: connector type'' 204-pin SO-DIMM AURA connector.
Each row in the pinout tables contains the following information:
{|class="wikitable" style="width:50%;"
|-
|'''Pin'''
* PMIC.<x> : pin connected to the Power Manager IC (NXP PCA9451A)
* LAN.<x> : pin connected to the LAN PHY (Microchip LAN8830T-V)
* NOR.<x>: pin connected to the flash NOR
* SV.<x>: pin connected to voltage supervisor
* MTR: pin connected to voltage monitors
|-
|'''Ball/pin #'''
|3.3VIN
|3.3
|See [[AURA_SOM/AXEL_Lite_HardwareAURA_Hardware/Electrical_Thermal_and_Mechanical_Features/Operational_characteristics#Recommended_ratings|Operational_characteristics]] of the SoM wiki page|-|VCC_ENET_1V8|1.8|Voltage generated by the internal PSU. See [[AURA_SOM/AXEL_Lite_Hardware/Power_and_Reset/Power_Supply_Unit_(PSU)_and_recommended_power-up_sequence | Power Supply Unit (PSU)]] wiki page
|-
|IO_3V3NVCC_3V3
|3.3
|Voltage generated by the internal PSU. See [[AURA_SOM/AXEL_Lite_HardwareAURA_Hardware/Power_and_Reset/Power_Supply_Unit_(PSU)_and_recommended_power-up_sequence | Power Supply Unit (PSU)]] wiki page
|-
|GEN_2V5VDD_ANA_1V8|21.58|Voltage generated by the internal PSU. See [[AURA_SOM/AXEL_Lite_Hardware/Power_and_Reset/Power_Supply_Unit_(PSU)_and_recommended_power-up_sequence | Power Supply Unit (PSU)]] wiki page
|-
|}
 
===Pinout table XLS file ===
For your convenience, please find a spreadsheet with the AURA/MIMX935x pinout and pinmux table [https://www.dave.eu/links/p/hdTvHz4xQ811bdtb here].
==Pinout Table ODD pins declaration ==
{| class="wikitable"
! latexfontsize="scriptsize"| Pin ! latexfontsize="scriptsize"| Pin Name! latexfontsize="scriptsize"| Internal Connections ! latexfontsize="scriptsize"| Ball/pin # ! latexfontsize="scriptsize"| Voltage domain! latexfontsize="scriptsize"| Type ! latexfontsize="scriptsize"| Notes! colspan="2" latexfontsize="scriptsize"| Alternative Functions
|-
|rowspan="5"|J1.1|rowspan="5"|SD2_CMDDGND|rowspan="5"|CPU.SD2_CMDDGND|rowspan="5"|F19-|rowspan="5"|AXEL_IO_3V3-|rowspan="5"|IOG|rowspan="5"|Notes|Pin ALT-0|SD2_CMD
|-
|Pin ALTJ1.3|3.3VIN|INPUT VOLTAGE| -1|ECSPI5_MOSI3.3VIN|S|||
|-
|Pin ALTJ1.5|3.3VIN|INPUT VOLTAGE| -2|KEY_ROW53.3VIN|S|||
|-
|Pin ALTJ1.7|3.3VIN|INPUT VOLTAGE| -|3.3VIN|AUD4_RXCS|-|Pin ALT-5|GPIO1_IO11
|-
|rowspan="5"|J1.39|rowspan="5"|TBD3.3VIN|rowspan="5"|TBDINPUT VOLTAGE|rowspan="5"|TBD-|rowspan="5"|TBD3.3VIN|rowspan="5"|TBDS|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALTJ1.11|DGND|DGND| -1|TBD-|G|||
|-
|Pin ALT-2J1.13|ETH1_LED1|LAN.LED1/GPIO0|18|NVCC_3V3|O|||TBD
|-
|Pin ALT-3J1.15|ETH1_LED2|LAN.LED2/GPIO1|16|NVCC_3V3|O|||TBD
|-
|Pin ALTJ1.17|DGND|DGND| -5|TBD-|G|||
|-
|rowspan="5"|J1.519|rowspan="5"|TBDETH1_TXRX0_P|rowspan="5"|TBDLAN.TXRXP_A|rowspan="5"|TBD2|rowspan="5"|TBDNVCC_3V3|rowspan="5"|TBDD|rowspan="5"|TBDConnected to ENET_QOS controller|Pin ALT-0|TBD
|-
|Pin ALT-1J1.21|ETH1_TXRX0_M|LAN.TXRXM_A|3|NVCC_3V3|D|Connected to ENET_QOS controller||TBD
|-
|Pin ALT-2J1.23|ETH1_TXRX1_P|LAN.TXRXP_B|5|NVCC_3V3|D|Connected to ENET_QOS controller||TBD
|-
|Pin ALT-3J1.25|ETH1_TXRX1_M|LAN.TXRXM_B|6|NVCC_3V3|D|Connected to ENET_QOS controller||TBD
|-
|Pin ALT-5J1.27|ETH1_TXRX2_P|LAN.TXRXP_C|7|NVCC_3V3|D|Connected to ENET_QOS controller||TBD
|-
|rowspan="5"|J1.729|rowspan="5"|TBDETH1_TXRX2_M|rowspan="5"|TBDLAN.TXRXM_C|rowspan="5"|TBD8|rowspan="5"|TBDNVCC_3V3|rowspan="5"|TBDD|rowspan="5"|TBDConnected to ENET_QOS controller|Pin ALT-0|TBD
|-
|Pin ALT-1J1.31|ETH1_TXRX3_P|LAN.TXRXP_D|10|NVCC_3V3|D|Connected to ENET_QOS controller||TBD
|-
|Pin ALT-2J1.33|ETH1_TXRX3_M|LAN.TXRXM_D|11|NVCC_3V3|D|Connected to ENET_QOS controller||TBD
|-
|Pin ALTJ1.35|DGND|DGND| -3|TBD-|G|||
|-
|Pin ALT-5J1.37|ETH1_LED3|LAN.LED3/GPIO2|15|NVCC_3V3|O|||TBD
|-
|J1.39|ETH1_LED4|LAN.LED4/GPIO3|14|NVCC_3V3|O||||-|J1.41|ETH_OSC_EN||46|NVCC_3V3|I|mounting option|||-|rowspan="58"|J1.943|rowspan="58"|TBDGPIO_IO06|rowspan="58"|TBDCPU.GPIO_IO06|rowspan="58"|TBDL20|rowspan="58"|TBDNVCC_3V3|rowspan="58"|TBDIO|rowspan="58"|TBD
|Pin ALT-0
|TBDGPIO2_IO06
|-
|Pin ALT-1
|TBDTPM5_CH0
|-
|Pin ALT-2
|TBDPDM_BIT_STREAM01
|-
|Pin ALT-3
|TBDDISP_DATA02|-|Pin ALT-4|SPI7_SOUT
|-
|Pin ALT-5
|TBDUART6_CTS_B|-|Pin ALT-6|I2C7_SDA|-|Pin ALT-7|FLEXIO1_FLEXIO06
|-
|rowspan="58"|J1.1145|rowspan="58"|TBDGPIO_IO18|rowspan="58"|TBDCPU.GPIO_IO18|rowspan="58"|TBDR18|rowspan="58"|TBDNVCC_3V3|rowspan="58"|TBDIO|rowspan="58"|TBD
|Pin ALT-0
|TBDGPIO2_IO18
|-
|Pin ALT-1
|TBDSAI3_RX_BCLK
|-
|Pin ALT-2
|TBDCAM_DATA09
|-
|Pin ALT-3
|TBDDISP_DATA14|-|Pin ALT-4|SPI5_PCS0
|-
|Pin ALT-5
|TBDSPI4_PCS0
|-
|Pin ALT-6|TPM5_CH2|-|Pin ALT-7|FLEXIO1_FLEXIO18|-|rowspan="58"|J1.1347|rowspan="58"|TBDGPIO_IO09|rowspan="58"|TBDCPU.GPIO_IO09|rowspan="58"|TBDM21|rowspan="58"|TBDNVCC_3V3|rowspan="58"|TBDIO|rowspan="58"|TBD
|Pin ALT-0
|TBDGPIO2_IO09
|-
|Pin ALT-1
|TBDSPI3_SIN
|-
|Pin ALT-2
|TBDCAM_DATA03
|-
|Pin ALT-3
|TBDDISP_DATA05|-|Pin ALT-4|TPM3_EXTCLK
|-
|Pin ALT-5
|TBDUART7_RX
|-
|Pin ALT-6|I2C7_SCL|-|Pin ALT-7|FLEXIO1_FLEXIO09|-|rowspan="58"|J1.1549|rowspan="58"|TBDGPIO_IO08|rowspan="58"|TBDCPU.GPIO_IO08|rowspan="58"|TBDM20|rowspan="58"|TBDNVCC_3V3|rowspan="58"|TBDIO|rowspan="58"|TBD
|Pin ALT-0
|TBDGPIO2_IO08
|-
|Pin ALT-1
|TBDSPI3_SPCS0
|-
|Pin ALT-2
|TBDCAM_DATA02
|-
|Pin ALT-3
|TBDDISP_DATA04|-|Pin ALT-4|TPM6_CH0
|-
|Pin ALT-5
|TBDUART7_TX|-|Pin ALT-6|I2C7_SDA|-|Pin ALT-7|FLEXIO1_FLEXIO08|-|J1.51||||||||
|-
|rowspan="56"|J1.1753|rowspan="56"|TBDSAI1_TXFS|rowspan="56"|TBDCPU.SAI1_TXFS//BOOT2|rowspan="56"|TBDG21|rowspan="56"|TBDNVCC_AON|rowspan="56"|TBDIO|rowspan="56"|TBD
|Pin ALT-0
|TBDSAI1_TX_SYNC
|-
|Pin ALT-1
|TBDSAI1_TX_DATA01
|-
|Pin ALT-2
|TBDSPI1_PCS0
|-
|Pin ALT-3
|TBDUART2_DTR_B|-|Pin ALT-4|MQS1_LEFT
|-
|Pin ALT-5
|TBDGPIO1_IO11//BOOT_MODE[2]
|-
|rowspan="58"|J1.1955|rowspan="58"|TBDGPIO_IO10|rowspan="58"|TBDCPU.GPIO_IO10|rowspan="58"|TBDN17|rowspan="58"|TBDNVCC_3V3|rowspan="58"|TBDIO|rowspan="58"|TBD
|Pin ALT-0
|TBDGPIO2_IO10
|-
|Pin ALT-1
|TBDSPI3_SOUT
|-
|Pin ALT-2
|TBDCAM_DATA04
|-
|Pin ALT-3
|TBDDISP_DATA06|-|Pin ALT-4|TPM4_EXTCLK
|-
|Pin ALT-5
|TBDUART7_CTS_B|-|Pin ALT-6|I2C8_SDA|-|Pin ALT-7|FLEXIO1_FLEXIO10|-|J1.57|DGND|DGND| -| -|G|||
|-
|rowspan="58"|J1.2159|rowspan="58"|TBDGPIO_IO11|rowspan="58"|TBDCPU.GPIO_IO11|rowspan="58"|TBDN18|rowspan="58"|TBDNVCC_3V3|rowspan="58"|TBDIO|rowspan="58"|TBD
|Pin ALT-0
|TBDGPIO2_IO11
|-
|Pin ALT-1
|TBDSPI3_SCLK
|-
|Pin ALT-2
|TBDCAM_DATA05
|-
|Pin ALT-3
|TBDDISP_DATA07|-|Pin ALT-4|TPM5_EXTCLK
|-
|Pin ALT-5
|TBDUART7_RTS_B|-|Pin ALT-6|I2C8_SCL|-|Pin ALT-7|FLEXIO1_FLEXIO11
|-
|rowspan="54"|J1.2361|rowspan="54"|TBDSD3_DATA0|rowspan="54"|TBDCPU.GPIO_IO11|rowspan="54"|TBDT16|rowspan="54"|TBDNVCC_3V3|rowspan="54"|TBDIO|rowspan="54"|TBDOptionally connected to internal Flex SPI (NOR or NAND option)
|Pin ALT-0
|TBDUSDHC3_DATA0
|-
|Pin ALT-1
|TBDFLEXSPI1_A_DATA00
|-
|Pin ALT-24|TBD|-|Pin ALT-3|TBDFLEXIO1_FLEXIO22
|-
|Pin ALT-5
|TBDGPIO3_IO22
|-
|rowspan="54"|J1.2563|rowspan="54"|TBDSD3_DATA1|rowspan="54"|TBDCPU.GPIO_IO11|rowspan="54"|TBDV14|rowspan="54"|TBDNVCC_3V3|rowspan="54"|TBDIO|rowspan="54"|TBDOptionally connected to internal Flex SPI (NOR or NAND option)
|Pin ALT-0
|TBDUSDHC3_DATA1
|-
|Pin ALT-1
|TBDFLEXSPI1_A_DATA01
|-
|Pin ALT-24|TBD|-|Pin ALT-3|TBDFLEXIO1_FLEXIO23
|-
|Pin ALT-5
|TBDGPIO3_IO23
|-
|rowspan="54"|J1.2765|rowspan="54"|TBDSD3_DATA2|rowspan="54"|TBDCPU.GPIO_IO12|rowspan="54"|TBDU14|rowspan="54"|TBDNVCC_3V3|rowspan="54"|TBDIO|rowspan="54"|TBDOptionally connected to internal Flex SPI (NOR or NAND option)
|Pin ALT-0
|TBDUSDHC3_DATA2
|-
|Pin ALT-1
|TBDFLEXSPI1_A_DATA02
|-
|Pin ALT-24|TBD|-|Pin ALT-3|TBDFLEXIO1_FLEXIO24
|-
|Pin ALT-5
|TBDGPIO3_IO24
|-
|rowspan="54"|J1.2967|rowspan="54"|TBDSD3_DATA3|rowspan="54"|TBDCPU.GPIO_IO13|rowspan="54"|TBDT14|rowspan="54"|TBDNVCC_3V3|rowspan="54"|TBDIO|rowspan="54"|TBDOptionally connected to internal Flex SPI (NOR or NAND option)
|Pin ALT-0
|TBDUSDHC3_DATA3
|-
|Pin ALT-1
|TBD|-|Pin ALT-2|TBDFLEXSPI1_A_DATA03
|-
|Pin ALT-34|TBDFLEXIO1_FLEXIO25
|-
|Pin ALT-5
|TBDGPIO3_IO25
|-
|rowspan="54"|J1.3169|rowspan="54"|TBDSD3_CMD|rowspan="54"|TBDCPU.GPIO_IO21|rowspan="54"|TBDU16|rowspan="54"|TBDNVCC_3V3|rowspan="54"|TBDIO|rowspan="54"|TBDOptionally connected to internal Flex SPI (NOR or NAND option)
|Pin ALT-0
|TBDUSDHC3_CMD
|-
|Pin ALT-1
|TBD|-|Pin ALT-2|TBDFLEXSPI1_A_SS0_B
|-
|Pin ALT-34|TBDFLEXIO1_FLEXIO21
|-
|Pin ALT-5
|TBDGPIO3_IO21
|-
|rowspan="54"|J1.3371|rowspan="54"|TBDSD3_CLK|rowspan="54"|TBDCPU.GPIO_IO20|rowspan="54"|TBDV16|rowspan="54"|TBDNVCC_3V3|rowspan="54"|TBDIO|rowspan="54"|TBDOptionally connected to internal Flex SPI (NOR or NAND option)
|Pin ALT-0
|TBDUSDHC3_CLK
|-
|Pin ALT-1
|TBDFLEXSPI1_A_SCLK
|-
|Pin ALT-24|TBD|-|Pin ALT-3|TBDFLEXIO1_FLEXIO20
|-
|Pin ALT-5
|TBDGPIO3_IO20
|-
|J1.73|DGND|DGND| -| -|G||||-|rowspan="5"|J1.3575|rowspan="5"|TBDSD2_DATA0|rowspan="5"|TBDCPU.SD2_DATA0|rowspan="5"|TBDY18|rowspan="5"|TBDNVCC_3V3|rowspan="5"|TBDIO|rowspan="5"|TBD
|Pin ALT-0
|TBDUSDHC2_DATA0
|-
|Pin ALT-1
|TBDENET1_1588_EVENT0_OUT
|-
|Pin ALT-2
|TBDCAN2_TX
|-
|Pin ALT-34|TBDFLEXIO1_FLEXIO03
|-
|Pin ALT-5
|TBDGPIO3_IO03
|-
|rowspan="5"|J1.3777|rowspan="5"|TBDSD2_DATA1|rowspan="5"|TBDCPU.SD2_DATA1|rowspan="5"|TBDAA18|rowspan="5"|TBDNVCC_3V3|rowspan="5"|TBDIO|rowspan="5"|TBD
|Pin ALT-0
|TBDUSDHC2_DATA1
|-
|Pin ALT-1
|TBDENET1_1588_EVENT1_IN
|-
|Pin ALT-2
|TBDCAN2_RX
|-
|Pin ALT-34|TBDFLEXIO1_FLEXIO04
|-
|Pin ALT-5
|TBDGPIO3_IO04
|-
|rowspan="5"|J1.3979|rowspan="5"|TBDSD2_DATA2|rowspan="5"|TBDCPU.SD2_DATA2|rowspan="5"|TBDY20|rowspan="5"|TBDNVCC_3V3|rowspan="5"|TBDIO|rowspan="5"|TBD
|Pin ALT-0
|TBDUSDHC2_DATA2
|-
|Pin ALT-1
|TBDENET1_1588_EVENT1_OUT
|-
|Pin ALT-2
|TBDMQS1_RIGHT
|-
|Pin ALT-34|TBDFLEXIO1_FLEXIO05
|-
|Pin ALT-5
|TBDGPIO3_IO05
|-
|rowspan="5"|J1.4181|rowspan="5"|TBDSD2_DATA3|rowspan="5"|TBDCPU.SD2_DATA3|rowspan="5"|TBDAA20|rowspan="5"|TBDNVCC_3V3|rowspan="5"|TBDIO|rowspan="5"|TBD
|Pin ALT-0
|TBDUSDHC2_DATA3
|-
|Pin ALT-1
|TBDLPTMR2_ALT1
|-
|Pin ALT-2
|TBDMQS1_LEFT
|-
|Pin ALT-34|TBDFLEXIO1_FLEXIO06
|-
|Pin ALT-5
|TBDGPIO3_IO06
|-
|rowspan="56"|J1.4383|rowspan="56"|TBDSD2_CMD|rowspan="56"|TBDCPU.SD2_CMD|rowspan="56"|TBDY19|rowspan="56"|TBDNVCC_3V3|rowspan="56"|TBDIO|rowspan="56"|TBD
|Pin ALT-0
|TBDUSDHC2_CMD
|-
|Pin ALT-1
|TBDENET1_1588_EVENT0_IN
|-
|Pin ALT-2
|TBDI3C2_PUR
|-
|Pin ALT-3
|TBDI3C2_PUR_B|-|Pin ALT-4|FLEXIO1_FLEXIO02
|-
|Pin ALT-5
|TBDGPIO3_IO02
|-
|rowspan="5"|J1.4585|rowspan="5"|TBDSD2_CLK|rowspan="5"|TBDCPU.SD2_CLK|rowspan="5"|TBDAA19|rowspan="5"|TBDNVCC_3V3|rowspan="5"|TBDIO|rowspan="5"|TBD
|Pin ALT-0
|TBDUSDHC2_CLK
|-
|Pin ALT-1
|TBDENET_QOS_1588_EVENT0_OUT
|-
|Pin ALT-2
|TBDI3C2_SDA
|-
|Pin ALT-34|TBDFLEXIO1_FLEXIO01
|-
|Pin ALT-5
|TBDGPIO3_IO01
|-
|J1.87|DGND|DGND| -| -|G||||-|rowspan="58"|J1.4789|rowspan="58"|TBDGPIO_IO14|rowspan="58"|TBDCPU.GPIO_IO14|rowspan="58"|TBDP20|rowspan="58"|TBDNVCC_3V3|rowspan="58"|TBDIO|rowspan="58"|TBD
|Pin ALT-0
|TBDGPIO2_IO14
|-
|Pin ALT-1
|TBDUART3_TX
|-
|Pin ALT-2
|TBDCAM_DATA06
|-
|Pin ALT-3
|TBDDISP_DATA10|-|Pin ALT-4|SPI8_SOUT
|-
|Pin ALT-5
|TBDUART8_CTS_B
|-
|Pin ALT-6|UART4_TX|-|Pin ALT-7|FLEXIO1_FLEXIO14|-|rowspan="58"|J1.4991|rowspan="58"|TBDGPIO_IO15|rowspan="58"|TBDCPU.GPIO_IO15|rowspan="58"|TBDP21|rowspan="58"|TBDNVCC_3V3|rowspan="58"|TBDIO|rowspan="58"|TBD
|Pin ALT-0
|TBDGPIO2_IO15
|-
|Pin ALT-1
|TBDUART3_RX
|-
|Pin ALT-2
|TBDCAM_DATA07
|-
|Pin ALT-3
|TBDDISP_DATA11|-|Pin ALT-4|SPI8_SCK
|-
|Pin ALT-5
|TBDUART8_RTS_B
|-
|Pin ALT-6|UART4_RX|-|Pin ALT-7|FLEXIO1_FLEXIO15|-|rowspan="5"|J1.5193|rowspan="5"|TBDUART2_TXD|rowspan="5"|TBDCPU.UART2_TXD//BOOT1|rowspan="5"|TBDF21|rowspan="5"|TBDNVCC_3V3|rowspan="5"|TBDIO|rowspan="5"|TBDUsed as default console for Cortex-M33
|Pin ALT-0
|TBDUART2_TX
|-
|Pin ALT-1
|TBDUART1_RTS_B
|-
|Pin ALT-2
|TBDSPI2_SCK
|-
|Pin ALT-3
|TBDTPM1_CH3
|-
|Pin ALT-5
|TBDGPIO1_IO07//BOOT_MODE[1]
|-
|rowspan="56"|J1.5395|rowspan="56"|TBDUART2_RXD|rowspan="56"|TBDCPU.UART2_RXD|rowspan="56"|TBDF20|rowspan="56"|TBDNVCC_3V3|rowspan="56"|TBDIO|rowspan="56"|TBDUsed as default console for Cortex-M33
|Pin ALT-0
|TBDUART2_RX
|-
|Pin ALT-1
|TBDUART1_CTS_B
|-
|Pin ALT-2
|TBDSPI2_SOUT
|-
|Pin ALT-3
|TBDTPM1_CH2|-|Pin ALT-4|SAI1_MCLK
|-
|Pin ALT-5
|TBDGPIO1_IO06
|-
|rowspan="5"|J1.5597|rowspan="5"|TBDSD2_VSELECT|rowspan="5"|TBDCPU.SD2_VSELECT|rowspan="5"|TBDV18|rowspan="5"|TBDNVCC_3V3|rowspan="5"|TBDIO|rowspan="5"|TBD
|Pin ALT-0
|TBDUSDHC2_VSELECT
|-
|Pin ALT-1
|TBDUSHDC2_WP
|-
|Pin ALT-2
|TBDLPTMR2_ALT3
|-
|Pin ALT-34|TBDFLEXIO1_FLEXIO19
|-
|Pin ALT-5
|TBDGPIO3_IO19
|-
|rowspan="54"|J1.5799|rowspan="54"|TBDSD2_RESET_B|rowspan="54"|TBDCPU.SD2_RESET_B|rowspan="54"|TBDAA17|rowspan="54"|TBDNVCC_3V3|rowspan="54"|TBDIO|rowspan="54"|TBD
|Pin ALT-0
|TBDUSDHC2_RESET_B
|-
|Pin ALT-1
|TBD|-|Pin ALT-2|TBDLPTMR2_ALT2
|-
|Pin ALT-34|TBDFLEXIO1_FLEXIO07
|-
|Pin ALT-5
|TBDGPIO3_IO07
|-
|rowspan="5"|J1.59101|rowspan="5"|TBDI2C1_SCL|rowspan="5"|TBDCPU.I2C1_SCL|rowspan="5"|TBDC20|rowspan="5"|TBDNVCC_3V3|rowspan="5"|TBDIO|rowspan="5"|TBD
|Pin ALT-0
|TBDI2C1_SCL
|-
|Pin ALT-1
|TBDI3C1_SCL
|-
|Pin ALT-2
|TBDUART1_DCB_B
|-
|Pin ALT-3
|TBDTPM2_CH0
|-
|Pin ALT-5
|TBDGPIO1_IO00
|-
|rowspan="5"|J1.61103|rowspan="5"|TBDI2C1_SDA|rowspan="5"|TBDCPU.I2C1_SDA|rowspan="5"|TBDC21|rowspan="5"|TBDNVCC_3V3|rowspan="5"|TBDIO|rowspan="5"|TBD
|Pin ALT-0
|TBDI2C1_SDA
|-
|Pin ALT-1
|TBDI3C1_SDA
|-
|Pin ALT-2
|TBDUART1_RIN_B
|-
|Pin ALT-3
|TBDTPM2_CH1
|-
|Pin ALT-5
|TBDGPIO1_IO01
|-
|rowspan="56"|J1.63105|rowspan="56"|TBDSAI1_TXD0|rowspan="56"|TBDCPU.SAI1_TXD0//BOOT3|rowspan="56"|TBDH21|rowspan="56"|TBDNVCC_3V3|rowspan="56"|TBDIO|rowspan="56"|TBD
|Pin ALT-0
|TBDSAI1_TX_DATA00
|-
|Pin ALT-1
|TBDUART2_RTS_B
|-
|Pin ALT-2
|TBDSPI1_SCK
|-
|Pin ALT-3
|TBDUART1_DTR_B|-|Pin ALT-4|CAN1_TX
|-
|Pin ALT-5
|TBDGPIO1_IO13//BOOT_MODE[3]
|-
|rowspan="56"|J1.65107|rowspan="56"|TBDSAI1_TXC|rowspan="56"|TBDCPU.SAI1_TXC|rowspan="56"|TBDG20|rowspan="56"|TBDNVCC_3V3|rowspan="56"|TBDIO|rowspan="56"|TBD
|Pin ALT-0
|TBDSAI1_TX_BCLK
|-
|Pin ALT-1
|TBDUART2_CTS_B
|-
|Pin ALT-2
|TBDSPI1_SIN
|-
|Pin ALT-3
|TBDUART1_DSR_B|-|Pin ALT-4|CAN1_RX
|-
|Pin ALT-5
|TBDGPIO1_IO12
|-
|rowspan="5"|J1.67109|rowspan="5"|TBDDGND|rowspan="5"|TBDDGND|rowspan="5"|TBD-|rowspan="5"|TBD-|rowspan="5"|TBDG|rowspan="5"|TBD|Pin ALT-0|TBD
|-
| rowspan="1" |J1.111| rowspan="1" |ADC_IN0| rowspan="1" |CPU.ADC_IN0| rowspan="1" |B19| rowspan="1" |NVCC_3V3| rowspan="1" |IO| rowspan="1" ||Pin ALT-10|TBDADC_IN0
|-
| rowspan="1" |J1.113| rowspan="1" |ADC_IN1| rowspan="1" |CPU.ADC_IN1| rowspan="1" |A20| rowspan="1" |NVCC_3V3| rowspan="1" |IO| rowspan="1" ||Pin ALT-20|TBDADC_IN1
|-
| rowspan="1" |J1.115| rowspan="1" |ADC_IN2| rowspan="1" |CPU.ADC_IN2| rowspan="1" |B20| rowspan="1" |NVCC_3V3| rowspan="1" |IO| rowspan="1" ||Pin ALT-30|TBDADC_IN2
|-
|Pin ALT-5|TBD|-|rowspan="51"|J1.69117|rowspan="51"|TBDADC_IN3|rowspan="51"|TBDCPU.ADC_IN3|rowspan="51"|TBDB21|rowspan="51"|TBDNVCC_3V3|rowspan="51"|TBDIO|rowspan="51"|TBD
|Pin ALT-0
|TBDADC_IN3
|-
|Pin ALTJ1.119|PMIC_SCLH|PMIC.SCLH|25| -1|TBD|||
|-
|Pin ALTJ1.121|PMIC_SDAH|PMIC.SDAH|24| -2|TBD|||
|-
|Pin ALTJ1.123|PMIC_SCLL|PMIC.SCLL|27| -3|TBD|||
|-
|Pin ALT-5|TBD|-|rowspan="5"|J1.71125|rowspan="5"|TBDPMIC_SDAL|rowspan="5"|TBDPMIC.SDAL|rowspan="5"|TBD26|rowspan="5"|TBD-|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
| rowspan="5" |J1.127| rowspan="5" |I2C2_SDA| rowspan="5" |CPU.I2C2_SDA<br>PMIC.SDA| rowspan="5" |D21<br>42| rowspan="5" |NVCC_3V3| rowspan="5" |IO| rowspan="5" ||Pin ALT-10|TBDI2C2_SDA
|-
|Pin ALT-23|TBDUART2_RIN_B
|-
|Pin ALT-34|TBDTPM2_CH3
|-
|Pin ALT-5
|TBD|-|rowspan="5"|J1.73|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBDSAI1_RX_BCLK
|-
|Pin ALT-5
|TBDGPIO1_IO03
|-
|rowspan="57"|J1.75129|rowspan="57"|TBDI2C2_SCL|rowspan="57"|TBDCPU.I2C2_SCL<br>PMIC.SCL|rowspan="57"|TBDD20<br>41|rowspan="57"|TBDNVCC_3V3|rowspan="57"|TBDIO|rowspan="57"|TBD
|Pin ALT-0
|TBDI2C2_SCL
|-
|Pin ALT-1
|TBDI3C1_PUR
|-
|Pin ALT-23|TBDUART2_DCB_B
|-
|Pin ALT-34|TBDTPM2_CH2
|-
|Pin ALT-5
|TBDSAI1_RX_SYNC
|-
|rowspan="5"|J1.77|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-05|TBDGPIO1_IO02
|-
|Pin ALT-16|TBDI3C1_PUR_B
|-
|Pin ALTJ1.131|DGND|DGND| -2|TBD-|G|||
|-
|Pin ALT-3J1.133|LVDS_CLK_N|CPU.LVDS_CLK_N|A3|VDD_ANA_1V8|D|||TBD
|-
|Pin ALT-5J1.135|LVDS_CLK_P|CPU.LVDS_CLK_P|B3|VDD_ANA_1V8|D|||TBD
|-
|rowspan="5"|J1.79137|rowspan="5"|TBDLVDS_TX0_N|rowspan="5"|TBDCPU.LVDS_TX0_N|rowspan="5"|TBDA5|rowspan="5"|TBDVDD_ANA_1V8|rowspan="5"|TBDD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J1.139|LVDS_TX0_P|CPU.LVDS_TX0_P|B5|VDD_ANA_1V8|D|||TBD
|-
|Pin ALT-2J1.141|LVDS_TX1_N|CPU.LVDS_TX1_N|A4|VDD_ANA_1V8|D|||TBD
|-
|Pin ALT-3J1.143|LVDS_TX1_P|CPU.LVDS_TX1_P|B4|VDD_ANA_1V8|D|||TBD
|-
|Pin ALT-5J1.145|LVDS_TX2_N|CPU.LVDS_TX2_N|A2|VDD_ANA_1V8|D|||TBD
|-
|rowspan="5"|J1.81147|rowspan="5"|TBDLVDS_TX2_P|rowspan="5"|TBDCPU.LVDS_TX2_P|rowspan="5"|TBDB2|rowspan="5"|TBDVDD_ANA_1V8|rowspan="5"|TBDD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J1.149|LVDS_TX3_N|CPU.LVDS_TX3_N|B1|VDD_ANA_1V8|D|||TBD
|-
|Pin ALT-2J1.151|LVDS_TX3_P|CPU.LVDS_TX3_P|C1|VDD_ANA_1V8|D|||TBD
|-
|Pin ALTJ1.153|DGND|DGND| -3|TBD-|G|||
|-
|Pin ALT-5J1.155|DSI_CLK_N|CPU.DSI_CLK_N|D6|VDD_ANA_1V8|D|||TBD
|-
|rowspan="5"|J1.83157|rowspan="5"|TBDDSI_CLK_P|rowspan="5"|TBDCPU.DSI_CLK_P|rowspan="5"|TBDE6|rowspan="5"|TBDVDD_ANA_1V8|rowspan="5"|TBDD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J1.159|DSI_TX0_N|CPU.DSI_TX0_N|A6|VDD_ANA_1V8|D|||TBD
|-
|Pin ALT-2J1.161|DSI_TX0_P|CPU.DSI_TX0_P|B6|VDD_ANA_1V8|D|||TBD
|-
|Pin ALT-3J1.163|DSI_TX1_N|CPU.DSI_TX1_N|A7|VDD_ANA_1V8|D|||TBD
|-
|Pin ALT-5J1.165|DSI_TX1_P|CPU.DSI_TX1_P|B7|VDD_ANA_1V8|D|||TBD
|-
|rowspan="5"|J1.85167|rowspan="5"|TBDDSI_TX2_N|rowspan="5"|TBDCPU.DSI_TX2_N|rowspan="5"|TBDA8|rowspan="5"|TBDVDD_ANA_1V8|rowspan="5"|TBDD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J1.169|DSI_TX2_P|CPU.DSI_TX2_P|B8|VDD_ANA_1V8|D|||TBD
|-
|Pin ALT-2J1.171|DSI_TX3_N|CPU.DSI_TX3_N|A9|VDD_ANA_1V8|D|||TBD
|-
|Pin ALT-3J1.173|DSI_TX3_P|CPU.DSI_TX3_P|B9|VDD_ANA_1V8|D|||TBD
|-
|Pin ALTJ1.175|DGND|DGND| -5|TBD-|G|||
|-
|rowspan="5"|J1.87177|rowspan="5"|TBDSD2_CD_B|rowspan="5"|TBDCPU.GPIO_IO08|rowspan="5"|TBDM20|rowspan="5"|TBDNVCC_3V3|rowspan="5"|TBDIO|rowspan="5"|TBD
|Pin ALT-0
|TBDUSDHC2_CD_B
|-
|Pin ALT-1
|TBDENET_QOS_1588_EVENT0_IN
|-
|Pin ALT-2
|TBDI2C3_SCL
|-
|Pin ALT-34|TBDFLEXIO1_FLEXIO00
|-
|Pin ALT-5
|TBDGPIO3_IO00
|-
|rowspan="58"|J1.89179|rowspan="58"|TBDGPIO_IO00|rowspan="58"|TBDCPU.GPIO_IO00|rowspan="58"|TBDJ21|rowspan="58"|TBDNVCC_3V3|rowspan="58"|TBDIO|rowspan="58"|TBD
|Pin ALT-0
|TBDGPIO2_IO00
|-
|Pin ALT-1
|TBDI2C3_SDA
|-
|Pin ALT-2
|TBDCAM_CLK
|-
|Pin ALT-3
|TBDDISP_CLK |-|Pin ALT-4|SPI6_PCS0
|-
|Pin ALT-5
|TBDUART5_TX
|-
|Pin ALT-6|I2C5_SDA|-|Pin ALT-7|FLEXIO1_FLEXIO00|-|rowspan="58"|J1.91181|rowspan="58"|TBDGPIO_IO03|rowspan="58"|TBDCPU.GPIO_IO03|rowspan="58"|TBDK21|rowspan="58"|TBDNVCC_3V3|rowspan="58"|TBDIO|rowspan="58"|TBD
|Pin ALT-0
|TBDGPIO2_IO03
|-
|Pin ALT-1
|TBDI2C4_SCL
|-
|Pin ALT-2
|TBDCAM_HSYNC
|-
|Pin ALT-3
|TBDDISP_HSYNC|-|Pin ALT-4|SPI6_SCK
|-
|Pin ALT-5
|TBDUART5_RTS_B|-|Pin ALT-6|I2C6_SCL|-|Pin ALT-7|FLEXIO1_FLEXIO03
|-
|rowspan="58"|J1.93183|rowspan="58"|TBDGPIO_IO01|rowspan="58"|TBDCPU.GPIO_IO01|rowspan="58"|TBDK21|rowspan="58"|TBDNVCC_3V3|rowspan="58"|TBDIO|rowspan="58"|TBD
|Pin ALT-0
|TBDGPIO2_IO01
|-
|Pin ALT-1
|TBDI2C3_SCL
|-
|Pin ALT-2
|TBDCAM_DATA00
|-
|Pin ALT-3
|TBDDISP_DE|-|Pin ALT-4|SPI6_SIN
|-
|Pin ALT-5
|TBDUART5_RX|-|Pin ALT-6|I2C5_SCL
|-
|Pin ALT-7|FLEXIO1_FLEXIO01|-|J1.185| -| -| -| -|||||-|rowspan="5"|J1.95187|rowspan="5"|TBDUART1_TXD|rowspan="5"|TBDCPU.UART1_TXD//BOOT0|rowspan="5"|TBDE21|rowspan="5"|TBDNVCC_3V3|rowspan="5"|TBDIO|rowspan="5"|TBDUsed as default Linux console (Cortex-A55)
|Pin ALT-0
|TBDUART1_TX
|-
|Pin ALT-1
|TBDSECO_UART_TX
|-
|Pin ALT-2
|TBDSPI2_PCS0
|-
|Pin ALT-3
|TBDTPM1_CH1
|-
|Pin ALT-5
|TBDGPIO1_IO05//BOOT_MODE[0]
|-
|rowspan="5"|J1.97189|rowspan="5"|TBDUART1_RXD|rowspan="5"|TBDCPU.UART1_RXD|rowspan="5"|TBDE20|rowspan="5"|TBDNVCC_3V3|rowspan="5"|TBDIO|rowspan="5"|TBDUsed as default Linux console (Cortex-A55)
|Pin ALT-0
|TBDUART1_RX
|-
|Pin ALT-1
|TBDSECO_UART_RX
|-
|Pin ALT-2
|TBDSPI2_SIN
|-
|Pin ALT-3
|TBDTPM1_CH0
|-
|Pin ALT-5
|TBDGPIO1_IO04
|-
|rowspan="58"|J1.99191|rowspan="58"|TBDGPIO_IO12|rowspan="58"|TBDCPU.GPIO_IO12|rowspan="58"|TBDN20|rowspan="58"|TBDNVCC_3V3|rowspan="58"|TBDIO|rowspan="58"|TBD
|Pin ALT-0
|TBDGPIO2_IO12
|-
|Pin ALT-1
|TBDTPM3_CH2
|-
|Pin ALT-2
|TBDPDM_BIT_STREAM02
|-
|Pin ALT-3
|TBDDISP_DATA08|-|Pin ALT-4|SPI8_PCS0
|-
|Pin ALT-5
|TBDUART8_TX
|-
|Pin ALT-6|I2C8_SDA|-|Pin ALT-7|SAI3_RX_SYNC|-|rowspan="58"|J1.101193|rowspan="58"|TBDGPIO_IO13|rowspan="58"|TBDCPU.GPIO_IO13|rowspan="58"|TBDN21|rowspan="58"|TBDNVCC_3V3|rowspan="58"|TBDIO|rowspan="58"|TBD
|Pin ALT-0
|TBDGPIO2_IO13
|-
|Pin ALT-1
|TBDTPM4_CH2
|-
|Pin ALT-2
|TBDPDM_BIT_STREAM03
|-
|Pin ALT-3
|TBDDISP_DATA09|-|Pin ALT-4|SPI8_SIN
|-
|Pin ALT-5
|TBDUART8_RX|-|Pin ALT-6|I2C8_SCL
|-
|Pin ALT-7|FLEXIO1_FLEXIO13|-|rowspan="58"|J1.103195|rowspan="58"|TBDGPIO_IO02|rowspan="58"|TBDCPU.GPIO_IO02|rowspan="58"|TBDK21|rowspan="58"|TBDNVCC_3V3|rowspan="58"|TBDIO|rowspan="58"|TBD
|Pin ALT-0
|TBDGPIO2_IO13
|-
|Pin ALT-1
|TBDI2C4_SDA
|-
|Pin ALT-2
|TBDCAM_VSYNC
|-
|Pin ALT-3
|TBDDISP_VSYNC|-|Pin ALT-4|SPI6_SOUT
|-
|Pin ALT-5
|TBDUART5_CTS_B|-|Pin ALT-6|I2C6_SDA|-|Pin ALT-7|FLEXIO1_FLEXIO02
|-
|J1.197| -| -| -| -|||||-|rowspan="57"|J1.105199|rowspan="57"|TBDPDM_BIT_STREAM0|rowspan="57"|TBDCPU.PDM_BIT_STREAM0|rowspan="57"|TBDJ17|rowspan="57"|TBDNVCC_3V3|rowspan="57"|TBDIO|rowspan="57"|TBD
|Pin ALT-0
|TBDPDM_BIT_STREAM00
|-
|Pin ALT-1
|TBDMQS1_RIGHT
|-
|Pin ALT-2
|TBDSPI1_PCS1
|-
|Pin ALT-3
|TBDTPM1_EXTCLK|-|Pin ALT-4|LPTMR1_ALT2
|-
|Pin ALT-5
|TBDGPIO1_IO09
|-
|Pin ALT-6|CAN1_RX|-|rowspan="5"|J1.107201|rowspan="5"|TBDPDM_CLK|rowspan="5"|TBDCPU.PDM_CLK|rowspan="5"|TBDG17|rowspan="5"|TBDNVCC_3V3|rowspan="5"|TBDIO|rowspan="5"|TBD
|Pin ALT-0
|TBDPDM_CLK
|-
|Pin ALT-1
|TBDMQS1_LEFT
|-
|Pin ALT-24|TBD|-|Pin ALT-3|TBDLPTMR1_ALT1
|-
|Pin ALT-5
|TBDGPIO1_IO08
|-
|rowspan="5"|J1.109|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-06|TBDCAN1_TX
|-
|J1.203|DGND|DGND| -| -|G||||} ==Pinout Table EVEN pins declaration =={| class="wikitable" ! latexfontsize="scriptsize" |Pin ALT-1! latexfontsize="scriptsize" | Pin Name! latexfontsize="scriptsize" | Internal Connections ! latexfontsize="scriptsize" | Ball/pin # ! latexfontsize="scriptsize" |Voltagedomain! latexfontsize="scriptsize" | Type ! latexfontsize="scriptsize" | Notes! colspan="2" latexfontsize="scriptsize" |TBDAlternative Functions
|-
|Pin ALTJ1.2|DGND|DGND| -2|TBD-|G|||
|-
|Pin ALTJ1.4|3.3VIN|INPUT VOLTAGE| -|3.3VIN|S|||TBD
|-
|Pin ALTJ1.6|3.3VIN|INPUT VOLTAGE| -5|TBD3.3VIN|S|||
|-
|rowspan="5"|J1.1118|rowspan="5"|TBD3.3VIN|rowspan="5"|TBDINPUT VOLTAGE|rowspan="5"|TBD-|rowspan="5"|TBD3.3VIN|rowspan="5"|TBDS|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALTJ1.10|3.3VIN|INPUT VOLTAGE| -1|TBD3.3VIN|S|||
|-
|Pin ALTJ1.12|DGND|DGND| -2|TBD-|G|||
|-
|Pin ALT-3J1.14|SYS_NRST|PMIC.PMIC_RST_B|8||I|||TBD
|-
|Pin ALT-5J1.16|CPU_ON_OFF|CPU.ON_OFF|A19|NVCC_3V3|I|||TBD
|-
|rowspan="5"|J1.11318|rowspan="5"|TBDSOM_PGOOD|rowspan="5"|TBD-|rowspan="5"|TBD-|rowspan="5"|TBDNVCC_3V3|rowspan="5"|TBDO|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALTJ1.20|BOOT_MODE_SEL|BOOT MODE SELECTION| -1|TBDNVCC_3V3|I|internal pull-up to NVCC_3V3||
|-
|Pin ALTJ1.22|CPU_PORn|CPU.POR_BPMIC.POR_B|A169|NVCC_BBSM_1V8|I/O|internal pull-2up 100k to NVCC_BBSM_1V8||TBD
|-
|Pin ALT-3J1.24|PMIC_ON_REQ|PMIC.PMIC_ON_REQ|39|NVCC_BBSM_1V8|TBDI|internal pull-up 100k to NVCC_BBSM_1V8|Pin ALT-5|TBD
|-
|rowspan="56"|J1.11526|rowspan="56"|TBDPDM_BIT_STREAM1|rowspan="56"|TBDCPU.PDM_BIT_STREAM1|rowspan="56"|TBDJG18|rowspan="56"|TBDNVCC_3V3|rowspan="56"|TBDIO|rowspan="56"|TBD
|Pin ALT-0
|TBDPDM_BIT_STREAM01
|-
|Pin ALT-1
|TBDNMI_GLUE_NMI
|-
|Pin ALT-2
|TBDSPI2_PCS1
|-
|Pin ALT-3
|TBDTPM2_EXTCLK|-|Pin ALT-4|LPTMR1_ALT3
|-
|Pin ALT-5
|TBDGPIO1_IO10
|-
|rowspan="52"|J1.11728|rowspan="52"|TBDWDOG_ANY|rowspan="52"|TBDCPU.PDM_BIT_STREAM1|rowspan="52"|TBDJG18|rowspan="52"|TBDNVCC_3V3|rowspan="52"|TBDIO|rowspan="52"|TBD
|Pin ALT-0
|TBDWDOG1_WDOG_ANY
|-
|Pin ALT-15|TBDGPIO1_IO15
|-
|Pin ALTJ1.30|DGND|DGND| -2|TBD-|G|||
|-
|Pin ALT-3J1.32|TBDPMIC_STBY_REQ|PMIC.PMIC_STBY_REQ|40|NVCC_BBSM_1V8|O|-|Pin ALT-5|TBD
|-
|rowspan="58"|J1.11934|rowspan="58"|TBDGPIO_IO17|rowspan="58"|TBDCPU.GPIO_IO17|rowspan="58"|TBDR20|rowspan="58"|TBDNVCC_3V3|rowspan="58"|TBDIO|rowspan="58"|TBD
|Pin ALT-0
|TBDGPIO2_IO17
|-
|Pin ALT-1
|TBDSAI3_MCLK
|-
|Pin ALT-2
|TBDCAM_DATA08
|-
|Pin ALT-3
|TBDDISP_DATA13|-|Pin ALT-4|UART3_RTS_B
|-
|Pin ALT-5
|TBDSPI4_PCS1
|-
|Pin ALT-6|UART4_RTS_B|-|Pin ALT-7|FLEXIO1_FLEXIO17|-|rowspan="58"|J1.12136|rowspan="58"|TBDGPIO_IO21|rowspan="58"|TBDCPU.GPIO_IO21|rowspan="58"|TBDT21|rowspan="58"|TBDNVCC_3V3|rowspan="58"|TBDIO|rowspan="58"|TBD
|Pin ALT-0
|TBDGPIO2_IO21
|-
|Pin ALT-1
|TBDSAI3_TX_DATA00
|-
|Pin ALT-2
|TBDPDM_CLK
|-
|Pin ALT-3
|TBDDISP_DATA17|-|Pin ALT-4|SPI5_SCK
|-
|Pin ALT-5
|TBDSPI4_SCK
|-
|rowspan="5"|J1.123|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-06|TBDTPM4_CH1
|-
|Pin ALT-17|TBDSAI3_RX_BCLK
|-
| rowspan="3" |J1.38| rowspan="3" |GPIO_IO29| rowspan="3" |CPU.GPIO_IO29| rowspan="3" |Y21| rowspan="3" |NVCC_3V3| rowspan="3" |IO| rowspan="3" ||Pin ALT-20|TBDGPIO2_IO29
|-
|Pin ALT-31|TBDI2C3_SCL
|-
|Pin ALT-57|TBDFLEXIO1_FLEXIO29
|-
|rowspan="58"|J1.12540|rowspan="58"|TBDGPIO_IO07|rowspan="58"|TBDCPU.GPIO_IO07|rowspan="58"|TBDL21|rowspan="58"|TBDNVCC_3V3|rowspan="58"|TBDIO|rowspan="58"|TBD
|Pin ALT-0
|TBDGPIO2_IO07
|-
|Pin ALT-1
|TBDSPI3_PCS1
|-
|Pin ALT-2
|TBDCAM_DATA01
|-
|Pin ALT-3
|TBDDISP_DATA03|-|Pin ALT-4|SPI7_SCK
|-
|Pin ALT-5
|TBDUART6_RTS_B
|-
|Pin ALT-6|I2C7_SCL|-|Pin ALT-7|FLEXIO1_FLEXIO07|-|rowspan="58"|J1.12742|rowspan="58"|TBDGPIO_IO25//CAN_H|rowspan="58"|TBDCPU.GPIO_IO25CAN.CANH|rowspan="58"|TBDV217|rowspan="58"|TBDNVCC_3V3|rowspan="58"|TBDIO|rowspan="58"|TBDoptional CAN transceiver
|Pin ALT-0
|TBDGPIO2_IO25
|-
|Pin ALT-1
|TBDUSDHC3_DATA1
|-
|Pin ALT-2
|TBDCAN2_TX
|-
|Pin ALT-3
|TBDDISP_DATA21|-|Pin ALT-4|TPM4_CH3
|-
|Pin ALT-5
|TBDJTAG_MUX_TCK|-|Pin ALT-6|SPI7_PCS1
|-
|Pin ALT-7|FLEXIO1_FLEXIO25|-|rowspan="58"|J1.12944|rowspan="58"|TBDGPIO_IO27//CAN_L|rowspan="58"|TBDCPU.GPIO_IO27CAN.CANL|rowspan="58"|TBDW216|rowspan="58"|TBDNVCC_3V3|rowspan="58"|TBDIO|rowspan="58"|TBDoptional CAN transceiver
|Pin ALT-0
|TBDGPIO2_IO27
|-
|Pin ALT-1
|TBDUSDHC3_DATA3
|-
|Pin ALT-2
|TBDCAN2_RX
|-
|Pin ALT-3
|TBDDISP_DATA23|-|Pin ALT-4|TPM6_CH3
|-
|Pin ALT-5
|TBDJTAG_MUX_TMS
|-
|Pin ALT-6|SPI5_PCS1|-|Pin ALT-7|FLEXIO1_FLEXIO27|-|rowspan="57"|J1.13146|rowspan="57"|TBDGPIO_IO24|rowspan="57"|TBDCPU.GPIO_IO24|rowspan="57"|TBDU21|rowspan="57"|TBDNVCC_3V3|rowspan="57"|TBDIO|rowspan="57"|TBD
|Pin ALT-0
|TBDGPIO2_IO24
|-
|Pin ALT-1
|TBDUSDHC3_DATA0
|-
|Pin ALT-23|TBDDISP_DATA20
|-
|Pin ALT-34|TBDTPM3_CH3
|-
|Pin ALT-5
|TBDJTAG_MUX_TDO
|-
|Pin ALT-6|SPI6_PSC1|-|Pin ALT-7|FLEXIO1_FLEXIO24|-|rowspan="53"|J1.13348|rowspan="53"|TBDGPIO_IO28|rowspan="53"|TBDCPU.GPIO_IO28|rowspan="53"|TBDW20|rowspan="53"|TBDNVCC_3V3|rowspan="53"|TBDIO|rowspan="53"|TBD
|Pin ALT-0
|TBDGPIO2_IO28
|-
|Pin ALT-1
|TBDI2C3_SDA
|-
|Pin ALT-27|TBDFLEXIO1_FLEXIO28|-| rowspan="3" |J1.50| rowspan="3" |CCM_CLK01| rowspan="3" |CPU.CCM_CLK01| rowspan="3" |AA2| rowspan="3" |NVCC_3V3| rowspan="3" |IO| rowspan="3" ||Pin ALT-0|CCMSRCGPCMIX_CLK01
|-
|Pin ALT-34|TBDFLEXIO1_FLEXIO26
|-
|Pin ALT-5
|TBDGPIO3_IO26
|-
|rowspan="53"|J1.13552|rowspan="53"|TBDCCM_CLK02|rowspan="53"|TBDCPU.CCM_CLK02|rowspan="53"|TBDY3|rowspan="53"|TBDNVCC_3V3|rowspan="53"|TBDIO|rowspan="53"|TBD
|Pin ALT-0
|TBDCCMSRCGPCMIX_CLK02
|-
|Pin ALT-14|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBDFLEXIO1_FLEXIO27
|-
|Pin ALT-5
|TBDGPIO3_IO27
|-
|rowspan="53"|J1.13754|rowspan="53"|TBDCCM_CLK03|rowspan="53"|TBDCPU.CCM_CLK03|rowspan="53"|TBDU4|rowspan="53"|TBDNVCC_3V3|rowspan="53"|TBDIO|rowspan="53"|TBD
|Pin ALT-0
|TBDCCMSRCGPCMIX_CLK01
|-
|Pin ALT-14|TBDFLEXIO2_FLEXIO28|-|Pin ALT-5|GPIO4_IO28
|-
|Pin ALTJ1.56|DGND|DGND| -2|TBD-|G|||
|-
|Pin ALT-3J1.58|ETH_RSTn|LAN.RESETn|43|NVCC_3V3|I|Hardware mounting option||TBD
|-
|Pin ALT-5J1.60|ETH_INTn|LAN.INT_N|39|NVCC_3V3|O|Hardware mounting option||TBD
|-
|rowspan="56"|J1.13962|rowspan="56"|TBDSAI1_RXD0|rowspan="56"|TBDCPU.SAI1_RXD0|rowspan="56"|TBDH20|rowspan="56"|TBDNVCC_3V3|rowspan="56"|TBDIO|rowspan="56"|TBD
|Pin ALT-0
|TBDSAI1_RX_DATA00
|-
|Pin ALT-1
|TBDSAI1_MCLK
|-
|Pin ALT-2
|TBDSPI1_SOUT
|-
|Pin ALT-3
|TBDUART2_DSR_B|-|Pin ALT-4|MQS1_RIGHT
|-
|Pin ALT-5
|TBDGPIO1_IO14
|-
|rowspan="53"|J1.14164|rowspan="53"|TBDCCM_CLK04|rowspan="53"|TBDCPU.CCM_CLK04|rowspan="53"|TBDV4|rowspan="53"|TBDNVCC_3V3|rowspan="53"|TBDIO|rowspan="53"|TBD
|Pin ALT-0
|TBDCCMSRCGPCMIX_CLK04
|-
|Pin ALT-14|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBDFLEXIO2_FLEXIO29
|-
|Pin ALT-5
|TBDGPIO4_IO29
|-
|rowspan="58"|J1.14366|rowspan="58"|TBDGPIO_IO16|rowspan="58"|TBDCPU.GPIO_IO16|rowspan="58"|TBDR21|rowspan="58"|TBDNVCC_3V3|rowspan="58"|TBDIO|rowspan="58"|TBD
|Pin ALT-0
|TBDGPIO2_IO16
|-
|Pin ALT-1
|TBDSAI3_TX_BCLK
|-
|Pin ALT-2
|TBDPDM_BIT_STREAM02
|-
|Pin ALT-3
|TBDDISP_DATA12|-|Pin ALT-4|UART3_CTS_B
|-
|Pin ALT-5
|TBDSPI4_PCS2|-|Pin ALT-6|UART4_CTS_B|-|Pin ALT-7|FLEXIO1_FLEXIO16
|-
|rowspan="58"|J1.14568|rowspan="58"|TBDGPIO_IO19|rowspan="58"|TBDCPU.GPIO_IO19|rowspan="58"|TBDR17|rowspan="58"|TBDNVCC_3V3|rowspan="58"|TBDIO|rowspan="58"|TBD
|Pin ALT-0
|TBDGPIO2_IO19
|-
|Pin ALT-1
|TBDSAI3_RX_SYNC
|-
|Pin ALT-2
|TBDPDM_BIT_STREAM03
|-
|Pin ALT-3
|TBDDISP_DATA15|-|Pin ALT-4|SPI5_SIN
|-
|Pin ALT-5
|TBDSPI4_SIN|-|Pin ALT-6|TPM4_CH2|-|Pin ALT-7|SAI3_TX_DATA00
|-
|rowspan="58"|J1.14770|rowspan="58"|TBDGPIO_IO26|rowspan="58"|TBDCPU.GPIO_IO26|rowspan="58"|TBDV20|rowspan="58"|TBDNVCC_3V3|rowspan="58"|TBDIO|rowspan="58"|TBD
|Pin ALT-0
|TBDGPIO2_IO26
|-
|Pin ALT-1
|TBDUSDHC3_DATA2
|-
|Pin ALT-2
|TBDPDM_BIT_STREAM01
|-
|Pin ALT-3
|TBDDISP_DATA22|-|Pin ALT-4|TPM3_CH3
|-
|Pin ALT-5
|TBDJTAG_MUX_TDI
|-
|Pin ALT-6|SPI8_PCS1|-|Pin ALT-7|SAI3_TX_SYNC|-|rowspan="58"|J1.14972|rowspan="58"|TBDGPIO_IO20|rowspan="58"|TBDCPU.GPIO_IO20|rowspan="58"|TBDT20|rowspan="58"|TBDNVCC_3V3|rowspan="58"|TBDIO|rowspan="58"|TBD
|Pin ALT-0
|TBDGPIO2_IO20
|-
|Pin ALT-1
|TBDSAI3_RX_DATA00
|-
|Pin ALT-2
|TBDPDM_BIT_STREAM00
|-
|Pin ALT-3
|TBDDISP_DATA16|-|Pin ALT-4|SPI5_SOUT
|-
|Pin ALT-5
|TBDSPI4_SOUT
|-
|Pin ALT-6|TPM3_CH1|-|Pin ALT-7|FLEXIO1_FLEXIO20|-|rowspan="58"|J1.15174|rowspan="58"|TBDGPIO_IO22|rowspan="58"|TBDCPU.GPIO_IO22|rowspan="58"|TBDU18|rowspan="58"|TBDNVCC_3V3|rowspan="58"|TBDIO|rowspan="58"|TBD
|Pin ALT-0
|TBDGPIO2_IO22
|-
|Pin ALT-1
|TBDUSDHC3_CLK
|-
|Pin ALT-2
|TBDSPDIF_IN
|-
|Pin ALT-3
|TBDDISP_DATA18|-|Pin ALT-4|TPM5_CH1
|-
|Pin ALT-5
|TBDTPM6_EXTCLK|-|Pin ALT-6|I2C5_SDA|-|Pin ALT-7|FLEXIO1_FLEXIO22
|-
|rowspan="57"|J1.15376|rowspan="57"|TBDGPIO_IO23|rowspan="57"|TBDCPU.GPIO_IO23|rowspan="57"|TBDU20|rowspan="57"|TBDNVCC_3V3|rowspan="57"|TBDIO|rowspan="57"|TBD
|Pin ALT-0
|TBDGPIO2_IO23
|-
|Pin ALT-1
|TBDUSDHC3_CMD
|-
|Pin ALT-2
|TBDSPDIF_OUT
|-
|Pin ALT-3
|TBDDISP_DATA19|-|Pin ALT-4|TPM6_CH1|-|Pin ALT-6|I2C5_SCL
|-
|Pin ALT-57|TBDFLEXIO1_FLEXIO23
|-
|rowspan="58"|J1.15578|rowspan="58"|TBDGPIO_IO05|rowspan="58"|TBDCPU.GPIO_IO05|rowspan="58"|TBDL18|rowspan="58"|TBDNVCC_3V3|rowspan="58"|TBDIO|rowspan="58"|TBD
|Pin ALT-0
|TBDGPIO2_IO05
|-
|Pin ALT-1
|TBDTPM4_CH0
|-
|Pin ALT-2
|TBDPDM_BIT_STREAM00
|-
|Pin ALT-3
|TBDDISP_DATA01|-|Pin ALT-4|SPI7_SIN
|-
|Pin ALT-5
|TBDUART6_RX|-|Pin ALT-6|I2C6_SCL|-|Pin ALT-7|FLEXIO1_FLEXIO05
|-
|rowspan="58"|J1.15780|rowspan="58"|TBDGPIO_IO04|rowspan="58"|TBDCPU.GPIO_IO04|rowspan="58"|TBDL17|rowspan="58"|TBDNVCC_3V3|rowspan="58"|TBDIO|rowspan="58"|TBD
|Pin ALT-0
|TBDGPIO2_IO04
|-
|Pin ALT-1
|TBDTPM3_CH0
|-
|Pin ALT-2
|TBDPDM_CLK
|-
|Pin ALT-3
|TBDDISP_DATA00|-|Pin ALT-4|SPI7_PCS0
|-
|Pin ALT-5
|TBDUART6_TX
|-
|rowspan="5"|J1.159|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-06|TBDI2C6_SDA
|-
|Pin ALT-17|TBDFLEXIO1_FLEXIO04
|-
|Pin ALTJ1.82|DGND|DGND| -2|TBD-|G|||
|-
| rowspan="1" |J1.84| rowspan="1" |TAMPER0| rowspan="1" |CPU.TAMPER0| rowspan="1" |B16| rowspan="1" |NVCC_3V3| rowspan="1" |I| rowspan="1" ||Pin ALT-30|TBDBBSMMIX.TAMPER0
|-
| rowspan="1" |J1.86| rowspan="1" |TAMPER1| rowspan="1" |CPU.TAMPER1| rowspan="1" |F14| rowspan="1" |NVCC_3V3| rowspan="1" |I| rowspan="1" ||Pin ALT-50|TBDBBSMMIX.TAMPER1
|-
|rowspan="52"|J1.16188|rowspan="52"|TBDCLKIN1|rowspan="52"|TBDCPU.CLKIN1|rowspan="52"|TBDB17|rowspan="52"|TBDNVCC_3V3|rowspan="52"|TBDI|rowspan="52"|TBD
|Pin ALT-0
|TBDANAMIX.CLKIN1
|-
|Pin ALT-1
|TBDANAMIX.ESD_DIODE
|-
| rowspan="2" |J1.90| rowspan="2" |CLKIN2| rowspan="2" |CPU.CLKIN2| rowspan="2" |A18| rowspan="2" |NVCC_3V3| rowspan="2" |I| rowspan="2" ||Pin ALT-20|TBDANAMIX.CLKIN2
|-
|Pin ALT-31|TBDANAMIX.ATX
|-
|Pin ALT-5|TBD|-|rowspan="56"|J1.16392|rowspan="56"|TBDJTAG_TDI|rowspan="56"|TBDCPU.DAP_TDI|rowspan="56"|TBDW1|rowspan="56"|TBDNVCC_3V3|rowspan="56"|TBDIO|rowspan="56"|TBD
|Pin ALT-0
|TBDJTAG_MUX_TDI
|-
|Pin ALT-1
|TBDMQS2_LEFT
|-
|Pin ALT-23|TBDCAN2_TX
|-
|Pin ALT-34|TBDFLEXIO2_FLEXIO30
|-
|Pin ALT-5
|TBDGPIO3_IO28|-|Pin ALT-6|UART5_RX
|-
|rowspan="54"|J1.16594|rowspan="54"|TBDJTAG_TMS|rowspan="54"|TBDCPU.DAP_TMS_SWDIO|rowspan="54"|TBDW2|rowspan="54"|TBDNVCC_3V3|rowspan="54"|TBDIO|rowspan="54"|TBD
|Pin ALT-0
|TBDJTAG_MUX_TMS
|-
|Pin ALT-14|TBDFLEXIO2_FLEXIO31
|-
|Pin ALT-25|TBDGPIO3_IO29
|-
|Pin ALT-36|TBDUART5_RTS_B
|-
|Pin ALT-5|TBD|-|rowspan="54"|J1.16796|rowspan="54"|TBDJTAG_TMS|rowspan="54"|TBDCPU.DAP_TCLK_SWCLK|rowspan="54"|TBDY1|rowspan="54"|TBDNVCC_3V3|rowspan="54"|TBDIO|rowspan="54"|TBD
|Pin ALT-0
|TBDJTAG_MUX_TCK
|-
|Pin ALT-14|TBDFLEXIO1_FLEXIO30
|-
|Pin ALT-25|TBDGPIO3_IO30
|-
|Pin ALT-36|TBDUART5_CTS_B
|-
|Pin ALT-5|TBD|-|rowspan="56"|J1.16998|rowspan="56"|TBDJTAG_TDO|rowspan="56"|TBDCPU.DAP_TDO_TRACE_SWO|rowspan="56"|TBDW1|rowspan="56"|TBDNVCC_3V3|rowspan="56"|TBDIO|rowspan="56"|TBD
|Pin ALT-0
|TBDJTAG_MUX_TDO
|-
|Pin ALT-1
|TBDMQS2_RIGHT
|-
|Pin ALT-23|TBDCAN2_RX
|-
|Pin ALT-34|TBDFLEXIO1_FLEXIO31
|-
|Pin ALT-5
|TBDGPIO3_IO31
|-
|rowspan="5"|J1.171|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-06|TBDUART5_TX
|-
|Pin ALTJ1.100|DGND|DGND| -1|TBD-|G|||
|-
|Pin ALT-2J1.102|CSI_CLK_N|CPU.MIPI_CSI1_CLK_N|D10|VDD_ANA_1V8|D|||TBD
|-
|Pin ALT-3J1.104|CSI_CLK_P|CPU.MIPI_CSI1_CLK_P|E10|VDD_ANA_1V8|D|||TBD
|-
|Pin ALT-5J1.106|CSI_D0_N|CPU.MIPI_CSI1_D0_N|A11|VDD_ANA_1V8|D|||TBD
|-
|rowspan="5"|J1.173108|rowspan="5"|TBDCSI_D0_P|rowspan="5"|TBDCPU.MIPI_CSI1_D0_P|rowspan="5"|TBDB11|rowspan="5"|TBDVDD_ANA_1V8|rowspan="5"|TBDD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J1.110|CSI_D1_N|CPU.MIPI_CSI1_D1_N|A10|VDD_ANA_1V8|D|||TBD
|-
|Pin ALT-2J1.112|CSI_D1_P|CPU.MIPI_CSI1_D1_P|B10|VDD_ANA_1V8|D|||TBD
|-
|Pin ALT-3J1.114|USB1_RX_N|CPU.USB1_RX_N|A12|VDD_ANA_1V8|D|Only for i.MX933x/i.MX935x||TBD
|-
|Pin ALT-5J1.116|USB1_RX_P|CPU.USB1_RX_P|B12|VDD_ANA_1V8|D|Only for i.MX933x/i.MX935x||TBD
|-
|rowspan="5"|J1.175118|rowspan="5"|TBDUSB1_TX_N|rowspan="5"|TBDCPU.USB1_TX_N|rowspan="5"|TBDA13|rowspan="5"|TBDVDD_ANA_1V8|rowspan="5"|TBDD|rowspan="5"|TBDOnly for i.MX933x/i.MX935x|Pin ALT-0|TBD
|-
|Pin ALT-1J1.120|USB1_TX_P|CPU.USB1_TX_P|B13|VDD_ANA_1V8|D|Only for i.MX933x/i.MX935x||TBD
|-
|Pin ALT-2J1.122|DGND|TBDDGND|-|Pin ALT-3|TBDG|||
|-
|Pin ALT-5|TBD|-|rowspan="56"|J1.177124|rowspan="56"|TBDENET1_MDC|rowspan="56"|TBDCPU.ENET1_MDC|rowspan="56"|TBDAA11|rowspan="56"|TBDNVCC_3V3|rowspan="56"|TBDIO|rowspan="56"|TBD
|Pin ALT-0
|TBDENET_QOS_MDC
|-
|Pin ALT-1
|TBDUART3_DCR_B
|-
|Pin ALT-2
|TBDI3C2_SCL
|-
|Pin ALT-3
|TBDUSB1_OTG_ID|-|Pin ALT-4|FLEXIO2_FLEXIO00
|-
|Pin ALT-5
|TBDGPIO4_IO00
|-
|rowspan="56"|J1.179126|rowspan="56"|TBDENET1_MDIO|rowspan="56"|TBDCPU.ENET1_MDIO|rowspan="56"|TBDAA10|rowspan="56"|TBDNVCC_3V3|rowspan="56"|TBDIO|rowspan="56"|TBD
|Pin ALT-0
|TBDENET_QOS_MDIO
|-
|Pin ALT-1
|TBDUART3_RIN_B
|-
|Pin ALT-2
|TBDI3C2_SDA
|-
|Pin ALT-3
|TBDUSB1_OTG_PWR|-|Pin ALT-4|FLEXIO2_FLEXIO01
|-
|Pin ALT-5
|TBDGPIO4_IO01
|-
|rowspan="53"|J1.181128|rowspan="53"|TBDSD1_CLK|rowspan="53"|TBDCPU.SD1_CLK|rowspan="53"|TBDY11|rowspan="53"|TBDNVCC_3V3|rowspan="53"|TBDIO|rowspan="53"|TBD
|Pin ALT-0
|TBDUSDHC1_CLK
|-
|Pin ALT-14|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBDFLEXIO1_FLEXIO08
|-
|Pin ALT-5
|TBDGPIO3_IO08
|-
|rowspan="53"|J1.183130|rowspan="53"|TBDSD1_CMD|rowspan="53"|TBDCPU.SD1_CMD|rowspan="53"|TBDAA12|rowspan="53"|TBDNVCC_3V3|rowspan="53"|TBDIO|rowspan="53"|TBD
|Pin ALT-0
|TBDUSDHC1_CMD
|-
|Pin ALT-14|TBDFLEXIO1_FLEXIO09
|-
|Pin ALT-25|TBDGPIO3_IO09
|-
|Pin ALT-3J1.132|TBDETH1_LED5|LAN.LED5/GPIO4|13|NVCC_3V3|O|-|Pin ALT-5|TBD
|-
|rowspan="54"|J1.185134|rowspan="54"|TBDSD1_STROBE|rowspan="54"|TBDCPU.SD1_CLK|rowspan="54"|TBDY11|rowspan="54"|TBDNVCC_3V3|rowspan="54"|TBDIO|rowspan="54"|TBD
|Pin ALT-0
|TBDUSDHC1_CLK
|-
|Pin ALT-1
|TBDFLEXSPI1_A_DQS
|-
|Pin ALT-24|TBD|-|Pin ALT-3|TBDFLEXIO1_FLEXIO18
|-
|Pin ALT-5
|TBDGPIO3_IO018
|-
|J1.136||| | |||||-|rowspan="53"|J1.187138|rowspan="53"|TBDSD1_DATA0|rowspan="53"|TBDCPU.SD1_DATA0|rowspan="53"|TBDAA14|rowspan="53"|TBDNVCC_3V3|rowspan="53"|TBDIO|rowspan="53"|TBD
|Pin ALT-0
|TBDUSDHC1_DATA0|-|Pin ALT-4|FLEXIO1_FLEXIO10
|-
|Pin ALT-15|TBDGPIO3_IO10
|-
| rowspan="3" |J1.140| rowspan="3" |SD1_DATA1| rowspan="3" |CPU.SD1_DATA1| rowspan="3" |AA15| rowspan="3" |NVCC_3V3| rowspan="3" |IO| rowspan="3" ||Pin ALT-20|TBDUSDHC1_DATA1
|-
|Pin ALT-34|TBDFLEXIO1_FLEXIO11
|-
|Pin ALT-5
|TBDGPIO3_IO11
|-
|rowspan="53"|J1.189142|rowspan="53"|TBDSD1_DATA2|rowspan="53"|TBDCPU.SD1_DATA2|rowspan="53"|TBDAA16|rowspan="53"|TBDNVCC_3V3|rowspan="53"|TBDIO|rowspan="53"|TBD
|Pin ALT-0
|TBDUSDHC1_DATA2
|-
|Pin ALT-14|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBDFLEXIO1_FLEXIO12
|-
|Pin ALT-5
|TBDGPIO3_IO12
|-
|rowspan="53"|J1.191144|rowspan="53"|TBDSD1_DATA3|rowspan="53"|TBDCPU.SD1_DATA3|rowspan="53"|TBDY11|rowspan="53"|TBDNVCC_3V3|rowspan="53"|TBDIO|rowspan="53"|TBD
|Pin ALT-0
|TBDUSDHC1_DATA3
|-
|Pin ALT-1
|TBDFLEXSPI1_A_SS1_B
|-
|Pin ALT-24|TBDFLEXIO1_FLEXIO13
|-
|Pin ALT-35|TBDGPIO3_IO13
|-
|Pin ALTJ1.146|DGND|DGND| -5|TBD-|G|||
|-
|rowspan="54"|J1.193148|rowspan="54"|TBDSD1_DATA4|rowspan="54"|TBDCPU.SD1_DATA4|rowspan="54"|TBDY13|rowspan="54"|TBDNVCC_3V3|rowspan="54"|TBDIO|rowspan="54"|TBD
|Pin ALT-0
|TBDUSDHC1_DATA4
|-
|Pin ALT-1
|TBDFLEXSPI1_A_DATA04
|-
|Pin ALT-24|TBD|-|Pin ALT-3|TBDFLEXIO1_FLEXIO14
|-
|Pin ALT-5
|TBDGPIO3_IO14
|-
|rowspan="54"|J1.195150|rowspan="54"|TBDSD1_DATA5|rowspan="54"|TBDCPU.SD1_DATA5|rowspan="54"|TBDY14|rowspan="54"|TBDNVCC_3V3|rowspan="54"|TBDIO|rowspan="54"|TBD
|Pin ALT-0
|TBDUSDHC1_DATA5
|-
|Pin ALT-1
|TBDFLEXSPI1_A_DATA05
|-
|Pin ALT-24|TBDFLEXIO1_FLEXIO15
|-
|Pin ALT-35|TBDGPIO3_IO15|-| rowspan="4" |J1.152| rowspan="4" |SD1_DATA5| rowspan="4" |CPU.SD1_DATA6| rowspan="4" |Y15| rowspan="4" |NVCC_3V3| rowspan="4" |IO| rowspan="4" ||Pin ALT-0|USDHC1_DATA6|-|Pin ALT-1|FLEXSPI1_A_DATA06|-|Pin ALT-4|FLEXIO1_FLEXIO16
|-
|Pin ALT-5
|TBDGPIO3_IO16
|-
|rowspan="54"|J1.197154|rowspan="54"|TBDSD1_DATA7|rowspan="54"|TBDCPU.SD1_DATA7|rowspan="54"|TBDY16|rowspan="54"|TBDNVCC_3V3|rowspan="54"|TBDIO|rowspan="54"|TBD
|Pin ALT-0
|TBDUSDHC1_DATA7
|-
|Pin ALT-1
|TBDFLEXSPI1_A_DATA07|-|Pin ALT-4|FLEXIO1_FLEXIO17|-|Pin ALT-5|GPIO3_IO17|-| rowspan="4" |J1.156| rowspan="4" |ENET2_TD3| rowspan="4" |CPU.ENET2_TD3| rowspan="4" |T10| rowspan="4" |NVCC_3V3| rowspan="4" |IO| rowspan="4" ||Pin ALT-0|ENET1_RGMII_TD3
|-
|Pin ALT-2
|TBDSAI2_RX_DATA00
|-
|Pin ALT-34|TBDFLEXIO2_FLEXIO16
|-
|Pin ALT-5
|TBDGPIO4_IO16
|-
|rowspan="5"|J1.199158|rowspan="5"|TBDENET2_TD2|rowspan="5"|TBDCPU.ENET2_TD2|rowspan="5"|TBDV8|rowspan="5"|TBDNVCC_3V3|rowspan="5"|TBDIO|rowspan="5"|TBD
|Pin ALT-0
|TBDENET1_RGMII_TD2
|-
|Pin ALT-1
|TBDENET1_TX_CLK // CCMSRCGPMCMIX.ENET_REF_CLK_ROOT
|-
|Pin ALT-2
|TBDSAI2_RX_DATA01
|-
|Pin ALT-34|TBDFLEXIO2_FLEXIO17
|-
|Pin ALT-5
|TBDGPIO4_IO17
|-
|rowspan="5"|J1.201160|rowspan="5"|TBDENET2_TD1|rowspan="5"|TBDCPU.ENET2_TD1|rowspan="5"|TBDU8|rowspan="5"|TBDNVCC_3V3|rowspan="5"|TBDIO|rowspan="5"|TBD
|Pin ALT-0
|TBDENET1_RGMII_TD1
|-
|Pin ALT-1
|TBDUART4_RTS_B
|-
|Pin ALT-2
|TBDSAI2_RX_DATA02
|-
|Pin ALT-34|TBDFLEXIO2_FLEXIO18
|-
|Pin ALT-5
|TBDGPIO4_IO18
|-
|rowspan="5"|J1.203162|rowspan="5"|TBDENET2_TD0|rowspan="5"|TBDCPU.ENET2_TD0|rowspan="5"|TBDT8|rowspan="5"|TBDNVCC_3V3|rowspan="5"|TBDIO|rowspan="5"|TBD
|Pin ALT-0
|TBDENET1_RGMII_TD0
|-
|Pin ALT-1
|TBDUART4_TX
|-
|Pin ALT-2
|TBDSAI2_RX_DATA03
|-
|Pin ALT-34|TBDFLEXIO2_FLEXIO19
|-
|Pin ALT-5
|TBDGPIO4_IO19
|-
|}J1.164 ==Pinout Table EVEN pins declaration == {| class="wikitable" ! latexfontsize="scriptsize"| Pin DGND! latexfontsize="scriptsize"| Pin NameDGND! latexfontsize="scriptsize"| Internal Connections -! latexfontsize="scriptsize"| Ball/pin # -! latexfontsize="scriptsize"| Voltage domainG! latexfontsize="scriptsize"| Type ! latexfontsize="scriptsize"| Notes! colspan="2" latexfontsize="scriptsize"| Alternative Functions
|-
|rowspan="5"|J1.2166|rowspan="5"|SD2_CMDENET2_XC|rowspan="5"|CPU.SD2_CMDENET2_XC|rowspan="5"|F19U6|rowspan="5"|AXEL_IO_3V3NVCC_3V3|rowspan="5"|IO|rowspan="5"|Notes
|Pin ALT-0
|SD2_CMDENET1_RGMI_TXC
|-
|Pin ALT-1
|ECSPI5_MOSIENET1_TX_ER
|-
|Pin ALT-2
|KEY_ROW5SAI2_TX_BCLK
|-
|Pin ALT-34|AUD4_RXCFLEXIO2_FLEXIO21
|-
|Pin ALT-5
|GPIO1_IO11GPIO4_IO21
|-
|rowspan="5"|J1.4168|rowspan="5"|TBDENET2_TX_CTL|rowspan="5"|TBDCPU.ENET2_TX_CTL|rowspan="5"|TBDV6|rowspan="5"|TBDNVCC_3V3|rowspan="5"|TBDIO|rowspan="5"|TBD
|Pin ALT-0
|TBDENET1_RGMI_TX_CTL
|-
|Pin ALT-1
|TBDUART4_DTR_B
|-
|Pin ALT-2
|TBDSAI2_TX_SYNC
|-
|Pin ALT-34|TBDFLEXIO2_FLEXIO20
|-
|Pin ALT-5
|TBDGPIO4_IO20
|-
|rowspan="5"|J1.6170|rowspan="5"|TBDENET2_MDC|rowspan="5"|TBDCPU.ENET2_MDC|rowspan="5"|TBDY7|rowspan="5"|TBDNVCC_3V3|rowspan="5"|TBDIO|rowspan="5"|TBD
|Pin ALT-0
|TBDENET1_MDC
|-
|Pin ALT-1
|TBDUART4_DCR_B
|-
|Pin ALT-2
|TBDSAI2_RX_SYNC
|-
|Pin ALT-34|TBDFLEXIO2_FLEXIO14
|-
|Pin ALT-5
|TBDGPIO4_IO14
|-
|rowspan="5"|J1.8172|rowspan="5"|TBDENET2_MDIO|rowspan="5"|TBDCPU.ENET2_MDIO|rowspan="5"|TBDAA6|rowspan="5"|TBDNVCC_3V3|rowspan="5"|TBDIO|rowspan="5"|TBD
|Pin ALT-0
|TBDENET1_MDIO
|-
|Pin ALT-1
|TBDUART4_RIN_B
|-
|Pin ALT-2
|TBDSAI2_RX_BCLK
|-
|Pin ALT-34|TBDFLEXIO2_FLEXIO15
|-
|Pin ALT-5
|TBDGPIO4_IO15
|-
|rowspan="5"|J1.10174|rowspan="5"|TBDENET2_RX_CTL|rowspan="5"|TBDCPU.ENET2_RX_CTL|rowspan="5"|TBDY4|rowspan="5"|TBDNVCC_3V3|rowspan="5"|TBDIO|rowspan="5"|TBD
|Pin ALT-0
|TBDENET1_RGMII_RX_CTL
|-
|Pin ALT-1
|TBDUART4_DSR_B
|-
|Pin ALT-2
|TBDSAI2_TX_DATA00
|-
|Pin ALT-34|TBDFLEXIO2_FLEXIO22
|-
|Pin ALT-5
|TBDGPIO4_IO22
|-
|rowspan="5"|J1.12176|rowspan="5"|TBDENET2_RD0|rowspan="5"|TBDCPU.ENET2_RD0|rowspan="5"|TBDAA4|rowspan="5"|TBDNVCC_3V3|rowspan="5"|TBDIO|rowspan="5"|TBD
|Pin ALT-0
|TBDENET1_RGMII_RD0
|-
|Pin ALT-1
|TBDUART4_RX
|-
|Pin ALT-2
|TBDSAI2_TX_DATA02
|-
|Pin ALT-34|TBDFLEXIO2_FLEXIO24
|-
|Pin ALT-5
|TBDGPIO4_IO24
|-
|rowspan="5"|J1.14178|rowspan="5"|TBDENET2_RD1|rowspan="5"|TBDCPU.ENET2_RD1|rowspan="5"|TBDY5|rowspan="5"|TBDNVCC_3V3|rowspan="5"|TBDIO|rowspan="5"|TBD
|Pin ALT-0
|TBDENET1_RGMII_RD1
|-
|Pin ALT-1
|TBDSPDIF_IN
|-
|Pin ALT-2
|TBDSAI2_TX_DATA03
|-
|Pin ALT-34|TBDFLEXIO2_FLEXIO25
|-
|Pin ALT-5
|TBDGPIO4_IO25
|-
|rowspan="56"|J1.16180|rowspan="56"|TBDENET2_RD2|rowspan="56"|TBDCPU.ENET2_RD2|rowspan="56"|TBDAA5|rowspan="56"|TBDNVCC_3V3|rowspan="56"|TBDIO|rowspan="56"|TBD
|Pin ALT-0
|TBDENET1_RGMII_RD1
|-
|Pin ALT-1
|TBDUART4_CTS_B
|-
|Pin ALT-2
|TBDSAI2_MCLK
|-
|Pin ALT-3
|TBDMQS2_RIGHT|-|Pin ALT-4|FLEXIO2_FLEXIO26
|-
|Pin ALT-5
|TBDGPIO4_IO26
|-
|rowspan="56"|J1.18182|rowspan="56"|TBDENET2_RD3|rowspan="56"|TBDCPU.ENET2_RD3|rowspan="56"|TBDY6|rowspan="56"|TBDNVCC_3V3|rowspan="56"|TBDIO|rowspan="56"|TBD
|Pin ALT-0
|TBDENET1_RGMII_RD3
|-
|Pin ALT-1
|TBDSPDIF_OUT
|-
|Pin ALT-2
|TBDSPDIF_IN
|-
|Pin ALT-3
|TBDMQS2_LEFT|-|Pin ALT-4|FLEXIO2_FLEXIO27
|-
|Pin ALT-5
|TBDGPIO4_IO27
|-
|rowspan="5"|J1.20184|rowspan="5"|TBDENET2_RXC|rowspan="5"|TBDCPU.ENET2_RXC|rowspan="5"|TBDAA3|rowspan="5"|TBDNVCC_3V3|rowspan="5"|TBDIO|rowspan="5"|TBD
|Pin ALT-0
|TBDENET1_RGMII_RXC
|-
|Pin ALT-1
|TBDENET1_RX_ER
|-
|Pin ALT-2
|TBDSAI2_TX_DATA01
|-
|Pin ALT-34|TBDFLEXIO2_FLEXIO23
|-
|Pin ALT-5
|TBDGPIO4_IO23
|-
|rowspan="5"|J1.22186|rowspan="5"|TBDUSB1_VBUS|rowspan="5"|TBDCPU.USB1_VBUS|rowspan="5"|TBDF13|rowspan="5"|TBDNVCC_3V3|rowspan="5"|TBDD|rowspan="5"|TBD(3V3 reference signal)|Pin ALT-0|TBD
|-
|Pin ALT-1J1.188|USB2_VBUS|CPU.USB2_VBUS|E14|NVCC_3V3|D|(3V3 reference signal)||TBD
|-
|Pin ALTJ1.190|DGND|DGND| -2|TBD-|G|||
|-
|Pin ALT-3J1.192|USB1_ID|CPU.USB1_ID|C11||D|||TBD
|-
|Pin ALT-5J1.194|USB2_ID|CPU.USB2_ID|E12||D|||TBD
|-
|rowspan="5"|J1.24196|rowspan="5"|TBDUSB1_DN|rowspan="5"|TBDCPU.USB1_DN|rowspan="5"|TBDA14|rowspan="5"|TBD|rowspan="5"|TBDD|rowspan="5"|TBD|Pin ALT-0|TBD
|-
|Pin ALT-1J1.198|USB1_DP|CPU.USB1_DP|B14||D|||TBD
|-
|Pin ALT-2J1.200|USB2_DP|CPU.USB2_DP|B15||D|||TBD
|-
|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.26|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.28|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.30|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.32|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.34|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.36|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.38|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.40|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.42|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.44|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.46|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.48|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.50|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.52|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.54|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.56|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.58|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.60|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.62|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.64|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.66|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.68|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.70|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.72|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.74|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.76|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.78|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.80|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.82|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.84|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.86|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.88|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.90|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.92|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.94|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.96|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.98|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.100|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.102|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.104|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.106|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.108|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.110|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.112|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.114|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.116|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.118|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.120|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.122|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.124|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.126|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.128|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.130|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.132|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.134|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.136|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.138|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.140|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.142|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.144|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.146|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.148|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.150|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.152|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.154|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.156|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.158|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.160|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.162|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.164|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.166|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.168|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.170|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.172|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.174|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.176|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.178|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.180|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.182|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.184|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.186|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.188|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.190|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.192|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.194|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.196|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.198|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.200|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-|rowspan="5"|J1.202|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBD|-|Pin ALT-3|TBD|-|Pin ALT-5|TBD|-USB2_DN|rowspan="5"|J1CPU.204|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|rowspan="5"|TBD|Pin ALT-0|TBD|-|Pin ALT-1|TBD|-|Pin ALT-2|TBDUSB2_DN|-A15|Pin ALT-3|TBDD|-|Pin ALT-5|TBD
|-
|J1.204
|DGND
|DGND
| -
| -
|G
|
|
|
|}
U0016
a000298_approval, dave_user
551
edits
Retrieved from "https://wiki.dave.eu/index.php/Special:MobileDiff/17890...20284"