Bureaucrats, dave_user, Administrators
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<section begin=History/>
{| style="border-collapse:collapse; "
!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History
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!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes
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|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|2023/09/13
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|First release
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<section begin=Body/>
==Peripheral UART ==
LPUART provides asynchronous, serial communication capabilities with external devices. LPUART can continue operating when the processor is in Low-Power mode, if an appropriate peripheral clock is available.
The UART interface available on AURA is based on i.MX93 SoC. The chip includes eight instances of UART Modules:
* LPUART1 and LPUART2 are in ''Low Power Real Time Domain''
* LPUART[3..8] are in ''Application Flex Domain''
=== Description ===
The UART port supports the following standards and features:
* Full-duplex, standard NRZ format
* Programmable baud rates (13-bit modulo divider) with a configurable oversampling ratio
* Asynchronous operations of transmit and receive baud rates with respect to the bus clock
* Interrupt, DMA, or polled operations
* Hardware parity generation and checking
* Programmable 7-bit, 8-bit, 9-bit, or 10-bit character length
* Programmable 1-bit or 2-bit stop bits
* Hardware flow control support for request to send (RTS) and clear to send (CTS) signals
* Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with a programmable pulse width
===Pin mapping===
The Pin mapping is described in the [[AURA SOM/AURA Hardware/Pinout_Table | Pinout table section]]
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[[Category:AURA]]
{| style="border-collapse:collapse; "
!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History
|-
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes
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|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|2023/09/13
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|First release
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<section end=History/>
__FORCETOC__
<section begin=Body/>
==Peripheral UART ==
LPUART provides asynchronous, serial communication capabilities with external devices. LPUART can continue operating when the processor is in Low-Power mode, if an appropriate peripheral clock is available.
The UART interface available on AURA is based on i.MX93 SoC. The chip includes eight instances of UART Modules:
* LPUART1 and LPUART2 are in ''Low Power Real Time Domain''
* LPUART[3..8] are in ''Application Flex Domain''
=== Description ===
The UART port supports the following standards and features:
* Full-duplex, standard NRZ format
* Programmable baud rates (13-bit modulo divider) with a configurable oversampling ratio
* Asynchronous operations of transmit and receive baud rates with respect to the bus clock
* Interrupt, DMA, or polled operations
* Hardware parity generation and checking
* Programmable 7-bit, 8-bit, 9-bit, or 10-bit character length
* Programmable 1-bit or 2-bit stop bits
* Hardware flow control support for request to send (RTS) and clear to send (CTS) signals
* Selectable IrDA 1.4 return-to-zero-inverted (RZI) format with a programmable pulse width
===Pin mapping===
The Pin mapping is described in the [[AURA SOM/AURA Hardware/Pinout_Table | Pinout table section]]
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[[Category:AURA]]