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==Peripheral SPI ==
A SPI bus is a synchronous serial communication interface used in embedded systems. It is typically used to perform short-distance communications between microcontrollers and peripheral devices. The SPI interface available on AURA is based on i.MX93 SoC. The chip includes eight instances of LPSPI Modules:* LPSPI1 and LPSPI2 are in ''TBD: sostituire le sezioni con le informazioni sull'uso della perifericaLow Power Real Time Domain''* LPSPI[3..8] are in ''Nell'esempio di seguito c'è la descrizione dell'interfaccia HDMIApplication Flex Domain''* SPI1 and SPI2 are only supported in Master Mode, not Slave Mode.
=== Description ===
The SPI port supports the following standards and features:
* HighFIFO register access supported by DMA transmit and receive requests* Continues operating in Stop mode, if configured to do so and an appropriate clock is available* 32-Definition Multimedia Interface Specification, Version 1.4a bit word size* Configurable clock polarity and phase* Master mode—supports 2 peripheral chip selects and Slave mode* Support for up to 1080p at 60Hz HDTV display resolutions 8-word transmit, receive and up to QXGA graphic display resolutions. command FIFO* Support for 4k x 2k Flexible timing parameters in Master mode, including SCK frequency and duty cycle, and delays between PCS and 3D video formats SCK edges* Support for up Continuous transfer option to 16keep PCS asserted across multiple frames* Full-duplex transfers support 1-bit Deep Color modestransmit and receive on each clock edge and Half-duplex transfers support
===Pin mapping===