Bureaucrats, dave_user, Administrators
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Created page with "<section begin=History/> {| style="border-collapse:collapse; " !colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History |- !style="border-le..."
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{| style="border-collapse:collapse; "
!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History
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!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes
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|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|2023/09/13
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|First release
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==Peripheral I3C ==
The MIPI Alliance Improved Inter-Integrated Circuit (MIPI I3C) improves upon the use and power of I2C, and provides an alternative to SPI for mid-speed applications.
The I3C interface available on AURA is based on i.MX93 SoC. The chip includes two instances of I3C Modules:
* I3C1 is in ''Low Power Real Time Domain''
* I3C2 is in ''Application Flex Domain''
=== Description ===
The I3C bus protocol supports:
* all required and most optional features of the MIPI Alliance Specification for I3C, v1.0 and v1.1, except for ternary data rates (HDR-TSP and HDR-TSL)
* In-band interrupts (IBI)
* Common Command Codes (CCC)
* Dynamic addressing
* Multi-controller/multi-drop
* Hot-Join (HJ)
* I2C compatibility
===Pin mapping===
The Pin mapping is described in the [[AURA SOM/AURA Hardware/Pinout_Table | Pinout table section]]
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[[Category:AURA]]
{| style="border-collapse:collapse; "
!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History
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!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes
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|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|2023/09/13
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|First release
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<section begin=Body/>
==Peripheral I3C ==
The MIPI Alliance Improved Inter-Integrated Circuit (MIPI I3C) improves upon the use and power of I2C, and provides an alternative to SPI for mid-speed applications.
The I3C interface available on AURA is based on i.MX93 SoC. The chip includes two instances of I3C Modules:
* I3C1 is in ''Low Power Real Time Domain''
* I3C2 is in ''Application Flex Domain''
=== Description ===
The I3C bus protocol supports:
* all required and most optional features of the MIPI Alliance Specification for I3C, v1.0 and v1.1, except for ternary data rates (HDR-TSP and HDR-TSL)
* In-band interrupts (IBI)
* Common Command Codes (CCC)
* Dynamic addressing
* Multi-controller/multi-drop
* Hot-Join (HJ)
* I2C compatibility
===Pin mapping===
The Pin mapping is described in the [[AURA SOM/AURA Hardware/Pinout_Table | Pinout table section]]
----
[[Category:AURA]]