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AURA SOM/AURA Hardware/Pinout Table

< AURA SOM‎ | AURA Hardware
Revision as of 16:49, 18 May 2023 by U0007 (talk | contribs)

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History
ID# Issue Date Notes

17891

15/05/2023 Preliminary version


Contents

Connectors and Pinout TableEdit

 

Connectors descriptionEdit

In the following table are described all available connectors integrated on AURA SOM:

Connector name Connector Type Notes Carrier board counterpart
J1 SODIMM DDR3 edge connector 204 pin TE Connectivity 2013289-1

The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to AURA pinout specifications. See the images below for reference:

 
AURA TOP view
 
AURA BOTTOM view

Pinout table naming conventionsEdit

This chapter contains the pinout description of the AURA module, grouped in two tables (odd and even pins) that report the pin mapping of the 204-pin SO-DIMM AURA connector.

Each row in the pinout tables contains the following information:

Pin Reference to the connector pin
Pin Name Pin (signal) name on the AURA connectors
Internal
connections 		Connections to the AURA components
  • CPU.<x> : pin connected to CPU pad named <x>
  • CAN.<x> : pin connected to the CAN transceiver (TI SN65HVD232)
  • PMIC.<x> : pin connected to the Power Manager IC (NXP PCA9451A)
  • LAN.<x> : pin connected to the LAN PHY (Microchip LAN8830T-V)
Ball/pin # Component ball/pin number connected to signal
Voltage I/O voltage levels
Type Pin type:
  • I = Input
  • O = Output
  • D = Differential
  • Z = High impedance
  • S = Power supply voltage
  • G = Ground
  • A = Analog signal
Notes Remarks on special pin characteristics
Pin MUX alternative functions Muxes:
  • Pin ALT-0
  • ...
  • Pin ALT-N

The number of functions depends on platform

Voltage domainsEdit

Voltage domain Nominal voltage [V] Notes
3.3VIN 3.3 See Operational_characteristics of the SoM wiki page
NVCC_3V3 3.3 Voltage generated by the internal PSU. See Power Supply Unit (PSU) wiki page
VDD_ANA_1V8 1.8

Pinout Table ODD pins declarationEdit

Pin Pin Name Internal Connections Ball/pin # Voltage

domain

Type Notes Alternative Functions
J1.1 DGND DGND - - G
J1.3 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.5 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.7 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.9 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.11 DGND DGND - - G
J1.13 ETH1_LED1 LAN.LED1/GPIO0 18 NVCC_3V3 O
J1.15 ETH1_LED2 LAN.LED2/GPIO1 16 NVCC_3V3 O
J1.17 DGND DGND - - G
J1.19 ETH1_TXRX0_P LAN.TXRXP_A 2 NVCC_3V3 D
J1.21 ETH1_TXRX0_M LAN.TXRXM_A 3 NVCC_3V3 D
J1.23 ETH1_TXRX1_P LAN.TXRXP_B 5 NVCC_3V3 D
J1.25 ETH1_TXRX1_M LAN.TXRXM_B 6 NVCC_3V3 D
J1.27 ETH1_TXRX2_P LAN.TXRXP_C 7 NVCC_3V3 D
J1.29 ETH1_TXRX2_M LAN.TXRXM_C 8 NVCC_3V3 D
J1.31 ETH1_TXRX3_P LAN.TXRXP_D 10 NVCC_3V3 D
J1.33 ETH1_TXRX3_M LAN.TXRXM_D 11 NVCC_3V3 D
J1.35 DGND DGND - - G
J1.37 ETH1_LED3 LAN.LED3/GPIO2 15 NVCC_3V3 O
J1.39 ETH1_LED4 LAN.LED4/GPIO3 14 NVCC_3V3 O
J1.41 ETH_OSC_EN 46 NVCC_3V3 I mounting option
J1.43 GPIO_IO06 CPU.GPIO_IO06 L20 NVCC_3V3 IO Pin ALT-0 GPIO2_IO06
Pin ALT-1 TMP5.CH0
Pin ALT-2 PDM.BIT_STREAM[1]
Pin ALT-3 LCDIF.D[2]
Pin ALT-4 SPI7.SOUT
Pin ALT-5 UART6.CTS_B
Pin ALT-6 I2C7.SDA
Pin ALT-7 FLEXIO1.FLEXIO[6]
J1.45 GPIO_IO18 CPU.GPIO_IO18 R18 NVCC_3V3 IO Pin ALT-0 GPIO2_IO18
Pin ALT-1 SAI3.RX_BCLK
Pin ALT-2 ISI.D[9]
Pin ALT-3 LCDIF.D[14]
Pin ALT-4 SPI5.PCS0
Pin ALT-5 SPI4.PCS0
Pin ALT-6 TMP5.CH2
Pin ALT-7 FLEXIO1.FLEXIO[18]
J1.47 GPIO_IO09 CPU.GPIO_IO09 M21 NVCC_3V3 IO Pin ALT-0 GPIO2_IO09
Pin ALT-1 SPI3.SIN
Pin ALT-2 ISI.D[3]
Pin ALT-3 LCDIF.D[5]
Pin ALT-4 TMP3.EXTCLK
Pin ALT-5 UART7.RX
Pin ALT-6 I2C7.SCL
Pin ALT-7 FLEXIO1.FLEXIO[9]
J1.49 GPIO_IO08 CPU.GPIO_IO08 M20 NVCC_3V3 IO Pin ALT-0 GPIO2_IO08
Pin ALT-1 SPI3.SPCS0
Pin ALT-2 ISI.D[2]
Pin ALT-3 LCDIF.D[4]
Pin ALT-4 TMP6.CH0
Pin ALT-5 UART7.TX
Pin ALT-6 I2C7.SDA
Pin ALT-7 FLEXIO1.FLEXIO[8]
J1.51
J1.53 SAI1_TXFS CPU.SAI1_TXFS//BOOT2 G21 NVCC_AON IO Pin ALT-0 SAI1.TX_SYNC
Pin ALT-1 SAI1.TX_DATA[1]
Pin ALT-2 SPI1.PCS0
Pin ALT-3 UART2_DTR_B
Pin ALT-4 MQS1.LEFT
Pin ALT-5 GPIO1_IO11//BOOT_MODE[2]
J1.55 GPIO_IO10 CPU.GPIO_IO10 N17 NVCC_3V3 IO Pin ALT-0 GPIO2_IO10
Pin ALT-1 SPI3.SOUT
Pin ALT-2 ISI.D[4]
Pin ALT-3 LCDIF.D[6]
Pin ALT-4 TMP4.EXTCLK
Pin ALT-5 UART7.CTS_B
Pin ALT-6 I2C8.SDA
Pin ALT-7 FLEXIO1.FLEXIO[10]
J1.57 DGND DGND - - G
J1.59 GPIO_IO11 CPU.GPIO_IO11 N18 NVCC_3V3 IO Pin ALT-0 GPIO2_IO10
Pin ALT-1 SPI3.SCLK
Pin ALT-2 ISI.D[5]
Pin ALT-3 LCDIF.D[7]
Pin ALT-4 TMP5.EXTCLK
Pin ALT-5 UART7.RTS_B
Pin ALT-6 I2C8.SCL
Pin ALT-7 FLEXIO1.FLEXIO[11]
J1.61 SD3_DATA0 CPU.GPIO_IO11 T16 NVCC_3V3 IO Optionally connected to internal Flex SPI (NOR or NAND option) Pin ALT-0 USDHC3.DATA0
Pin ALT-1 FLEX_SPI.A_DATA[0]
Pin ALT-4 FLEXIO1.FLEXIO[22]
Pin ALT-5 GPIO3_IO22
J1.63 SD3_DATA1 CPU.GPIO_IO11 V14 NVCC_3V3 IO Optionally connected to internal Flex SPI (NOR or NAND option) Pin ALT-0 USDHC3.DATA1
Pin ALT-1 FLEX_SPI.A_DATA[1]
Pin ALT-4 FLEXIO1.FLEXIO[23]
Pin ALT-5 GPIO3_IO23
J1.65 SD3_DATA2 CPU.GPIO_IO12 U14 NVCC_3V3 IO Optionally connected to internal Flex SPI (NOR or NAND option) Pin ALT-0 USDHC3.DATA2
Pin ALT-1 FLEX_SPI.A_DATA[2]
Pin ALT-4 FLEXIO1.FLEXIO[24]
Pin ALT-5 GPIO3_IO24
J1.67 SD3_DATA3 CPU.GPIO_IO13 T14 NVCC_3V3 IO Optionally connected to internal Flex SPI (NOR or NAND option) Pin ALT-0 USDHC3.DATA3
Pin ALT-1 FLEX_SPI.A_DATA[3]
Pin ALT-4 FLEXIO1.FLEXIO[25]
Pin ALT-5 GPIO3_IO25
J1.69 SD3_CMD CPU.GPIO_IO21 U16 NVCC_3V3 IO Optionally connected to internal Flex SPI (NOR or NAND option) Pin ALT-0 USDHC3.CMD
Pin ALT-1 FLEX_SPI.A_SS0_B
Pin ALT-4 FLEXIO1.FLEXIO[21]
Pin ALT-5 GPIO3_IO21
J1.71 SD3_CLK CPU.GPIO_IO20 V16 NVCC_3V3 IO Optionally connected to internal Flex SPI (NOR or NAND option) Pin ALT-0 USDHC3.CLK
Pin ALT-1 FLEX_SPI.A_SCLK
Pin ALT-4 FLEXIO1.FLEXIO[20]
Pin ALT-5 GPIO3_IO20
J1.73 DGND DGND - - G
J1.75 SD2_DATA0 CPU.SD2_DATA0 Y18 NVCC_3V3 IO Pin ALT-0 USDHC2.DATA0
Pin ALT-1 ENET2.1588_EVENT0_OUT
Pin ALT-2 CAN2.TX
Pin ALT-4 FLEXIO1.FLEXIO[3]
Pin ALT-5 GPIO3_IO03
J1.77 SD2_DATA1 CPU.SD2_DATA1 AA18 NVCC_3V3 IO Pin ALT-0 USDHC2.DATA1
Pin ALT-1 ENET2.1588_EVENT1_IN
Pin ALT-2 CAN2.RX
Pin ALT-4 FLEXIO1.FLEXIO[4]
Pin ALT-5 GPIO3_IO04
J1.79 SD2_DATA2 CPU.SD2_DATA2 Y20 NVCC_3V3 IO Pin ALT-0 USDHC2.DATA2
Pin ALT-1 ENET2.1588_EVENT1_OUT
Pin ALT-2 MQS1.RIGHT
Pin ALT-4 FLEXIO1.FLEXIO[5]
Pin ALT-5 GPIO3_IO05
J1.81 SD2_DATA3 CPU.SD2_DATA3 AA20 NVCC_3V3 IO Pin ALT-0 USDHC2.DATA3
Pin ALT-1 LPTMR2.ALT1
Pin ALT-2 MQS1.LEFT
Pin ALT-4 FLEXIO1.FLEXIO[6]
Pin ALT-5 GPIO3_IO06
J1.83 SD2_CMD CPU.SD2_CMD Y19 NVCC_3V3 IO Pin ALT-0 USDHC2.CMD
Pin ALT-1 ENET2.1588_EVENT0_IN
Pin ALT-2 I3C2.PUR
Pin ALT-3 I3C2.PUR_B
Pin ALT-4 FLEXIO1.FLEXIO[2]
Pin ALT-5 GPIO3_IO02
J1.85 SD2_CLK CPU.SD2_CLK AA19 NVCC_3V3 IO Pin ALT-0 USDHC2.CLK
Pin ALT-1 ENET_QOS.1588_EVENT0_OUT
Pin ALT-2 I3C2.SDA
Pin ALT-4 FLEXIO1.FLEXIO[1]
Pin ALT-5 GPIO3_IO01
J1.87 DGND DGND - - G
J1.89 GPIO_IO14 CPU.GPIO_IO14 P20 NVCC_3V3 IO Pin ALT-0 GPIO2_IO14
Pin ALT-1 UART3.TX
Pin ALT-2 ISI.D[6]
Pin ALT-3 LCDIF.D[10]
Pin ALT-4 SPI8.SOUT
Pin ALT-5 UART8.CTS_B
Pin ALT-6 UART4.TX
Pin ALT-7 FLEXIO1.FLEXIO[14]
J1.91 GPIO_IO15 CPU.GPIO_IO15 P21 NVCC_3V3 IO Pin ALT-0 GPIO2_IO15
Pin ALT-1 UART3.RX
Pin ALT-2 ISI.D[7]
Pin ALT-3 LCDIF.D[11]
Pin ALT-4 SPI8.SCK
Pin ALT-5 UART8.RTS_B
Pin ALT-6 UART4.RX
Pin ALT-7 FLEXIO1.FLEXIO[15]
J1.93 UART2_TXD CPU.UART2_TXD//BOOT1 F21 NVCC_3V3 IO Used as default console for Cortex-M33 Pin ALT-0 UART2_TX
Pin ALT-1 UART1.RTS_B
Pin ALT-2 SPI2.SCK
Pin ALT-3 TMP1.CH3
Pin ALT-5 GPIO1_IO07//BOOT_MODE[1]
J1.95 UART2_RXD CPU.UART2_RXD F20 NVCC_3V3 IO Used as default console for Cortex-M33 Pin ALT-0 UART2_RX
Pin ALT-1 UART1.CTS_B
Pin ALT-2 SPI2.SOUT
Pin ALT-3 TMP1.CH2
Pin ALT-4 SAI1.MCLK
Pin ALT-5 GPIO1_IO06
J1.97 SD2_VSELECT CPU.SD2_VSELECT V18 NVCC_3V3 IO Pin ALT-0 USDHC2.VSELECT
Pin ALT-1 USHDC2.WP
Pin ALT-2 LPTMR2.ALT3
Pin ALT-4 FLEXIO1.FLEXIO[19]
Pin ALT-5 GPIO3_IO19
J1.99 SD2_RESET_B CPU.SD2_RESET_B AA17 NVCC_3V3 IO Pin ALT-0 USDHC2.RESET_B
Pin ALT-1 LPTMR2.ALT2
Pin ALT-4 FLEXIO1.FLEXIO[7]
Pin ALT-5 GPIO3_IO07
J1.101 I2C1_SCL CPU.I2C1_SCL C20 NVCC_3V3 IO Pin ALT-0 I2C1.SCL
Pin ALT-1 I3C1.SCL
Pin ALT-2 UART1.DCB_B
Pin ALT-3 TMP2.CH0
Pin ALT-5 GPIO1_IO00
J1.103 I2C1_SDA CPU.I2C1_SDA C21 NVCC_3V3 IO Pin ALT-0 I2C1.SDA
Pin ALT-1 I3C1.SDA
Pin ALT-2 UART1.RIN_B
Pin ALT-3 TMP2.CH1
Pin ALT-5 GPIO1_IO01
J1.105 SAI1_TXD0 CPU.SAI1_TXD0//BOOT3 H21 NVCC_3V3 IO Pin ALT-0 SAI1.TX_DATA[0]
Pin ALT-1 UART2.RTS_B
Pin ALT-2 SPI1.SCK
Pin ALT-3 UART1.DTR_B
Pin ALT-4 CAN1.TX
Pin ALT-5 GPIO1_IO13//BOOT_MODE[3]
J1.107 SAI1_TXC CPU.SAI1_TXC G20 NVCC_3V3 IO Pin ALT-0 SAI1.TX_BCLK
Pin ALT-1 UART2.CTS_B
Pin ALT-2 SPI1.SIN
Pin ALT-3 UART1.DSR_B
Pin ALT-4 CAN1.RX
Pin ALT-5 GPIO1_IO12
J1.109 DGND DGND - - G
J1.111 ADC_IN0 CPU.ADC_IN0 B19 NVCC_3V3 IO Pin ALT-0 ANAMIX.ADC_IN0
J1.113 ADC_IN1 CPU.ADC_IN1 A20 NVCC_3V3 IO Pin ALT-0 ANAMIX.ADC_IN1
J1.115 ADC_IN2 CPU.ADC_IN2 B20 NVCC_3V3 IO Pin ALT-0 ANAMIX.ADC_IN2
J1.117 ADC_IN3 CPU.ADC_IN3 B21 NVCC_3V3 IO Pin ALT-0 ANAMIX.ADC_IN3
J1.119 PMIC_SCLH PMIC.SCLH 25 -
J1.121 PMIC_SDAH PMIC.SDAH 24 -
J1.123 PMIC_SCLL PMIC.SCLL 27 -
J1.125 PMIC_SDAL PMIC.SDAL 26 -
J1.127 I2C2_SDA CPU.I2C2_SDA
PMIC.SDA 		D21
42 		NVCC_3V3 IO Pin ALT-0 I2C2.SDA
Pin ALT-3 UART2.RIN_B
Pin ALT-4 TMP2.CH3
Pin ALT-5 SAI1.RX_BCLK
Pin ALT-5 GPIO1_IO03
J1.129 I2C2_SCL CPU.I2C2_SCL
PMIC.SCL 		D20
41 		NVCC_3V3 IO Pin ALT-0 I2C2.SCL
Pin ALT-1 I3C1.PUR
Pin ALT-3 UART2.DCB_B
Pin ALT-4 TMP2.CH2
Pin ALT-5 SAI1.RX_SYNC
Pin ALT-5 GPIO1_IO02
Pin ALT-6 I3C1.PUR_B
J1.131 DGND DGND - - G
J1.133 LVDS_CLK_N CPU.LVDS_CLK_N A3 VDD_ANA_1V8 D
J1.135 LVDS_CLK_P CPU.LVDS_CLK_P B3 VDD_ANA_1V8 D
J1.137 LVDS_TX0_N CPU.LVDS_TX0_N A5 VDD_ANA_1V8 D
J1.139 LVDS_TX0_P CPU.LVDS_TX0_P B5 VDD_ANA_1V8 D
J1.141 LVDS_TX1_N CPU.LVDS_TX1_N A4 VDD_ANA_1V8 D
J1.143 LVDS_TX1_P CPU.LVDS_TX1_P B4 VDD_ANA_1V8 D
J1.145 LVDS_TX2_N CPU.LVDS_TX2_N A2 VDD_ANA_1V8 D
J1.147 LVDS_TX2_P CPU.LVDS_TX2_P B2 VDD_ANA_1V8 D
J1.149 LVDS_TX3_N CPU.LVDS_TX3_N B1 VDD_ANA_1V8 D
J1.151 LVDS_TX3_P CPU.LVDS_TX3_P C1 VDD_ANA_1V8 D
J1.153 DGND DGND - - G
J1.155 DSI_CLK_N CPU.DSI_CLK_N D6 VDD_ANA_1V8 D
J1.157 DSI_CLK_P CPU.DSI_CLK_P E6 VDD_ANA_1V8 D
J1.159 DSI_TX0_N CPU.DSI_TX0_N A6 VDD_ANA_1V8 D
J1.161 DSI_TX0_P CPU.DSI_TX0_P B6 VDD_ANA_1V8 D
J1.163 DSI_TX1_N CPU.DSI_TX1_N A7 VDD_ANA_1V8 D
J1.165 DSI_TX1_P CPU.DSI_TX1_P B7 VDD_ANA_1V8 D
J1.167 DSI_TX2_N CPU.DSI_TX2_N A8 VDD_ANA_1V8 D
J1.169 DSI_TX2_P CPU.DSI_TX2_P B8 VDD_ANA_1V8 D
J1.171 DSI_TX3_N CPU.DSI_TX3_N A9 VDD_ANA_1V8 D
J1.173 DSI_TX3_P CPU.DSI_TX3_P B9 VDD_ANA_1V8 D
J1.175 DGND DGND - - G
J1.177 SD2_CD_B CPU.GPIO_IO08 M20 NVCC_3V3 IO Pin ALT-0 USDHC2.CD_B
Pin ALT-1 ENET_QOS.1588_EVENT0_IN
Pin ALT-2 I2C3.SCL
Pin ALT-4 FLEXIO1.FLEXIO[0]
Pin ALT-5 GPIO3_IO00
J1.179 GPIO_IO00 CPU.GPIO_IO00 J21 NVCC_3V3 IO Pin ALT-0 GPIO2_IO00
Pin ALT-1 I2C3.SDA
Pin ALT-2 ISI.PCLK
Pin ALT-3 LCDIF.PCLK
Pin ALT-4 SPI6.PCS0
Pin ALT-5 UART5.TX
Pin ALT-6 I2C5.SDA
Pin ALT-7 FLEXIO1.FLEXIO[0]
J1.181 GPIO_IO03 CPU.GPIO_IO03 K21 NVCC_3V3 IO Pin ALT-0 GPIO2_IO03
Pin ALT-1 I2C4.SCL
Pin ALT-2 ISI.LINE_VALID
Pin ALT-3 LCDIF.HSYNC
Pin ALT-4 SPI6.SCK
Pin ALT-5 UART5.RTS_B
Pin ALT-6 I2C6.SCL
Pin ALT-7 FLEXIO1.FLEXIO[3]
J1.183 GPIO_IO01 CPU.GPIO_IO01 K21 NVCC_3V3 IO Pin ALT-0 GPIO2_IO01
Pin ALT-1 I2C3.SCL
Pin ALT-2 ISI.D[0]
Pin ALT-3 LCDIF.DE
Pin ALT-4 SPI6.SIN
Pin ALT-5 UART5.RX
Pin ALT-6 I2C5.SCL
Pin ALT-7 FLEXIO1.FLEXIO[1]
J1.185 - - - -
J1.187 UART1_TXD CPU.UART1_TXD//BOOT0 E21 NVCC_3V3 IO Used as default Linux console (Cortex-A55) Pin ALT-0 UART1_TX
Pin ALT-1 SECO.TX
Pin ALT-2 SPI2.PCS0
Pin ALT-3 TPM1.CH1
Pin ALT-5 GPIO1_IO05//BOOT_MODE[0]
J1.189 UART1_RXD CPU.UART1_RXD E20 NVCC_3V3 IO Used as default Linux console (Cortex-A55) Pin ALT-0 UART1_RX
Pin ALT-1 SECO.RX
Pin ALT-2 SPI2.SIN
Pin ALT-3 TPM1.CH0
Pin ALT-5 GPIO1_IO04
J1.191 GPIO_IO12 CPU.GPIO_IO12 N20 NVCC_3V3 IO Pin ALT-0 GPIO2_IO12
Pin ALT-1 TPM3.CH2
Pin ALT-2 PDM.BIT_STREAM[2]
Pin ALT-3 LCDIF.D[8]
Pin ALT-4 SPI8.PCS0
Pin ALT-5 UART8.TX
Pin ALT-6 I2C8.SDA
Pin ALT-7 SAI3.RX_SYNC
J1.193 GPIO_IO13 CPU.GPIO_IO13 N21 NVCC_3V3 IO Pin ALT-0 GPIO2_IO13
Pin ALT-1 TPM4.CH2
Pin ALT-2 PDM.BIT_STREAM[3]
Pin ALT-3 LCDIF.D[9]
Pin ALT-4 SPI8.SIN
Pin ALT-5 UART8.RX
Pin ALT-6 I2C8.SCL
Pin ALT-7 FLEXIO1.FLEXIO[13]
J1.195 GPIO_IO02 CPU.GPIO_IO02 K21 NVCC_3V3 IO Pin ALT-0 GPIO2_IO13
Pin ALT-1 I2C4.SDA
Pin ALT-2 ISI.FRAME_VALID
Pin ALT-3 LCDIF.VSYNC
Pin ALT-4 SPI6.SOUT
Pin ALT-5 UART5.CTS_B
Pin ALT-6 I2C6.SDA
Pin ALT-7 FLEXIO1.FLEXIO[2]
J1.197 - - - -
J1.199 PDM_BIT_STREAM0 CPU.PDM_BIT_STREAM0 J17 NVCC_3V3 IO Pin ALT-0 PDM.BIT_STREAM[0]
Pin ALT-1 MQS1.RIGHT
Pin ALT-2 SPI1.PCS1
Pin ALT-3 TPM1.EXTCLK
Pin ALT-4 LPTMR1.ALT2
Pin ALT-5 GPIO1.IO09
Pin ALT-6 CAN1.RX
J1.201 PDM_CLK CPU.PDM_CLK G17 NVCC_3V3 IO Pin ALT-0 PDM_CLK
Pin ALT-1 MQS1.LEFT
Pin ALT-4 LPTMR1.ALT1
Pin ALT-5 GPIO1.IO08
Pin ALT-6 CAN1.TX
J1.203 DGND DGND - - G

Pinout Table EVEN pins declarationEdit

Pin Pin Name Internal Connections Ball/pin # Voltage

domain

Type Notes Alternative Functions
J1.2 DGND DGND - - G
J1.4 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.6 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.8 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.10 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.12 DGND DGND - - G
J1.14 SYS_NRST PMIC.PMIC_RST_B 8 I
J1.16 CPU_ON_OFF CPU.ON_OFF A19 NVCC_3V3 I
J1.18 SOM_PGOOD - - NVCC_3V3 O
J1.20 BOOT_MODE_SEL BOOT MODE SELECTION - NVCC_3V3 I internal pull-up to NVCC_3V3
J1.22 CPU_PORn CPU.POR_B

PMIC.POR_B

A16

9

NVCC_BBSM_1V8 I/O internal pull-up 100k to NVCC_BBSM_1V8
J1.24 PMIC_ON_REQ PMIC.PMIC_ON_REQ 39 NVCC_BBSM_1V8 I internal pull-up 100k to NVCC_BBSM_1V8
J1.26 PDM_BIT_STREAM1 CPU.PDM_BIT_STREAM1 JG18 NVCC_3V3 IO Pin ALT-0 PDM.BIT_STREAM[1]
Pin ALT-1 M33.NMI
Pin ALT-2 SPI2.PCS1
Pin ALT-3 TPM2.EXTCLK
Pin ALT-4 LPTMR1.ALT3
Pin ALT-5 GPIO1.IO10
J1.28 WDOG_ANY CPU.PDM_BIT_STREAM1 JG18 NVCC_3V3 IO Pin ALT-0 WDOG1.WDOG_ANY
Pin ALT-5 GPIO1.IO15
J1.30 DGND DGND - - G
J1.32 PMIC_STBY_REQ PMIC.PMIC_STBY_REQ 40 NVCC_BBSM_1V8 O
J1.34 GPIO_IO17 CPU.GPIO_IO17 R20 NVCC_3V3 IO Pin ALT-0 GPIO2_IO17
Pin ALT-1 SAI3.MCLK
Pin ALT-2 ISI.D[8]
Pin ALT-3 LCDIF.D[13]
Pin ALT-4 UART3.RTS_B
Pin ALT-5 SPI4.PCS1
Pin ALT-6 UART4.RTS_B
Pin ALT-7 FLEXIO1.FLEXIO[17]
J1.36 GPIO_IO21 CPU.GPIO_IO21 T21 NVCC_3V3 IO Pin ALT-0 GPIO2_IO21
Pin ALT-1 SAI3.TX_DATA[0]
Pin ALT-2 PDM.CLK
Pin ALT-3 LCDIF.D[17]
Pin ALT-4 SPI5.SCK
Pin ALT-5 SPI4.SCK
Pin ALT-6 TMP4.CH1
Pin ALT-7 SAI3.RX_BCLK
J1.38 GPIO_IO29 CPU.GPIO_IO29 Y21 NVCC_3V3 IO Pin ALT-0 GPIO2_IO29
Pin ALT-1 I2C3.SCL
Pin ALT-7 FLEXIO1.FLEXIO[29]
J1.40 GPIO_IO07 CPU.GPIO_IO07 L21 NVCC_3V3 IO Pin ALT-0 GPIO2_IO07
Pin ALT-1 SPI3.PCS1
Pin ALT-2 ISI.D[1]
Pin ALT-3 LCDIF.D[3]
Pin ALT-4 SPI7.SCK
Pin ALT-5 UART6.RTS_B
Pin ALT-6 I2C7.SCL
Pin ALT-7 FLEXIO1.FLEXIO[7]
J1.42 GPIO_IO25//CAN_H CPU.GPIO_IO25

CAN.CANH

V21

7

NVCC_3V3 IO optional CAN transceiver Pin ALT-0 GPIO2_IO25
Pin ALT-1 USDHC3.DATA1
Pin ALT-2 CAN2.TX
Pin ALT-3 LCDIF.D[21]
Pin ALT-4 TMP4.CH3
Pin ALT-5 DAP.TCLK_SWCLK
Pin ALT-6 SPI7.PCS1
Pin ALT-7 FLEXIO1.FLEXIO[25]
J1.44 GPIO_IO27//CAN_L CPU.GPIO_IO27

CAN.CANL

W21

6

NVCC_3V3 IO optional CAN transceiver Pin ALT-0 GPIO2_IO27
Pin ALT-1 USDHC3.DATA3
Pin ALT-2 CAN2.RX
Pin ALT-3 LCDIF.D[23]
Pin ALT-4 TMP6.CH3
Pin ALT-5 DAP.TMS_SWDIO
Pin ALT-6 SPI5.PCS1
Pin ALT-7 FLEXIO1.FLEXIO[27]
J1.46 GPIO_IO24 CPU.GPIO_IO24 U21 NVCC_3V3 IO Pin ALT-0 GPIO2_IO24
Pin ALT-1 USDHC3.DATA0
Pin ALT-3 LCDIF.D[20]
Pin ALT-4 TMP3.CH3
Pin ALT-5 DAP.TDO_TRACESWO
Pin ALT-6 SPI6.PSC1
Pin ALT-7 FLEXIO1.FLEXIO[24]
J1.48 GPIO_IO28 CPU.GPIO_IO28 W20 NVCC_3V3 IO Pin ALT-0 GPIO2_IO28
Pin ALT-1 I2C3.SDA
Pin ALT-7 FLEXIO1.FLEXIO[28]
J1.50 CCM_CLK01 CPU.CCM_CLK01 AA2 NVCC_3V3 IO Pin ALT-0 CCMSRCGPCMIX.CLK01
Pin ALT-4 FLEXIO1.FLEXIO[26]
Pin ALT-5 GPIO3_IO26
J1.52 CCM_CLK02 CPU.CCM_CLK02 Y3 NVCC_3V3 IO Pin ALT-0 CCMSRCGPCMIX.CLK02
Pin ALT-4 FLEXIO1.FLEXIO[27]
Pin ALT-5 GPIO3_IO27
J1.54 CCM_CLK03 CPU.CCM_CLK03 U4 NVCC_3V3 IO Pin ALT-0 CCMSRCGPCMIX.CLK01
Pin ALT-4 FLEXIO2.FLEXIO[28]
Pin ALT-5 GPIO4_IO28
J1.56 DGND DGND - - G
J1.58 ETH_RSTn LAN.RESETn 43 NVCC_3V3 I Hardware mounting option
J1.60 ETH_INTn LAN.INT_N 39 NVCC_3V3 O Hardware mounting option
J1.62 SAI1_RXD0 CPU.SAI1_RXD0 H20 NVCC_3V3 IO Pin ALT-0 SAI1.RX_DATA[0]
Pin ALT-1 SAI1.MCLK
Pin ALT-2 SPI1.SOUT
Pin ALT-3 UART2.DSR_B
Pin ALT-4 MQS1.RIGHT
Pin ALT-5 GPIO1.IO14
J1.64 CCM_CLK04 CPU.CCM_CLK04 V4 NVCC_3V3 IO Pin ALT-0 CCMSRCGPCMIX.CLK04
Pin ALT-4 FLEXIO2.FLEXIO[29]
Pin ALT-5 GPIO4_IO29
J1.66 GPIO_IO16 CPU.GPIO_IO16 R21 NVCC_3V3 IO Pin ALT-0 GPIO2_IO16
Pin ALT-1 SAI3.TX_BCLK
Pin ALT-2 PDM.BIT_STREAM[2]
Pin ALT-3 LCDIF.D[12]
Pin ALT-4 UART3.CTS_B
Pin ALT-5 SPI4.PCS2
Pin ALT-6 UART4.CTS_B
Pin ALT-7 FLEXIO1.FLEXIO[16]
J1.68 GPIO_IO19 CPU.GPIO_IO19 R17 NVCC_3V3 IO Pin ALT-0 GPIO2_IO19
Pin ALT-1 SAI3.RX_SYNC
Pin ALT-2 PDM.BIT_STREAM[3]
Pin ALT-3 LCDIF.D[15]
Pin ALT-4 SPI5.SIN
Pin ALT-5 SPI4.SIN
Pin ALT-6 TMP4.CH2
Pin ALT-7 SAI3.TX_DATA[0]
J1.70 GPIO_IO26 CPU.GPIO_IO26 V20 NVCC_3V3 IO Pin ALT-0 GPIO2_IO26
Pin ALT-1 USDHC3.DATA2
Pin ALT-2 PDM.BIT_STREAM[1]
Pin ALT-3 LCDIF.D[22]
Pin ALT-4 TMP3.CH3
Pin ALT-5 DAP-TDI
Pin ALT-6 SPI8.PCS1
Pin ALT-7 SAI3.TX_SYNC
J1.72 GPIO_IO20 CPU.GPIO_IO20 T20 NVCC_3V3 IO Pin ALT-0 GPIO2_IO20
Pin ALT-1 SAI3.RX_DATA[0]
Pin ALT-2 PDM.BIT_STREAM[0]
Pin ALT-3 LCDIF.D[16]
Pin ALT-4 SPI5.SOUT
Pin ALT-5 SPI4.SOUT
Pin ALT-6 TMP3.CH1
Pin ALT-7 FLEXIO1.FLEXIO[20]
J1.74 GPIO_IO22 CPU.GPIO_IO22 U18 NVCC_3V3 IO Pin ALT-0 GPIO2_IO22
Pin ALT-1 USDHC3.CLK
Pin ALT-2 SPDIF1.IN
Pin ALT-3 LCDIF.D[18]
Pin ALT-4 TMP5.CH1
Pin ALT-5 TMP6.EXTCLK
Pin ALT-6 I2C5.SDA
Pin ALT-7 FLEXIO1.FLEXIO[22]
J1.76 GPIO_IO23 CPU.GPIO_IO23 U20 NVCC_3V3 IO Pin ALT-0 GPIO2_IO23
Pin ALT-1 USDHC3.CMD
Pin ALT-2 SPDIF1.OUT
Pin ALT-3 LCDIF.D[19]
Pin ALT-4 TMP6.CH1
Pin ALT-6 I2C5.SCL
Pin ALT-7 FLEXIO1.FLEXIO[23]
J1.78 GPIO_IO05 CPU.GPIO_IO05 L18 NVCC_3V3 IO Pin ALT-0 GPIO2_IO05
Pin ALT-1 TMP4.CH0
Pin ALT-2 PDM.BIT_STREAM[0]
Pin ALT-3 LCDIF.D[1]
Pin ALT-4 SPI7.SIN
Pin ALT-5 UART6.RX
Pin ALT-6 I2C6.SCL
Pin ALT-7 FLEXIO1.FLEXIO[5]
J1.80 GPIO_IO04 CPU.GPIO_IO04 L17 NVCC_3V3 IO Pin ALT-0 GPIO2_IO04
Pin ALT-1 TMP3.CH0
Pin ALT-2 PDM.CLK
Pin ALT-3 LCDIF.D[0]
Pin ALT-4 SPI7.PCS0
Pin ALT-5 UART6.TX
Pin ALT-6 I2C6.SDA
Pin ALT-7 FLEXIO1.FLEXIO[4]
J1.82 DGND DGND - - G
J1.84 TAMPER0 CPU.TAMPER0 B16 NVCC_3V3 I Pin ALT-0 BBSMMIX.TAMPER0
J1.86 TAMPER1 CPU.TAMPER1 F14 NVCC_3V3 I Pin ALT-0 BBSMMIX.TAMPER1
J1.88 CLKIN1 CPU.CLKIN1 B17 NVCC_3V3 I Pin ALT-0 ANAMIX.CLKIN1
Pin ALT-1 ANAMIX.ESD_DIODE
J1.90 CLKIN2 CPU.CLKIN2 A18 NVCC_3V3 I Pin ALT-0 ANAMIX.CLKIN2
Pin ALT-1 ANAMIX.ATX
J1.92 JTAG_TDI CPU.DAP_TDI W1 NVCC_3V3 IO Pin ALT-0 DAP.TDI
Pin ALT-1 MQS2.LEFT
Pin ALT-3 CAN2.TX
Pin ALT-4 FLEXIO2.FLEXIO[30]
Pin ALT-5 GPIO3.IO28
Pin ALT-6 UART5.RX
J1.94 JTAG_TMS CPU.DAP_TMS_SWDIO W2 NVCC_3V3 IO Pin ALT-0 DAP.TMS_SWDIO
Pin ALT-4 FLEXIO2.FLEXIO[31]
Pin ALT-5 GPIO3.IO29
Pin ALT-6 UART5.RTS_B
J1.96 JTAG_TMS CPU.DAP_TCLK_SWCLK Y1 NVCC_3V3 IO Pin ALT-0 DAP.TCLK_SWCLK
Pin ALT-4 FLEXIO1.FLEXIO[30]
Pin ALT-5 GPIO3.IO30
Pin ALT-6 UART5.CTS_B
J1.98 JTAG_TDO CPU.DAP_TDO_TRACE_SWO W1 NVCC_3V3 IO Pin ALT-0 DAP.TDO_TRACESWO
Pin ALT-1 MQS2.RIGHT
Pin ALT-3 CAN2.RX
Pin ALT-4 FLEXIO1.FLEXIO[31]
Pin ALT-5 GPIO3.IO31
Pin ALT-6 UART5.TX
J1.100 DGND DGND - - G
J1.102 CSI_CLK_N CPU.MIPI_CSI1_CLK_N D10 VDD_ANA_1V8 D
J1.104 CSI_CLK_P CPU.MIPI_CSI1_CLK_P E10 VDD_ANA_1V8 D
J1.106 CSI_D0_N CPU.MIPI_CSI1_D0_N A11 VDD_ANA_1V8 D
J1.108 CSI_D0_P CPU.MIPI_CSI1_D0_P B11 VDD_ANA_1V8 D
J1.110 CSI_D1_N CPU.MIPI_CSI1_D1_N A10 VDD_ANA_1V8 D
J1.112 CSI_D1_P CPU.MIPI_CSI1_D1_P B10 VDD_ANA_1V8 D
J1.114 USB1_RX_N CPU.USB1_RX_N A12 VDD_ANA_1V8 D Only for i.MX933x/i.MX935x
J1.116 USB1_RX_P CPU.USB1_RX_P B12 VDD_ANA_1V8 D Only for i.MX933x/i.MX935x
J1.118 USB1_TX_N CPU.USB1_TX_N A13 VDD_ANA_1V8 D Only for i.MX933x/i.MX935x
J1.120 USB1_TX_P CPU.USB1_TX_P B13 VDD_ANA_1V8 D Only for i.MX933x/i.MX935x
J1.122 DGND DGND - - G
J1.124 ENET1_MDC CPU.ENET1_MDC AA11 NVCC_3V3 IO Pin ALT-0 ENET_QOS.MDC
Pin ALT-1 UART3.DCR_B
Pin ALT-2 I3C2.SCL
Pin ALT-3 USB1.OTG_ID
Pin ALT-4 FLEXIO2.FLEXIO[0]
Pin ALT-5 GPIO4.IO00
J1.126 ENET1_MDIO CPU.ENET1_MDIO AA10 NVCC_3V3 IO Pin ALT-0 ENET_QOS.MDIO
Pin ALT-1 UART3.RIN_B
Pin ALT-2 I3C2.SDA
Pin ALT-3 USB1.OTG_PWR
Pin ALT-4 FLEXIO2.FLEXIO[1]
Pin ALT-5 GPIO4.IO01
J1.128 SD1_CLK CPU.SD1_CLK Y11 NVCC_3V3 IO Pin ALT-0 USDHC1.CLK
Pin ALT-4 FLEXIO1.FLEXIO[8]
Pin ALT-5 GPIO3_IO08
J1.130 SD1_CMD CPU.SD1_CMD AA12 NVCC_3V3 IO Pin ALT-0 USDHC1.CMD
Pin ALT-4 FLEXIO1.FLEXIO[9]
Pin ALT-5 GPIO3_IO09
J1.132 ETH1_LED5 LAN.LED5/GPIO4 13 NVCC_3V3 O
J1.134 SD1_STROBE CPU.SD1_CLK Y11 NVCC_3V3 IO Pin ALT-0 USDHC1.CLK
Pin ALT-1 FLEXSPI.A_DQS
Pin ALT-4 FLEXIO1.FLEXIO[18]
Pin ALT-5 GPIO3_IO018
J1.136
J1.138 SD1_DATA0 CPU.SD1_DATA0 AA14 NVCC_3V3 IO Pin ALT-0 USDHC1.DATA0
Pin ALT-4 FLEXIO1.FLEXIO[10]
Pin ALT-5 GPIO3_IO10
J1.140 SD1_DATA1 CPU.SD1_DATA1 AA15 NVCC_3V3 IO Pin ALT-0 USDHC1.DATA1
Pin ALT-4 FLEXIO1.FLEXIO[11]
Pin ALT-5 GPIO3_IO11
J1.142 SD1_DATA2 CPU.SD1_DATA2 AA16 NVCC_3V3 IO Pin ALT-0 USDHC1.DATA2
Pin ALT-4 FLEXIO1.FLEXIO[12]
Pin ALT-5 GPIO3_IO12
J1.144 SD1_DATA3 CPU.SD1_DATA3 Y11 NVCC_3V3 IO Pin ALT-0 USDHC1.DATA3
Pin ALT-4 FLEXIO1.FLEXIO[13]
Pin ALT-5 GPIO3_IO13
J1.146 DGND DGND - - G
J1.148 SD1_DATA4 CPU.SD1_DATA4 Y13 NVCC_3V3 IO Pin ALT-0 USDHC1.DATA4
Pin ALT-1 FLEXSPI.A_DATA[4]
Pin ALT-4 FLEXIO1.FLEXIO[14]
Pin ALT-5 GPIO3_IO14
J1.150 SD1_DATA5 CPU.SD1_DATA5 Y14 NVCC_3V3 IO Pin ALT-0 USDHC1.DATA5
Pin ALT-1 FLEXSPI.A_DATA[5]
Pin ALT-4 FLEXIO1.FLEXIO[15]
Pin ALT-5 GPIO3_IO15
J1.152 SD1_DATA5 CPU.SD1_DATA6 Y15 NVCC_3V3 IO Pin ALT-0 USDHC1.DATA6
Pin ALT-1 FLEXSPI.A_DATA[6]
Pin ALT-4 FLEXIO1.FLEXIO[16]
Pin ALT-5 GPIO3_IO16
J1.154 SD1_DATA7 CPU.SD1_DATA7 Y16 NVCC_3V3 IO Pin ALT-0 USDHC1.DATA7
Pin ALT-1 FLEXSPI.A_DATA[7]
Pin ALT-4 FLEXIO1.FLEXIO[17]
Pin ALT-5 GPIO3_IO17
J1.156 ENET2_TD3 CPU.ENET2_TD3 T10 NVCC_3V3 IO Pin ALT-0 ENET2.RGMII_TD3
Pin ALT-2 SAI2.RX_DATA[0]
Pin ALT-4 FLEXIO2.FLEXIO[16]
Pin ALT-5 GPIO4.IO16
J1.158 ENET2_TD2 CPU.ENET2_TD2 V8 NVCC_3V3 IO Pin ALT-0 ENET2.RGMII_TD2
Pin ALT-1 ENET2.TX_CLK // CCMSRCGPMCMIX.ENET_REF_CLK_ROOT
Pin ALT-2 SAI2.RX_DATA[1]
Pin ALT-4 FLEXIO2.FLEXIO[17]
Pin ALT-5 GPIO4.IO17
J1.160 ENET2_TD1 CPU.ENET2_TD1 U8 NVCC_3V3 IO Pin ALT-0 ENET2.RGMII_TD1
Pin ALT-1 UART4.RTS_B
Pin ALT-2 SAI2.RX_DATA[2]
Pin ALT-4 FLEXIO2.FLEXIO[18]
Pin ALT-5 GPIO4.IO18
J1.162 ENET2_TD0 CPU.ENET2_TD0 T8 NVCC_3V3 IO Pin ALT-0 ENET2.RGMII_TD0
Pin ALT-1 UART4.TX
Pin ALT-2 SAI2.RX_DATA[3]
Pin ALT-4 FLEXIO2.FLEXIO[19]
Pin ALT-5 GPIO4.IO19
J1.164 DGND DGND - - G
J1.166 ENET2_XC CPU.ENET2_XC U6 NVCC_3V3 IO Pin ALT-0 ENET2.RGMI_TXC
Pin ALT-1 ENET2.TX_ER
Pin ALT-2 SAI2.TX_BCLK
Pin ALT-4 FLEXIO2.FLEXIO[21]
Pin ALT-5 GPIO4.IO21
J1.168 ENET2_TX_CTL CPU.ENET2_TX_CTL V6 NVCC_3V3 IO Pin ALT-0 ENET2.RGMI_TX_CTL
Pin ALT-1 UART4.DTR_B
Pin ALT-2 SAI2.TX_SYNC
Pin ALT-4 FLEXIO2.FLEXIO[20]
Pin ALT-5 GPIO4.IO20
J1.170 ENET2_MDC CPU.ENET2_MDC Y7 NVCC_3V3 IO Pin ALT-0 ENET2.MDC
Pin ALT-1 UART4.DCR_B
Pin ALT-2 SAI2.RX_SYNC
Pin ALT-4 FLEXIO2.FLEXIO[14]
Pin ALT-5 GPIO4.IO14
J1.172 ENET2_MDIO CPU.ENET2_MDIO AA6 NVCC_3V3 IO Pin ALT-0 ENET2.MDIO
Pin ALT-1 UART4.RIN_B
Pin ALT-2 SAI2.RX_BCLK
Pin ALT-4 FLEXIO2.FLEXIO[15]
Pin ALT-5 GPIO4.IO15
J1.174 ENET2_RX_CTL CPU.ENET2_RX_CTL Y4 NVCC_3V3 IO Pin ALT-0 ENET2.RGMII_RX_CTL
Pin ALT-1 UART4.DSR_B
Pin ALT-2 SAI2.TX_DATA[0]
Pin ALT-4 FLEXIO2.FLEXIO[22]
Pin ALT-5 GPIO4.IO22
J1.176 ENET2_RD0 CPU.ENET2_RD0 AA4 NVCC_3V3 IO Pin ALT-0 ENET2.RGMII_RD0
Pin ALT-1 UART4.RX
Pin ALT-2 SAI2.TX_DATA[2]
Pin ALT-4 FLEXIO2.FLEXIO[24]
Pin ALT-5 GPIO4.IO24
J1.178 ENET2_RD1 CPU.ENET2_RD1 Y5 NVCC_3V3 IO Pin ALT-0 ENET2.RGMII_RD1
Pin ALT-1 SPDIF1.IN
Pin ALT-2 SAI2.TX_DATA[3]
Pin ALT-4 FLEXIO2.FLEXIO[25]
Pin ALT-5 GPIO4.IO25
J1.180 ENET2_RD2 CPU.ENET2_RD2 AA5 NVCC_3V3 IO Pin ALT-0 ENET2.RGMII_RD1
Pin ALT-1 UART4.CTS_B
Pin ALT-2 SAI2.MCLK
Pin ALT-3 MQS2.RIGHT
Pin ALT-4 FLEXIO2.FLEXIO[26]
Pin ALT-5 GPIO4.IO26
J1.182 ENET2_RD3 CPU.ENET2_RD3 Y6 NVCC_3V3 IO Pin ALT-0 ENET2.RGMII_RD3
Pin ALT-1 SPDIF1.OUT
Pin ALT-2 SPDIF1.N
Pin ALT-3 MQS2.LEFT
Pin ALT-4 FLEXIO2.FLEXIO[27]
Pin ALT-5 GPIO4.IO27
J1.184 ENET2_RXC CPU.ENET2_RXC AA3 NVCC_3V3 IO Pin ALT-0 ENET2.RGMII_RXC
Pin ALT-1 ENET2.RX_ER
Pin ALT-2 SAI2.TX_DATA[1]
Pin ALT-4 FLEXIO2.FLEXIO[23]
Pin ALT-5 GPIO4.IO23
J1.186 USB1_VBUS CPU.USB1_VBUS F13 NVCC_3V3 D (3V3 reference signal)
J1.188 USB2_VBUS CPU.USB2_VBUS E14 NVCC_3V3 D (3V3 reference signal)
J1.190 DGND DGND - - G
J1.192 USB1_ID CPU.USB1_ID C11 D
J1.194 USB2_ID CPU.USB2_ID E12 D
J1.196 USB1_DN CPU.USB1_DN A14 D
J1.198 USB1_DP CPU.USB1_DP B14 D
J1.200 USB2_DP CPU.USB2_DP B15 D
J1.202 USB2_DN CPU.USB2_DN A15 D
J1.204 DGND DGND - - G
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