AURA SOM/AURA Hardware/Pinout Table

History
ID#	Issue Date	Notes
17891	15/05/2023	Preliminary version

Contents

Connectors and Pinout TableEdit

Connectors descriptionEdit

In the following table are described all available connectors integrated on AURA SOM:

Connector name	Connector Type	Notes	Carrier board counterpart
J1	SODIMM DDR3 edge connector 204 pin		TE Connectivity 2013289-1

The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to AURA pinout specifications. See the images below for reference:

AURA TOP view

AURA BOTTOM view

Pinout table naming conventionsEdit

This chapter contains the pinout description of the AURA module, grouped in two tables (odd and even pins) that report the pin mapping of the 204-pin SO-DIMM AURA connector.

Each row in the pinout tables contains the following information:

Pin	Reference to the connector pin
Pin Name	Pin (signal) name on the AURA connectors
Internal connections	Connections to the AURA components CPU.<x> : pin connected to CPU pad named <x> CAN.<x> : pin connected to the CAN transceiver (TI SN65HVD232) PMIC.<x> : pin connected to the Power Manager IC (NXP PCA9451A) LAN.<x> : pin connected to the LAN PHY (Microchip LAN8830T-V) NOR.<x>: pin connected to the flash NOR SV.<x>: pin connected to voltage supervisor MTR: pin connected to voltage monitors
Ball/pin #	Component ball/pin number connected to signal
Voltage	I/O voltage levels
Type	Pin type: I = Input O = Output D = Differential Z = High impedance S = Power supply voltage G = Ground A = Analog signal
Notes	Remarks on special pin characteristics
Pin MUX alternative functions	Muxes: Pin ALT-0 ... Pin ALT-N The number of functions depends on platform

Voltage domainsEdit

Voltage domain	Nominal voltage [V]	Notes
3.3VIN	3.3	See Operational_characteristics of the SoM wiki page
NVCC_3V3	3.3	Voltage generated by the internal PSU. See Power Supply Unit (PSU) wiki page
NVCC_GPIO	3.3	Voltage generated by the internal PSU. See Power Supply Unit (PSU) wiki page

Pinout Table ODD pins declarationEdit

Pin	Pin Name	Internal Connections	Ball/pin #	Voltage domain	Type	Notes	Alternative Functions
J1.1	DGND	DGND	-	-	G
J1.3	3.3VIN	INPUT VOLTAGE	-	3.3VIN	S
J1.5	3.3VIN	INPUT VOLTAGE	-	3.3VIN	S
J1.7	3.3VIN	INPUT VOLTAGE	-	3.3VIN	S
J1.9	3.3VIN	INPUT VOLTAGE	-	3.3VIN	S
J1.11	DGND	DGND	-	-	G
J1.13	ETH1_LED1	LAN.LED1/PME_N1	18	NVCC_3V3	O
J1.15	ETH1_LED2	LAN.LED2	16	NVCC_3V3	O
J1.17	DGND	DGND	-	-	G
J1.19	ETH1_TXRX0_P	LAN.TXRXP_A	2	NVCC_3V3	D
J1.21	ETH1_TXRX0_M	LAN.TXRXM_A	3	NVCC_3V3	D
J1.23	ETH1_TXRX1_P	LAN.TXRXP_B	5	NVCC_3V3	D
J1.25	ETH1_TXRX1_M	LAN.TXRXM_B	6	NVCC_3V3	D
J1.27	ETH1_TXRX2_P	LAN.TXRXP_C	7	NVCC_3V3	D
J1.29	ETH1_TXRX2_M	LAN.TXRXM_C	8	NVCC_3V3	D
J1.31	ETH1_TXRX3_P	LAN.TXRXP_D	10	NVCC_3V3	D
J1.33	ETH1_TXRX3_M	LAN.TXRXM_D	11	NVCC_3V3	D
J1.35	DGND	DGND	-	-	G
J1.37	ETH1_LED3	LAN.LED3/GPIO2	15	NVCC_3V3	O
J1.39	ETH1_LED4	LAN.LED4/GPIO3	14	NVCC_3V3	O
J1.41	ETH_OSC_EN		46	NVCC_3V3	I			(mounting option)
J1.43	GPIO_IO06	CPU.GPIO_IO06	L20	NVCC_GPIO	IO		Pin ALT-0	GPIO2_IO06
							Pin ALT-1	TMP5.CH0
							Pin ALT-2	PDM.BIT_STREAM[1]
							Pin ALT-3	LCDIF.D[2]
							Pin ALT-4	SPI7.SOUT
							Pin ALT-5	UART6.CTS_B
							Pin ALT-6	I2C7.SDA
							Pin ALT-7	FLEXIO1.FLEXIO[6]
J1.45	GPIO_IO18	CPU.GPIO_IO18	R18	NVCC_GPIO	IO		Pin ALT-0	GPIO2_IO18
							Pin ALT-1	SAI3.RX_BCLK
							Pin ALT-2	ISI.D[9]
							Pin ALT-3	LCDIF.D[14]
							Pin ALT-4	SPI5.PCS0
							Pin ALT-5	SPI4.PCS0
							Pin ALT-6	TMP5.CH2
							Pin ALT-7	FLEXIO1.FLEXIO[18]
J1.47	GPIO_IO09	CPU.GPIO_IO09	M21	NVCC_GPIO	IO		Pin ALT-0	GPIO2_IO09
							Pin ALT-1	SPI3.SIN
							Pin ALT-2	ISI.D[3]
							Pin ALT-3	LCDIF.D[5]
							Pin ALT-4	TMP3.EXTCLK
							Pin ALT-5	UART7.RX
							Pin ALT-6	I2C7.SCL
							Pin ALT-7	FLEXIO1.FLEXIO[9]
J1.49	GPIO_IO08	CPU.GPIO_IO08	M20	NVCC_GPIO	IO		Pin ALT-0	GPIO2_IO08
							Pin ALT-1	SPI3.SPCS0
							Pin ALT-2	ISI.D[2]
							Pin ALT-3	LCDIF.D[4]
							Pin ALT-4	TMP6.CH0
							Pin ALT-5	UART7.TX
							Pin ALT-6	I2C7.SDA
							Pin ALT-7	FLEXIO1.FLEXIO[8]

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