BORA SOM/BORA Hardware/Power and Reset/System boot
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| 1.0.0 | Oct 2021 | New documentation layout | |
Contents
System boot[edit | edit source]
The boot process begins at Power On Reset (POR) where the hardware reset logic forces the ARM core to begin execution starting from the on-chip boot ROM.
Boot options[edit | edit source]
The boot ROM supports configuration from four different slave interfaces:
- Quad-SPI
- NAND
- NOR flash (not available on BORA)
- SD card
Boot mode is selectable via five mode pins (BOOT_MODE[4:0]), and two voltage mode signals, (VMODE[1:0]). The BOOT_MODE pins are MIO[6:2] and the VMODE pins are MIO[8:7]. The pins are used as follows:
| Function | Boot signals | Available options |
|---|---|---|
| JTAG mode | BOOT_MODE[3] MIO[2] |
0: Cascaded JTAG 1: Independent JTAG |
| Boot mode | BOOT_MODE[0-2-1] MIO[5:3] |
000: JTAG 010: NAND 100: Quad-SPI 110: SD card |
| PLLs enable | BOOT_MODE[4] MIO[6] |
0: PLL used 1: PLL bypassed |
| MIO Bank 0 Voltage | VMODE[0] MIO[7] |
0: 2.5 V, 3.3 V 1: 1.8 V |
| MIO Bank 0 Voltage | VMODE[1] MIO[8] |
0: 2.5 V, 3.3 V 1: 1.8 V |
In order to fully understand how boot works on BORA platform, please refer to chapter 6 ("Boot and configuration") of the Zynq7000 Technical Reference Manual.
Default boot configuration[edit | edit source]
Default configuration for BORA module is:
- Mode[0..3] = 1000: Quad-SPI mode
- Mode[4] = 0: PLL not bypassed
- VCFG[0] = 0: 2.5V, 3.3V operations for bank 0
- VCFG[1] = 1: 1.8 operations for bank 1
Assuming that:
- default configuration is not changed,
- there's a valid boot code programmed in SPI flash memory the actual boot sequence performed by ARM core will be:
- Bootrom is executed from internal ROM code memory
- FSBL is copied from on-board NOR flash memory connected to SPI0 port to on-chip SRAM by bootrom
- FSBL is executed from on-chip SRAM
- U-Boot bootloader (2nd stage) is copied by FSBL from NOR flash memory connected to Quad-SPI port to SDRAM
- U-boot (2nd stage) is executed from SDRAM
If no boot code is available in SPI NOR flash, the bootrom tries JTAG peripheral booting.
Boot sequence customization[edit | edit source]
BOOT_MODE[4:0] are routed to the J1 connector, enabling for the customization of the boot sequence through a simple resistor network that can be implemented on carrier board hosting BORA module.
| Mode signal | J1 pin | Pin name |
|---|---|---|
| BOOT_MODE[4] | J1.129 | SPI0_SCLK/MODE4/NAND_IO1 |
| BOOT_MODE[3] | J1.125 | SPI0_DQ0/MODE3/NAND_ALE |
| BOOT_MODE[2] | J1.121 | SPI0_DQ2/MODE2/NAND_IO2 |
| BOOT_MODE[1] | J1.123 | SPI0_DQ1/MODE1/NAND_WE |
| BOOT_MODE[0] | J1.119 | SPI0_DQ3/MODE0/NAND_IO0 |
