dave_user
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→Reset scheme and control signals
* '''SYS_nRST'''
* '''WDOG_B''', pulled-up with 100 kohm
* '''CPU_PORn''', pulled-up with 100 kohm. This signal, pilot by the PMIC, reset SoC's CPU and onboard eMMC and ethernet PHY.
* '''PMIC_INTn''', pulled-up with 10 kohm
Furthermore, the following some control signals are avaible:
* '''SOM_PGOOD''',
'''TBD: indicare le connessioni del segnale di reset verso altri device interni (come per esempio la NOR SPI'''
The electrical and functional characteristics of these signals are listed in the following table:
{| class="wikitable"
|+
!Signal
!Type
!Drive
!Purpose
|-
|'''SYS_nRST'''
|Input
|
|
|-
|'''WDOG_B'''
|Input, pulled-up with 100 kohm
|
|
|-
|'''CPU_PORn'''
|Output, open drain, on SOM pulled-up with 100 kohm
|
|
|-
|'''SOM_PGOOD'''
|Output, 3V3 LVTTL
|
|
|-
|'''PMIC_INTn'''
|Input, pulled-up with 10 kohm
|
|
|-
|'''PMIC_ON_REQ'''
|Input, pulled-down with 100 kohm
|
|
|-
|'''PMIC_STBY_REQ'''
|Input, pulled-down with 100 kohm
|
|
|-
|'''ONOFF'''
|Input, pulled-up with 100 kohm
|
|
|}
=== CPU_PORn ===
Since SPI NOR flash can be used as a boot device, CPU_PORn is connected to this device too. This guarantees it is in a known state when reset signal is released.
Ciclo di reset completo utilizzare
=== Handling CPU-initiated software reset ===