Difference between revisions of "ETRA SOM/ETRA Hardware/Peripherals/QUADSPI"
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==Peripheral QUADSPI == | ==Peripheral QUADSPI == | ||
| − | + | The QUADSPI is a dedicated communication interface for single, dual or quad SPI Flash memories. | |
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=== Description === | === Description === | ||
| − | The QUADSPI interface available on ETRA is based on | + | The QUADSPI interface available on ETRA SOM is based on STM32MP1 SoC. |
The QUADSPI port supports the following standards and features: | The QUADSPI port supports the following standards and features: | ||
| − | * | + | * three functional modes: indirect, status-polling, and memory-mapped |
| − | * | + | ** indirect mode: all the operations are performed using the QUADSPI registers |
| − | * | + | **status polling mode: the external Flash memory status register is periodically read and an interrupt can be generated in case of flag setting |
| − | * | + | **memory-mapped mode: the external Flash memory is mapped to the device address space and is seen by the system as if it was an internal memory |
| + | *dual-flash mode, where 8 bits can be sent/received simultaneously by accessing two Flash memories in parallel | ||
| + | *integrated FIFO for reception and transmission | ||
| + | *8, 16, and 32-bit data accesses | ||
| + | *DMA channel for indirect mode operations | ||
| + | *interrupt generation on FIFO threshold, timeout, operation complete, and access error | ||
===Pin mapping=== | ===Pin mapping=== | ||
Latest revision as of 11:43, 8 January 2024
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Contents
Peripheral QUADSPIEdit
The QUADSPI is a dedicated communication interface for single, dual or quad SPI Flash memories.
DescriptionEdit
The QUADSPI interface available on ETRA SOM is based on STM32MP1 SoC.
The QUADSPI port supports the following standards and features:
- three functional modes: indirect, status-polling, and memory-mapped
- indirect mode: all the operations are performed using the QUADSPI registers
- status polling mode: the external Flash memory status register is periodically read and an interrupt can be generated in case of flag setting
- memory-mapped mode: the external Flash memory is mapped to the device address space and is seen by the system as if it was an internal memory
- dual-flash mode, where 8 bits can be sent/received simultaneously by accessing two Flash memories in parallel
- integrated FIFO for reception and transmission
- 8, 16, and 32-bit data accesses
- DMA channel for indirect mode operations
- interrupt generation on FIFO threshold, timeout, operation complete, and access error
Pin mappingEdit
The Pin mapping is described in the Pinout table section