Difference between revisions of "ETRA SOM/ETRA Hardware/Peripherals/GPIOs"
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==Peripheral GPIOs == | ==Peripheral GPIOs == | ||
| − | + | The general-purpose input/output (GPIO) peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs. | |
| − | |||
=== Description === | === Description === | ||
| − | The GPIOs interface available on ETRA is based on | + | The primary GPIOs interface available on ETRA SOM is based on STM32MP1 SoC. |
| − | The | + | The STM32MP1 GPIO ports supports the following standards and features: |
| − | * | + | * output states: push-pull or open drain + pull-up/down |
| − | * | + | * speed selection for each I/O |
| − | * | + | * input states: floating, pull-up/down, analog |
| − | * | + | * bit set and reset register for atomic read/modify access |
| + | * analog function | ||
| + | * fast toggle capable of changing every two clock cycles | ||
| + | * external interrupt capability (unavailable in analog mode) | ||
| + | A secondary GPIOs interface available on ETRA SoM is based on ADP5589 I/O expander. This expander is controlled by an internal I2C BUS. | ||
===Pin mapping=== | ===Pin mapping=== | ||
Latest revision as of 11:44, 8 January 2024
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| History | |||
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| 2020/12/31 | First Release | ||
Contents
Peripheral GPIOsEdit
The general-purpose input/output (GPIO) peripheral provides dedicated general-purpose pins that can be configured as either inputs or outputs.
DescriptionEdit
The primary GPIOs interface available on ETRA SOM is based on STM32MP1 SoC.
The STM32MP1 GPIO ports supports the following standards and features:
- output states: push-pull or open drain + pull-up/down
- speed selection for each I/O
- input states: floating, pull-up/down, analog
- bit set and reset register for atomic read/modify access
- analog function
- fast toggle capable of changing every two clock cycles
- external interrupt capability (unavailable in analog mode)
A secondary GPIOs interface available on ETRA SoM is based on ADP5589 I/O expander. This expander is controlled by an internal I2C BUS.
Pin mappingEdit
The Pin mapping is described in the Pinout table section