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Difference between revisions of "ORCA SOM/ORCA Evaluation Kit/Interfaces and Connectors/JTAG"

< ORCA SOM‎ | ORCA Evaluation Kit
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__FORCETOC__
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<section begin="Body" />
  
 
==JTAG interface ==
 
==JTAG interface ==
  
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''TBD: sostituire le sezioni con le informazioni sull'uso della periferica e del suo connettore''
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JTAG interface allow the developer to access every peripheral of the SoC using a debugger.
−
''Nell'esempio di seguito c'è la descrizione dell'interfaccia UART/console''
+
 
 +
It is also possible to add the ETH1 PHY to the JTAG daisy chain (with a custom BOM).
 +
 
 +
The TRACE interface can be made available in alternative to the NAND or eMMC memory flash on board of the SoM.
  
 
=== Description  ===
 
=== Description  ===
  
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The JTAG interface available on the Evaluation Kit at the connector ''TBD:Jxxx''.  
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The JTAG interface available on the Evaluation Kit at the connector JD1.  
  
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''Jxx'' is a ''TBD:connector-type'' header connector for the RS232 two-wires UART3 port, used for debug purposes (bootloader and operating system serial console).
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JD1 is a 10x1x2.54mm strip header connector and it is not mounted.
  
  
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[[File:{{{nome-som}}-EVB-JTAG-connector.png|thumb|center|500px|JTAG connector]]
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[[File:ORCA-EVK-JTAG-connector.png|thumb|center|500px|JTAG connector]]
  
 
===Signals ===
 
===Signals ===
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{| class="wikitable"  
 
{| class="wikitable"  
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! latexfontsize="scriptsize"| Pin#
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! latexfontsize="scriptsize" | Pin#
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! latexfontsize="scriptsize"| SOM Pin#
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! latexfontsize="scriptsize" | Pin name
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! latexfontsize="scriptsize"| Pin name
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! latexfontsize="scriptsize" |Function
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! latexfontsize="scriptsize"| Pin function
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! latexfontsize="scriptsize" |'''ARM-20 JTAG'''
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! latexfontsize="scriptsize"| Pin Notes
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! latexfontsize="scriptsize" | Notes
 +
|-
 +
|1
 +
|DGND
 +
| -
 +
|4,6,8,10,12,14,16,18,20
 +
|For example documented on [https://www2.lauterbach.com/pdf/app_arm_jtag.pdf#page=3 Lauterbach specification]
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|-
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|2
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|JTAG_TCK
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| -
 +
|9
 +
| -
 
|-
 
|-
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|1,2,4,6,,7,8,10
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|3
 +
|JTAG_TMS
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| -
 +
|7
 
| -
 
| -
−
| N.A.
 
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| N.C.
 
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| Not connected
 
 
|-
 
|-
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| 3
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|4
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| J1.189
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|JTAG_TDO
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| RS232_RX
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| -
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| Receive line
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|13
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|  
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| -
 
|-
 
|-
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| 3
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|5
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| J1.187
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|JTAG_TDI
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| RS232_TX
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| -
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| Transmit line
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|5
−
|  
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| -
 
|-
 
|-
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| 9
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|6
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|JTAG_MOD
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| -
 
| -
 
| -
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| DGND
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|10K pull-down inside the SoM
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| Ground
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|-
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|  
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|7
 +
|CPU_PORn
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| -
 +
|15 (*)
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| -
 +
|-
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|8
 +
|N.C.
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| -
 +
| -
 +
| -
 +
|-
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|9
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|N.C.
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| -
 +
| -
 +
| -
 +
|-
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|10
 +
|JTAG_VREF
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| -
 +
|1
 +
|3V3 (BOARD_PGOOD driven signal)
 
|}
 
|}
 +
(*) optional signals, keep the possibility to be unconnected.
  
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=== Device mapping ===
 
−
UART3 is mapped to <code>/dev/ttymxc2</code> device in Linux. The peripheral is used as the default serial console, both for the bootloader and the kernel.
 
−
 
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=== Device usage ===
 
−
 
−
To connect to the debug serial port:
 
−
 
−
# connect the DB9 adapter bracket to the J22 connector on the SBCX board
 
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# connect a serial cable between DB9 connector and PC COM port through a NULL-modem cable (not provided)
 
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# start your favorite terminal emulator software on PC (eg: PuTTY); communication parameters are: 115200,N,8,1
 
  
 
----
 
----
  
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[[Category:ORCA SOM]]
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[[Category:ORCA]]

Latest revision as of 20:45, 8 January 2024

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History
Issue Date Notes
2021/12/10 First release



Contents

JTAG interfaceEdit

JTAG interface allow the developer to access every peripheral of the SoC using a debugger.

It is also possible to add the ETH1 PHY to the JTAG daisy chain (with a custom BOM).

The TRACE interface can be made available in alternative to the NAND or eMMC memory flash on board of the SoM.

DescriptionEdit

The JTAG interface available on the Evaluation Kit at the connector JD1.

JD1 is a 10x1x2.54mm strip header connector and it is not mounted.


 
JTAG connector

SignalsEdit

The following table describes the interface signals:

Pin# Pin name Function ARM-20 JTAG Notes
1 DGND - 4,6,8,10,12,14,16,18,20 For example documented on Lauterbach specification
2 JTAG_TCK - 9 -
3 JTAG_TMS - 7 -
4 JTAG_TDO - 13 -
5 JTAG_TDI - 5 -
6 JTAG_MOD - - 10K pull-down inside the SoM
7 CPU_PORn - 15 (*) -
8 N.C. - - -
9 N.C. - - -
10 JTAG_VREF - 1 3V3 (BOARD_PGOOD driven signal)

(*) optional signals, keep the possibility to be unconnected.


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