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Difference between revisions of "ETRA SOM/ETRA Hardware/Power and Reset/Reset scheme and control signals"

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[[File:ETRA-reset-scheme.png | 800px]]
 
[[File:ETRA-reset-scheme.png | 800px]]
−
 
−
''TBD: qui di seguito vanno inserite le sezioni che includano la descrizione dei segnali coinvolti nella fase di Reset, ad esempio:''
 
−
 
−
* MRST
 
−
* POR
 
−
* SNVS
 
−
* SYSRST
 
−
* ...
 
−
 
−
'''TBD: indicare le connessioni del segnale di reset verso altri device interni (come per esempio la NOR SPI'''
 
−
 
−
''TBD: di seguito la pagina di AXEL Lite da rivedere nel caso di altri SOM''
 
  
 
=== VDD ===
 
=== VDD ===
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=== NRST ===
 
=== NRST ===
−
Rest signal, tie to DGND to reset the system. It is driven by the PMIC to set the CPU in reset state.
+
Open drain rest signal, tie to DGND to reset the system.
 +
 
 +
It is driven by:
 +
* the PMIC to force the CPU in reset state
 +
* the CPU over a soft reset to restart the application
 +
This signal is also used to reset the following on board peripherals:
 +
* SPI NOR
 +
* eMMC
  
 
=== SOM_PGOOD ===
 
=== SOM_PGOOD ===
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=== PWR_ON ===
 
=== PWR_ON ===
 +
Power on CPU output signal, The state of this signal depends on power state of the processor.
  
 
=== PDR_ON ===
 
=== PDR_ON ===
 +
Input pin that disables the VDD internal voltage monitor. When this signal is set to logic 1 the processor does not issue a reset cycle when the VDD goes below the VVD_OK threshold.
 +
 +
Driven by default by PMIC, internally used for deep sleep modes.
  
 
=== PDR_ON_CORE ===
 
=== PDR_ON_CORE ===
 +
Input pin that disables the VDD_CORE internal voltage monitor. When this signal is set to logic 1 the processor does not issue a core reset cycle when the VDD_CORE goes below the VVD_OK threshold.
 +
 +
Driven by default by PMIC, internally used for deep sleep modes.
  
 
=== PWR_LP ===
 
=== PWR_LP ===
  
−
=== PMIC_VSNVS ===
+
CPU low power mode output, internally used by the PMIC to check the CPU low power state.
−
Some signals that are related to reset circuitry are pulled-up to PMIC_VSNVS. This voltage is generated by PMIC PF0100's VSNVS LDO/Switch and its actual value depends on:
 
−
* voltage applied to PMICS's VIN pin
 
−
** in case of AxelLite this pin is connected to 3.3VIN power rail
 
−
* voltage applied to PMICS's LICELL pin
 
−
** in case of AxelLite this pin is connected to pin 14 of SODIMM connector (PMIC_LICELL)
 
−
* PMIC's VSNVSCTL register configuration.
 
−
Hence '''it is recommended that system designer takes into account these factors in order to properly manage these signals at carrier board level'''.
 
−
 
 
−
For more details please refer to section ''VSNVS LDO/Switch'' of ''MMPF0100 Advance Information'' document.
 
−
 
 
−
=== CPU_PORn ===
 
−
 
 
−
The following devices can assert this active-low signal:
 
−
* PMIC
 
−
* multiple-voltage monitor: this device monitors critical power voltages and triggers a reset pulse in case any of these exhibits a brownout condition
 
−
 
 
−
Since SPI NOR flash can be used as boot device, CPU_PORn is connected to this device too. This guarantees it is in a known state when reset signal is released.
 
−
 
 
−
 
 
−
=== Handling CPU-initiated software reset ===
 
−
'''By default, MX6 processor does not assert any external signal when it initiates a software reset sequence. Also default software reset implementation does not guarantee that all processor registers are reset properly'''.
 
−
 
 
−
For these reasons, it is strongly recommended to use a different approach that, in combination with the use of a processor's watchdog timer (WDT), provides a full hardware reset in case a software reset is issued.
 
  
−
This technique is implemented in [[DESK-ETRA-L]]. At software level, U-Boot and Linux kernel software reset routines make use of processor's WDT #2 to assert the WDOG2_B reset signal. This signal in turn is routed to GPIO_1 pad (MUX mode = 1). At hardware level, this signal is AC-coupled to a 3-state output buffer (please refer to U22 chip of [[AxelEVB-Lite]] carrier board), driving PMIC_PWRON.
+
=== WAKEUP ===
 +
PMIC power on signal from CPU, used in low power mode by the CPU internal RTC to restart the PMIC.
  
 
----
 
----
  
 
[[Category:ETRA]]
 
[[Category:ETRA]]

Latest revision as of 11:39, 8 January 2024

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History
Issue Date Notes
2020/12/30 First Release


Contents

Reset scheme and control signalsEdit

The following picture shows the simplified block diagram of reset scheme and voltage monitoring.

 

VDDEdit

Some signals that are related to reset circuitry are pulled-up to VDD rail. This voltage is generated by the PMIC and act as power good to switch on/off the all the peripheral that could back power the CPU.

NRSTEdit

Open drain rest signal, tie to DGND to reset the system.

It is driven by:

  • the PMIC to force the CPU in reset state
  • the CPU over a soft reset to restart the application

This signal is also used to reset the following on board peripherals:

  • SPI NOR
  • eMMC

SOM_PGOODEdit

This is a convencional signal to drive DC/DC enable inputs or switch on/off control signals. It is connected to the VDD through a 22Ohm resistor.

PONKEYnEdit

User power on key (active low with internal pull-up), used to wake up the sysytem from power down.

NRST_COREEdit

Reset signal for the core, to be used if the VDD_CORE is not disabled during the reset. Internally tied to NRST signal.

PWR_ONEdit

Power on CPU output signal, The state of this signal depends on power state of the processor.

PDR_ONEdit

Input pin that disables the VDD internal voltage monitor. When this signal is set to logic 1 the processor does not issue a reset cycle when the VDD goes below the VVD_OK threshold.

Driven by default by PMIC, internally used for deep sleep modes.

PDR_ON_COREEdit

Input pin that disables the VDD_CORE internal voltage monitor. When this signal is set to logic 1 the processor does not issue a core reset cycle when the VDD_CORE goes below the VVD_OK threshold.

Driven by default by PMIC, internally used for deep sleep modes.

PWR_LPEdit

CPU low power mode output, internally used by the PMIC to check the CPU low power state.

WAKEUPEdit

PMIC power on signal from CPU, used in low power mode by the CPU internal RTC to restart the PMIC.

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