Difference between revisions of "BoraXEVB"

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Line 1: Line 1:
 
{{InfoBoxTop}}
 
{{InfoBoxTop}}
 
{{Applies To BoraX}}
 
{{Applies To BoraX}}
−
{{Applies To BoraLite}}
 
 
{{InfoBoxBottom}}
 
{{InfoBoxBottom}}
  
−
{{WarningMessage|text=By default, BoraXEVB comes with a Zynq 7030-based SoM when it is sold with BoraX. When it is sold with Bora Lite, it is mated with a Zynq 7020-based SoM instead.
+
[[File:Boraxevb.png|650px|frameless|border]]
  
−
Nevertheless, BoarX can host different models of BoraX and Bora Lite SoM's. From the point of view of PL's I/O voltage levels, different models may not be equivalent. Please refer to [[#PL's I/O voltage selections|this section]] to avoid unsupported configurations that '''may damage the hardware permanently'''.}}
 
 
==Introduction==
 
==Introduction==
−
BORA Xpress EVB is a carrier board designed to host [[BORA_Xpress_SOM|BORA Xpress system-on-module]].
+
Bora Xpress EVB is a carrier board designed to host [[BoraXpress SOM|Bora Xpress system-on-module]].
−
 
 
−
The EVB is used also as Evaluation board for the [[:Category:BoraLite | BORA Lite SOM]].
 
−
 
 
−
[[File:BoraXEVB-01.png|500px|frameless|border]]
 
−
 
 
−
<section begin=Block Diagram/>
 
  
 
==Block Diagram==
 
==Block Diagram==
  
−
The following picture shows BORA Xpress EVB block diagram:  
+
The following picture shows Bora Xpress EVB block diagram:  
−
 
 
−
[[File:Boraxevb-block_diagram.png|thumb|center|600px|BoraXEVB simplified block diagram]]
 
−
===Configurable routing options===
 
−
FPGA banks #12, #34 and #35 supports different routing options as shown in the following picture.
 
−
 
 
−
For a detailed description of FMC connector routing, please refer to [[#FPGA Mezzanine Card (FMC) Connector - J27|this section]].
 
−
 
 
−
====BoraX====
 
−
[[File:Boraxevb-FPGA-signals-routing.png|thumb|center|600px|Configurable routing options diagram]]
 
  
−
====Bora Lite====
+
[[File:Boraxevb-bd.png]]
−
[[File:Boralite-boraxevb-FPGA-signals-routing.png|center|thumb|862x862px|Configurable routing options diagram for BoraLite SoM]]
 
−
 
 
−
<section end=Block Diagram/>
 
  
 
== Features ==
 
== Features ==
Line 64: Line 44:
 
| LCD_BKLT_PWM I/O voltage
 
| LCD_BKLT_PWM I/O voltage
 
| LCD_BKLT_PWM signal is derived from IO_0_13 on BANK13. In the case of LVDS signals for LCD the BANK 13 must be powered at 2.5V. So in this case LCD_BKLT_PWM is an LVCMOS 2.5V signal. It is recommended to place a voltage level translator to 3.3V if the signal voltages are not compatible with the LCD diplay backlight input.
 
| LCD_BKLT_PWM signal is derived from IO_0_13 on BANK13. In the case of LVDS signals for LCD the BANK 13 must be powered at 2.5V. So in this case LCD_BKLT_PWM is an LVCMOS 2.5V signal. It is recommended to place a voltage level translator to 3.3V if the signal voltages are not compatible with the LCD diplay backlight input.
−
|-
 
−
| FMC connector
 
−
| For the [[Product_serial_number|serial numbers]] included in the range EVBBX0000C0R00A0 - EVBBX0000C0R00AB, the connector that is actually mounted on the board is the LPC version, not the HPC version listed in the specifications.
 
 
|-
 
|-
 
|}
 
|}
  
 
== Connectors pinout ==
 
== Connectors pinout ==
−
<section begin=CPU/>
+
 
−
=== J1,J2 and J3 ===
+
=== J1 ===
−
The pinout of the J1, J2 and J3 connectors of the Bora Xpress EVB is the same of the [[BORA_Xpress_SOM/BORA_Xpress_Hardware/Pinout_Table#Connectors_description|counterpart connectors on BORA Xpress module]].
+
The pinout of the J1 connector of the Bora Xpress EVB is the same of  the J1 connector on BORA Xpress module
−
<section end=CPU/>
+
 
−
<section begin=Power Supply/>
+
=== J2 ===
 +
The pinout of the J2 connector of the Bora Xpress EVB is the same of the J2 connector on BORA Xpress module
 +
 
 +
=== J3 ===
 +
The pinout of the J3 connector of the Bora Xpress EVB is the same of  the J3 connector on BORA Xpress module
  
 
=== Power supply - JP2 ===
 
=== Power supply - JP2 ===
Line 95: Line 76:
 
|-
 
|-
 
|}
 
|}
−
<section end=Power Supply/>
 
−
 
−
<section begin=Reset button/>
 
−
 
−
=== Reset button - S6 ===
 
−
 
−
S6 is the hardware reset button connected to the MRSTn signal (J2.16 SOM connector)
 
−
<section end=Reset button/>
 
−
 
−
<section begin=Boot Configurations/>
 
  
 
=== Boot mode selection - S5 ===
 
=== Boot mode selection - S5 ===
Line 118: Line 89:
 
| SD-card || OFF || ON || OFF || ON || ON || OFF || ON || OFF
 
| SD-card || OFF || ON || OFF || ON || ON || OFF || ON || OFF
 
|-
 
|-
−
| NAND (*) || OFF || ON || OFF || ON || ON || OFF || ON || ON
+
| NAND || OFF || ON || OFF || ON || ON || OFF || ON || ON
 
|-
 
|-
 
| JTAG || OFF || ON || OFF || ON || ON || ON || ON || ON
 
| JTAG || OFF || ON || OFF || ON || ON || ON || ON || ON
 
|}
 
|}
  
−
<b>(*)</b> Boot mode from NAND in supported '''ONLY''' on [[BORA Lite SOM|BORA Lite]] SOM module
 
−
 
−
<section end=Boot Configurations/>
 
−
<section begin=Watchdog/>
 
−
 
−
=== WatchDog Settings - S1, S2 and S3 ===
 
−
S1, S2 and S3 are dip-switch to override the default startup delay and timeout of the BORA Xpress module watchdog.
 
−
For more details please refer to [[BORA_Xpress_SOM/BORA_Xpress_Hardware/Peripherals/Watchdog|this page]].
 
−
 
−
{| class="wikitable"
 
−
|-
 
−
!  !! S1.1 !! S1.2
 
−
|-
 
−
| WD_SET0 SOM default || OFF || OFF
 
−
|-
 
−
| WD_SET0 = '1' || ON || OFF
 
−
|-
 
−
| WD_SET0 = '0' || OFF || ON
 
−
|}
 
−
 
−
{| class="wikitable"
 
−
|-
 
−
!  !! S2.1 !! S2.2
 
−
|-
 
−
| WD_SET1 SOM default || OFF || OFF
 
−
|-
 
−
| WD_SET1 = '1' || ON || OFF
 
−
|-
 
−
| WD_SET1 = '0' || OFF || ON
 
−
|}
 
−
 
−
{| class="wikitable"
 
−
|-
 
−
!  !! S3.1 !! S3.2
 
−
|-
 
−
| WD_SET2 SOM default || OFF || OFF
 
−
|-
 
−
| WD_SET2 = '1' || ON || OFF
 
−
|-
 
−
| WD_SET2 = '0' || OFF || ON
 
−
|}
 
−
<section end=Watchdog/>
 
−
<section begin=Ethernet0/>
 
  
 
=== Ethernet port #0 (ETH0) - J8 ===
 
=== Ethernet port #0 (ETH0) - J8 ===
Line 209: Line 137:
 
|-
 
|-
 
|}
 
|}
−
<section end=Ethernet0/>
+
 
−
<section begin=Ethernet1/>
 
 
=== Ethernet port #1 (ETH1) - J9 ===
 
=== Ethernet port #1 (ETH1) - J9 ===
  
Line 253: Line 180:
 
|-
 
|-
 
|}
 
|}
−
<section end=Ethernet1/>
 
  
 
=== BANK's Power GOOD signals - J28 ===
 
=== BANK's Power GOOD signals - J28 ===
Line 285: Line 211:
 
|}
 
|}
  
−
<section begin=JTAG/>
+
=== BANK13 VDDIO selector - JP25 ===
 +
JP25 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector:
 +
 
 +
{| class="wikitable"
 +
|-
 +
!Pin#
 +
!Pin name
 +
!Function
 +
!Notes
 +
|-
 +
|2 || LDO_B13_1V6|| adds +1.6V to VDDIO_BANK13 || -
 +
|-
 +
|4 || LDO_B13_800mV|| adds +800mV to VDDIO_BANK13 || -
 +
|-
 +
|6 || LDO_B13_400mV|| adds +400mV to VDDIO_BANK13 || -
 +
|-
 +
|8 || LDO_B13_200mV|| adds +200mV to VDDIO_BANK13 || -
 +
|-
 +
|10 || LDO_B13_100mV|| adds +100mV to VDDIO_BANK13 || -
 +
|-
 +
|12 || LDO_B13_50mV|| adds +50mV to VDDIO_BANK13 || -
 +
|-
 +
|1, 3, 5, 7, 9, 11 || DGND|| - || -
 +
|-
 +
|}
 +
 
 +
The jumper configurations are:
 +
# No jumpers installed -> DC output for VDDIO_BANK13 is 500mV
 +
# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK13 above the default 500mV
 +
# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV
 +
# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13 above the default 500mV
 +
# Jumper on 7-8 -> adds 200mV to VDDIO_BANK13 above the default 500mV
 +
# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13 above the default 500mV
 +
# Jumper on 11-12 -> adds 50mV to VDDIO_BANK13 above the default 500mV
 +
 
 +
The DEFAULT configuration is VDDIO_BANK13 @ 1.8V (500mV + 800mV + 400mV + 100mV):
 +
# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV
 +
# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13
 +
# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13
 +
 
 +
=== BANK35 VDDIO selector - JP27 ===
 +
JP27 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector:
 +
 
 +
{| class="wikitable"
 +
|-
 +
!Pin#
 +
!Pin name
 +
!Function
 +
!Notes
 +
|-
 +
|2 || LDO_B35_1V6|| adds +1.6V to VDDIO_BANK35 || -
 +
|-
 +
|4 || LDO_B35_800mV|| adds +800mV to VDDIO_BANK35 || -
 +
|-
 +
|6 || LDO_B35_400mV|| adds +400mV to VDDIO_BANK35 || -
 +
|-
 +
|8 || LDO_B35_200mV|| adds +200mV to VDDIO_BANK35 || -
 +
|-
 +
|10 || LDO_B35_100mV|| adds +100mV to VDDIO_BANK35 || -
 +
|-
 +
|12 || LDO_B35_50mV|| adds +50mV to VDDIO_BANK35 || -
 +
|-
 +
|1, 3, 5, 7, 9, 11 || DGND|| - || -
 +
|-
 +
|}
 +
 
 +
The jumper configurations are:
 +
# No jumpers installed -> DC output for VDDIO_BANK35 is 500mV
 +
# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK35 above the default 500mV
 +
# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above the default 500mV
 +
# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35 above the default 500mV
 +
# Jumper on 7-8 -> adds 200mV to VDDIO_BANK35 above the default 500mV
 +
# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35 above the default 500mV
 +
# Jumper on 11-12 -> adds 50mV to VDDIO_BANK35 above the default 500mV
 +
 
 +
The DEFAULT configuration is VDDIO_BANK35 @ 1.8V (500mV + 800mV + 400mV + 100mV):
 +
# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above the default 500mV
 +
# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35
 +
# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35
 +
 
 +
Please note that:
 +
* By default VDDIO_BANK35 is supplied by VADJ Regulator
 +
 
 +
=== VADJ VDDIO selector - JP28 ===
 +
JP28 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector:
 +
 
 +
{| class="wikitable"
 +
|-
 +
!Pin#
 +
!Pin name
 +
!Function
 +
!Notes
 +
|-
 +
|2 || VADJ_FB (22K)|| selects 3.3V VADJ || -
 +
|-
 +
|4 || VADJ_FB (30K9)|| selects 2.5V VADJ || -
 +
|-
 +
|6 || VADJ_FB (51K1)|| selects 1.8V VADJ || -
 +
|-
 +
|8 || VADJ_FB (68K)|| selects 1.5V VADJ || -
 +
|-
 +
|10 || VADJ_FB (100K)|| selects 1.2V VADJ || -
 +
|-
 +
|12 || RFU|| Reserved || -
 +
|-
 +
|1, 3, 5, 7, 9, 11 || DGND|| - || -
 +
|-
 +
|}
 +
 
 +
The jumper configurations are:
 +
# Jumper on 1-2 -> supply VADJ with 3.3V
 +
# Jumper on 3-4 -> supply VADJ with 2.5V
 +
# Jumper on 5-6 -> supply VADJ with 1.8V
 +
# Jumper on 7-8 -> supply VADJ with 1.5V
 +
# Jumper on 9-10 -> supply VADJ with 1.2V
 +
 
 +
The DEFAULT configuration is:
 +
# Jumper on 5-6 -> supply VADJ with 1.8V
 +
 
 
=== JTAG ===
 
=== JTAG ===
  
Line 292: Line 336:
 
* 2.54mm-pitch 10x2 header (ARM standard): http://www2.lauterbach.com/pdf/arm_app_jtag.pdf
 
* 2.54mm-pitch 10x2 header (ARM standard): http://www2.lauterbach.com/pdf/arm_app_jtag.pdf
 
* This port is connected to Zynq's native JTAG signals. Please note that Zynq's internal JTAG chain supports differents configurations, depending on bootstrap signals. In case split mode is selected, CPU JTAG can be routed separately via PL. For more details please refer to Zynq Technical Reference Manual.
 
* This port is connected to Zynq's native JTAG signals. Please note that Zynq's internal JTAG chain supports differents configurations, depending on bootstrap signals. In case split mode is selected, CPU JTAG can be routed separately via PL. For more details please refer to Zynq Technical Reference Manual.
−
* JTAG on BORA Xpress EVB is also connected to the FMC connector. For more details on how to connect JTAG on a custom FMC card please refer to ANSI/VITA FPGA Mezzanine Card (FMC) Standard.
+
* JTAG on Bora Xpress EVB is also connected to the FMC connector. For more details on how to connect JTAG on a custom FMC card please refer to ANSI/VITA FPGA Mezzanine Card (FMC) Standard.
  
 
==== JTAG XILINX - J13 ====
 
==== JTAG XILINX - J13 ====
Line 350: Line 394:
 
|-
 
|-
 
|}
 
|}
−
<section end=JTAG/>
 
  
−
<section begin=Console/>
 
 
=== UART1 - J17 ===
 
=== UART1 - J17 ===
  
Line 390: Line 432:
 
|-
 
|-
 
|}
 
|}
−
<section end=Console/>
 
  
−
<section begin=USB OTG/>
 
 
=== USB OTG - J19 ===
 
=== USB OTG - J19 ===
  
−
J19 is a standard USB MICRO AB connector. It is connected to the BORA Xpress USB 2.0 OTG peripheral. The following table reports the pinout of the connector:
+
J19 is a standard USB MICRO AB connector. It is connected to the Bora Xpress USB 2.0 OTG peripheral. The following table reports the pinout of the connector:
  
 
{| class="wikitable"  
 
{| class="wikitable"  
Line 417: Line 457:
 
|-
 
|-
 
|}
 
|}
−
<section end=USB OTG/>
 
  
−
<section begin=micro SD/>
 
 
=== MicroSD - J21 ===
 
=== MicroSD - J21 ===
  
−
J21 is a microSD memory card connector. It is connected to the BORA Xpress SOM through a bidirectional 1.8V/3.3V voltage-level translator mounted on the BORA Xpress EVB. Level shifter is required because MIO signals are 1.8V. The following table reports the pinout of the connector:
+
J21 is a microSD memory card connector. It is connected to the Bora Xpress SOM through a bidirectional 1.8V/3.3V voltage-level translator mounted on the Bora Xpress EVB. Level shifter is required because MIO signals are 1.8V. The following table reports the pinout of the connector:
  
 
{| class="wikitable"  
 
{| class="wikitable"  
Line 447: Line 485:
 
|8 ||PS_SD0_DAT1||| - || -
 
|8 ||PS_SD0_DAT1||| - || -
 
|-
 
|-
−
| 13 |3.3V||| - ||  ||Pull up to 3.3V with 10K Ohm -
+
|13 |3.3V||| - ||  ||Pull up to 3.3V with 10K Ohm -
 
|-
 
|-
 
|}
 
|}
−
<section end=micro SD/>
 
  
−
<section begin=DWM/>
 
 
=== DWM (DAVE Wifi/BT module) socket - J23 ===
 
=== DWM (DAVE Wifi/BT module) socket - J23 ===
−
J23 is a 52991-0308 connector type (30 pins, vertical, 0.50mm picth). This socket connects the [[DWM_ADD-ON | DWM Wireless Module]] (optional) to the BORA Xpress EVB. The following table reports the pinout of the connector:
+
J23 is a 52991-0308 connector type (30 pins, vertical, 0.50mm picth). This socket connects the [[Wireless_Module_(DWM) | DWM Wireless Module]] (optional) to the Bora Xpress EVB. The following table reports the pinout of the connector:
  
 
{| class="wikitable"  
 
{| class="wikitable"  
Line 502: Line 538:
 
|-
 
|-
 
|}
 
|}
−
<section end=DWM/>
 
−
 
−
<section begin=CAN/>
 
  
 
=== CAN - J24 ===
 
=== CAN - J24 ===
−
J24 is a 10-pin 5x2x2.54mm pitch vertical header directly connected to BORA Xpress SoM's transceiver for the CAN interface. This 2.5mm-pitch header is compatible with commonly available IDC-10/DB9 flat cables. The following table reports the pinout of the connector:
+
J24 is a 10-pin 5x2x2.54mm pitch vertical header directly connected to Bora Xpress SoM's transceiver for the CAN interface. This 2.5mm-pitch header is compatible with commonly available IDC-10/DB9 flat cables. The following table reports the pinout of the connector:
  
 
{| class="wikitable"  
 
{| class="wikitable"  
Line 525: Line 558:
 
|-
 
|-
 
|}
 
|}
−
<section end=CAN/>
+
 
−
<section begin=Touchscreen/>
 
 
=== Touch screen - J25===
 
=== Touch screen - J25===
−
J25 is a ZIF 4-pin 1.0mm pitch connector that connects the touchscreen drive lines to the touch screen controller on the BoORA Xpress EVB. The following table reports the pinout of the connector:
+
J25 is a ZIF 4-pin 1.0mm pitch connector that connects the touchscreen drive lines to the touch screen controller on the Bora Xpress EVB. The following table reports the pinout of the connector:
  
 
{| class="wikitable"  
 
{| class="wikitable"  
Line 546: Line 578:
 
|-
 
|-
 
|}
 
|}
−
<section end=Touchscreen/>
+
 
−
<section begin=LVDS/>
 
 
=== LVDS - J26 ===
 
=== LVDS - J26 ===
 
J26 is a vertical double row straight 20-pin 1.25mm pitch header. This interface shows how to implement a differential connection to an LCD screen. As known, Zynq does not implement an LCD controller, however this can be integrated in FPGA fabric as shown by this example: https://wiki.analog.com/resources/tools-software/linux-drivers/platforms/zynq. The following table reports the pinout of the connector:
 
J26 is a vertical double row straight 20-pin 1.25mm pitch header. This interface shows how to implement a differential connection to an LCD screen. As known, Zynq does not implement an LCD controller, however this can be integrated in FPGA fabric as shown by this example: https://wiki.analog.com/resources/tools-software/linux-drivers/platforms/zynq. The following table reports the pinout of the connector:
Line 573: Line 604:
 
|-
 
|-
 
|12 ||LCD_LVDS_D2+ || - || -
 
|12 ||LCD_LVDS_D2+ || - || -
−
|-
 
−
|14 ||LCD_LVDS_CLK- || - || -
 
 
|-
 
|-
 
|15 ||LCD_LVDS_CLK+ || - || -
 
|15 ||LCD_LVDS_CLK+ || - || -
Line 586: Line 615:
 
|21,22 ||DGND || Ground || Shield
 
|21,22 ||DGND || Ground || Shield
 
|-
 
|-
−
|}
 
−
<section end=LVDS/>
 
−
<section begin=FMC/>
 
−
=== FPGA Mezzanine Card (FMC) Connector - J27 ===
 
−
J27 is a 400 pins ANSI/VITA 57.1-2008 FPGA Mezzanine Card Connector that allows to connect to standard I/O mezzanine cards.
 
−
 
−
Please note that BoraXpress EVB FMC Connector is:
 
−
* fully compliant to FMC LPC
 
−
* partially compliant to FMC HPC because HPC side is not fully populated.
 
−
 
−
The following tables detail how BORA Xpress signals have been routed to FMC connector. At this [[:File:BoraXEVB-FMC-routing.zip|link]] a spreadsheet providing the same information is available for download.
 
−
 
−
For more information about I/O voltage of single-ended signals available on FMC connector, please refer to [[#PL's I/O voltage selections|this section]].
 
−
 
−
==== HPC Row A ====
 
−
 
−
{| class="wikitable"
 
−
|-
 
−
!Pin#
 
−
!Pin name
 
−
!Function
 
−
!Notes
 
−
|-
 
−
| A1||DGND||GND||
 
−
|-
 
−
| A2||MGTxRXP1||DP1_M2C_P||
 
−
|-
 
−
| A3||MGTxRXN1||DP1_M2C_N||
 
−
|-
 
−
| A4||DGND||GND||
 
−
|-
 
−
| A5||DGND||GND||
 
−
|-
 
−
| A6||MGTxRXP2||DP2_M2C_P||
 
−
|-
 
−
| A7||MGTxRXN2||DP2_M2C_N||
 
−
|-
 
−
| A8||DGND||GND||
 
−
|-
 
−
| A9||DGND||GND||
 
−
|-
 
−
| A10||MGTxRXP3||DP3_M2C_P||
 
−
|-
 
−
| A11||MGTxRXN3||DP3_M2C_N||
 
−
|-
 
−
| A12||DGND||GND||
 
−
|-
 
−
| A13||DGND||GND||
 
−
|-
 
−
| A14||<span style="color:#ff0000">not connected</span>||DP4_M2C_P||
 
−
|-
 
−
| A15||<span style="color:#ff0000">not connected</span>||DP4_M2C_N||
 
−
|-
 
−
| A16||DGND||GND||
 
−
|-
 
−
| A17||DGND||GND||
 
−
|-
 
−
| A18||<span style="color:#ff0000">not connected</span>||DP5_M2C_P||
 
−
|-
 
−
| A19||<span style="color:#ff0000">not connected</span>||DP5_M2C_N||
 
−
|-
 
−
| A20||DGND||GND||
 
−
|-
 
−
| A21||DGND||GND||
 
−
|-
 
−
| A22||MGTxTXP1||DP1_C2M_P||
 
−
|-
 
−
| A23||MGTxTXN1||DP1_C2M_N||
 
−
|-
 
−
| A24||DGND||GND||
 
−
|-
 
−
| A25||DGND||GND||
 
−
|-
 
−
| A26||MGTxTXP2||DP2_C2M_P||
 
−
|-
 
−
| A27||MGTxTXN2||DP2_C2M_N||
 
−
|-
 
−
| A28||DGND||GND||
 
−
|-
 
−
| A29||DGND||GND||
 
−
|-
 
−
| A30||MGTxTXP3||DP3_C2M_P||
 
−
|-
 
−
| A31||MGTxTXN3||DP3_C2M_N||
 
−
|-
 
−
| A32||DGND||GND||
 
−
|-
 
−
| A33||DGND||GND||
 
−
|-
 
−
| A34||<span style="color:#ff0000">not connected</span>||DP4_C2M_P||
 
−
|-
 
−
| A35||<span style="color:#ff0000">not connected</span>||DP4_C2M_N||
 
−
|-
 
−
| A36||DGND||GND||
 
−
|-
 
−
| A37||DGND||GND||
 
−
|-
 
−
| A38||<span style="color:#ff0000">not connected</span>||DP5_C2M_P||
 
−
|-
 
−
| A39||<span style="color:#ff0000">not connected</span>||DP5_C2M_N||
 
−
|-
 
−
| A40||DGND||GND||
 
−
|}
 
−
 
−
==== HPC Row B ====
 
−
 
−
{| class="wikitable"
 
−
|-
 
−
!Pin#
 
−
!Pin name
 
−
!Function
 
−
!Notes
 
−
|-
 
−
| B1||RSVD||RES1||
 
−
|-
 
−
| B2||DGND||GND||
 
−
|-
 
−
| B3||DGND||GND||
 
−
|-
 
−
| B4||<span style="color:#ff0000">not connected</span>||DP9_M2C_P||
 
−
|-
 
−
| B5||<span style="color:#ff0000">not connected</span>||DP9_M2C_N||
 
−
|-
 
−
| B6||DGND||GND||
 
−
|-
 
−
| B7||DGND||GND||
 
−
|-
 
−
| B8||<span style="color:#ff0000">not connected</span>||DP8_M2C_P||
 
−
|-
 
−
| B9||<span style="color:#ff0000">not connected</span>||DP8_M2C_N||
 
−
|-
 
−
| B10||DGND||GND||
 
−
|-
 
−
| B11||DGND||GND||
 
−
|-
 
−
| B12||<span style="color:#ff0000">not connected</span>||DP7_M2C_P||
 
−
|-
 
−
| B13||<span style="color:#ff0000">not connected</span>||DP7_M2C_N||
 
−
|-
 
−
| B14||DGND||GND||
 
−
|-
 
−
| B15||DGND||GND||
 
−
|-
 
−
| B16||<span style="color:#ff0000">not connected</span>||DP6_M2C_P||
 
−
|-
 
−
| B17||<span style="color:#ff0000">not connected</span>||DP6_M2C_N||
 
−
|-
 
−
| B18||DGND||GND||
 
−
|-
 
−
| B19||DGND||GND||
 
−
|-
 
−
| B20||MGTREFCLK1P||GBTCLK1_M2C_P||
 
−
|-
 
−
| B21||MGTREFCLK1N||GBTCLK1_M2C_N||
 
−
|-
 
−
| B22||DGND||GND||
 
−
|-
 
−
| B23||DGND||GND||
 
−
|-
 
−
| B24||<span style="color:#ff0000">not connected</span>||DP9_C2M_P||
 
−
|-
 
−
| B25||<span style="color:#ff0000">not connected</span>||DP9_C2M_N||
 
−
|-
 
−
| B26||DGND||GND||
 
−
|-
 
−
| B27||DGND||GND||
 
−
|-
 
−
| B28||<span style="color:#ff0000">not connected</span>||DP8_C2M_P||
 
−
|-
 
−
| B29||<span style="color:#ff0000">not connected</span>||DP8_C2M_N||
 
−
|-
 
−
| B30||DGND||GND||
 
−
|-
 
−
| B31||DGND||GND||
 
−
|-
 
−
| B32||<span style="color:#ff0000">not connected</span>||DP7_C2M_P||
 
−
|-
 
−
| B33||<span style="color:#ff0000">not connected</span>||DP7_C2M_N||
 
−
|-
 
−
| B34||DGND||GND||
 
−
|-
 
−
| B35||DGND||GND||
 
−
|-
 
−
| B36||<span style="color:#ff0000">not connected</span>||DP6_C2M_P||
 
−
|-
 
−
| B37||<span style="color:#ff0000">not connected</span>||DP6_C2M_N||
 
−
|-
 
−
| B38||DGND||GND||
 
−
|-
 
−
| B39||DGND||GND||
 
−
|-
 
−
| B40||RSVD||RES0||
 
−
|}
 
−
 
−
==== LPC Row C ====
 
−
 
−
{| class="wikitable"
 
−
|-
 
−
!Pin#
 
−
!Pin name
 
−
!Function
 
−
!Notes
 
−
|-
 
−
| C1||DGND||GND||
 
−
|-
 
−
| C2||MGTxTXP0||DP0_C2M_P||
 
−
|-
 
−
| C3||MGTxTXN0||DP0_C2M_N||
 
−
|-
 
−
| C4||DGND||GND||
 
−
|-
 
−
| C5||DGND||GND||
 
−
|-
 
−
| C6||MGTxRXP0||DP0_M2C_P||
 
−
|-
 
−
| C7||MGTxRXN0||DP0_M2C_N||
 
−
|-
 
−
| C8||DGND||GND||
 
−
|-
 
−
| C9||DGND||GND||
 
−
|-
 
−
| C10||IO_L23P_T3_34||LA06_P||
 
−
|-
 
−
| C11||IO_L23N_T3_34||LA06_N||
 
−
|-
 
−
| C12||DGND||GND||
 
−
|-
 
−
| C13||DGND||GND||
 
−
|-
 
−
| C14||IO_L2P_T0_34||LA10_P||
 
−
|-
 
−
| C15||IO_L2N_T0_34||LA10_N||
 
−
|-
 
−
| C16||DGND||GND||
 
−
|-
 
−
| C17||DGND||GND||
 
−
|-
 
−
| C18||IO_L1P_T0_34||LA14_P||
 
−
|-
 
−
| C19||IO_L1N_T0_34||LA14_N||
 
−
|-
 
−
| C20||DGND||GND||
 
−
|-
 
−
| C21||DGND||GND||
 
−
|-
 
−
| C22||IO_L16P_T2_34||LA18_P_CC||
 
−
|-
 
−
| C23||IO_L16N_T2_34||LA18_N_CC||
 
−
|-
 
−
| C24||DGND||GND||
 
−
|-
 
−
| C25||DGND||GND||
 
−
|-
 
−
| C26||IO_L6P_T0_35||LA27_P||
 
−
|-
 
−
| C27||IO_L6N_T0_VREF_35||LA27_N||
 
−
|-
 
−
| C28||DGND||GND||
 
−
|-
 
−
| C29||DGND||GND||
 
−
|-
 
−
| C30||I2C0_SCL||SCL||
 
−
|-
 
−
| C31||I2C0_SDA||SDA||
 
−
|-
 
−
| C32||DGND||GND||
 
−
|-
 
−
| C33||DGND||GND||
 
−
|-
 
−
| C34||GA0||GA0||
 
−
|-
 
−
| C35||FMC_12P0V||12P0V||
 
−
|-
 
−
| C36||DGND||GND||
 
−
|-
 
−
| C37||FMC_12P0V||12P0V||
 
−
|-
 
−
| C38||DGND||GND||
 
−
|-
 
−
| C39||FMC_3P3V||3P3V||
 
−
|-
 
−
| C40||DGND||GND||
 
−
|}
 
−
 
−
==== LPC Row D ====
 
−
 
−
{| class="wikitable"
 
−
|-
 
−
!Pin#
 
−
!Pin name
 
−
!Function
 
−
!Notes
 
−
|-
 
−
| D1||IO_25_VRP_34||PG_C2M||
 
−
|-
 
−
| D2||DGND||GND||
 
−
|-
 
−
| D3||DGND||GND||
 
−
|-
 
−
| D4||MGTREFCLK0P||GBTCLK0_M2C_P||
 
−
|-
 
−
| D5||MGTREFCLK0N||GBTCLK0_M2C_N||
 
−
|-
 
−
| D6||DGND||GND||
 
−
|-
 
−
| D7||DGND||GND||
 
−
|-
 
−
| D8||IO_L14P_T2_SRCC_34||LA01_P_CC||
 
−
|-
 
−
| D9||IO_L14N_T2_SRCC_34||LA01_N_CC||
 
−
|-
 
−
| D10||DGND||GND||
 
−
|-
 
−
| D11||IO_L9P_T1_DQS_34||LA05_P||
 
−
|-
 
−
| D12||IO_L9N_T1_DQS_34||LA05_N||
 
−
|-
 
−
| D13||DGND||GND||
 
−
|-
 
−
| D14||IO_L6P_T0_34||LA09_P||
 
−
|-
 
−
| D15||IO_L6N_T0_VREF_34||LA09_N||
 
−
|-
 
−
| D16||DGND||GND||
 
−
|-
 
−
| D17||IO_L20P_T3_34||LA13_P||
 
−
|-
 
−
| D18||IO_L20N_T3_34||LA13_N||
 
−
|-
 
−
| D19||DGND||GND||
 
−
|-
 
−
| D20||IO_L15P_T2_DQS_34||LA17_P_CC||
 
−
|-
 
−
| D21||IO_L15N_T2_DQS_34||LA17_N_CC||
 
−
|-
 
−
| D22||DGND||GND||
 
−
|-
 
−
| D23||IO_L2P_T0_AD8P_35||LA23_P||
 
−
|-
 
−
| D24||IO_L2N_T0_AD8N_35||LA23_N||
 
−
|-
 
−
| D25||DGND||GND||
 
−
|-
 
−
| D26||IO_L5P_T0_AD9P_35||LA26_P||
 
−
|-
 
−
| D27||IO_L5N_T0_AD9N_35||LA26_N||
 
−
|-
 
−
| D28||DGND||GND||
 
−
|-
 
−
| D29||JTAG_TCK||TCK||
 
−
|-
 
−
| D30||JTAG_TDI||TDI||
 
−
|-
 
−
| D31||FMC_TDO_ZYNQ_TDI||TDO||
 
−
|-
 
−
| D32||FMC_3P3VAUX||3P3VAUX||
 
−
|-
 
−
| D33||JTAG_TMS||TMS||
 
−
|-
 
−
| D34||JTAG_TRSTn||TRST_L||
 
−
|-
 
−
| D35||GA0||GA1||
 
−
|-
 
−
| D36||FMC_3P3V||3P3V||
 
−
|-
 
−
| D37||DGND||GND||
 
−
|-
 
−
| D38||FMC_3P3V||3P3V||
 
−
|-
 
−
| D39||DGND||GND||
 
−
|-
 
−
| D40||FMC_3P3V||3P3V||
 
−
|}
 
−
 
−
==== HPC Row E ====
 
−
 
−
{| class="wikitable"
 
−
|-
 
−
!Pin#
 
−
!Pin name
 
−
!Function
 
−
!Notes
 
−
|-
 
−
| E1||DGND||GND||
 
−
|-
 
−
| E2||IO_L14P_T2_AD4P_SRCC_35||HA01_P_CC||
 
−
|-
 
−
| E3||IO_L14N_T2_AD4N_SRCC_35||HA01_N_CC||
 
−
|-
 
−
| E4||DGND||GND||
 
−
|-
 
−
| E5||DGND||GND||
 
−
|-
 
−
| E6||IO_L20P_T3_AD6P_35||HA05_P||
 
−
|-
 
−
| E7||IO_L20N_T3_AD6N_35||HA05_N||
 
−
|-
 
−
| E8||DGND||GND||
 
−
|-
 
−
| E9||IO_L24P_T3_AD15P_35||HA09_P||
 
−
|-
 
−
| E10||IO_L24N_T3_AD15N_35||HA09_N||
 
−
|-
 
−
| E11||DGND||GND||
 
−
|-
 
−
| E12||<span style="color:#ff0000">not connected</span>||HA13_P||
 
−
|-
 
−
| E13||<span style="color:#ff0000">not connected</span>||HA13_N||
 
−
|-
 
−
| E14||DGND||GND||
 
−
|-
 
−
| E15||<span style="color:#ff0000">not connected</span>||HA16_P||
 
−
|-
 
−
| E16||<span style="color:#ff0000">not connected</span>||HA16_N||
 
−
|-
 
−
| E17||DGND||GND||
 
−
|-
 
−
| E18||<span style="color:#ff0000">not connected</span>||HA20_P||
 
−
|-
 
−
| E19||<span style="color:#ff0000">not connected</span>||HA20_N||
 
−
|-
 
−
| E20||DGND||GND||
 
−
|-
 
−
| E21||<span style="color:#ff0000">not connected</span>||HB03_P||
 
−
|-
 
−
| E22||<span style="color:#ff0000">not connected</span>||HB03_N||
 
−
|-
 
−
| E23||DGND||GND||
 
−
|-
 
−
| E24||<span style="color:#ff0000">not connected</span>||HB05_P||
 
−
|-
 
−
| E25||<span style="color:#ff0000">not connected</span>||HB05_N||
 
−
|-
 
−
| E26||DGND||GND||
 
−
|-
 
−
| E27||<span style="color:#ff0000">not connected</span>||HB09_P||
 
−
|-
 
−
| E28||<span style="color:#ff0000">not connected</span>||HB09_N||
 
−
|-
 
−
| E29||DGND||GND||
 
−
|-
 
−
| E30||<span style="color:#ff0000">not connected</span>||HB13_P||
 
−
|-
 
−
| E31||<span style="color:#ff0000">not connected</span>||HB13_N||
 
−
|-
 
−
| E32||DGND||GND||
 
−
|-
 
−
| E33||<span style="color:#ff0000">not connected</span>||HB19_P||
 
−
|-
 
−
| E34||<span style="color:#ff0000">not connected</span>||HB19_N||
 
−
|-
 
−
| E35||DGND||GND||
 
−
|-
 
−
| E36||<span style="color:#ff0000">not connected</span>||HB21_P||
 
−
|-
 
−
| E37||<span style="color:#ff0000">not connected</span>||HB21_N||
 
−
|-
 
−
| E38||DGND||GND||
 
−
|-
 
−
| E39||FMC_VADJ||VADJ||
 
−
|-
 
−
| E40||DGND||GND||
 
 
|}
 
|}
  
−
==== HPC Row F ====
 
−
 
−
{| class="wikitable"
 
−
|-
 
−
!Pin#
 
−
!Pin name
 
−
!Function
 
−
!Notes
 
−
|-
 
−
| F1||IO_0_VRN_35||PG_M2C||
 
−
|-
 
−
| F2||DGND||GND||
 
−
|-
 
−
| F3||DGND||GND||
 
−
|-
 
−
| F4||IO_L13P_T2_MRCC_35||HA00_P_CC||
 
−
|-
 
−
| F5||IO_L13N_T2_MRCC_35||HA00_N_CC||
 
−
|-
 
−
| F6||DGND||GND||
 
−
|-
 
−
| F7||IO_L19P_T3_35||HA04_P||
 
−
|-
 
−
| F8||IO_L19N_T3_VREF_35||HA04_N||
 
−
|-
 
−
| F9||DGND||GND||
 
−
|-
 
−
| F10||IO_L23P_T3_35||HA08_P||
 
−
|-
 
−
| F11||IO_L23N_T3_35||HA08_N||
 
−
|-
 
−
| F12||DGND||GND||
 
−
|-
 
−
| F13||<span style="color:#ff0000">not connected</span>||HA12_P||
 
−
|-
 
−
| F14||<span style="color:#ff0000">not connected</span>||HA12_N||
 
−
|-
 
−
| F15||DGND||GND||
 
−
|-
 
−
| F16||<span style="color:#ff0000">not connected</span>||HA15_P||
 
−
|-
 
−
| F17||<span style="color:#ff0000">not connected</span>||HA15_N||
 
−
|-
 
−
| F18||DGND||GND||
 
−
|-
 
−
| F19||<span style="color:#ff0000">not connected</span>||HA19_P||
 
−
|-
 
−
| F20||<span style="color:#ff0000">not connected</span>||HA19_N||
 
−
|-
 
−
| F21||DGND||GND||
 
−
|-
 
−
| F22||<span style="color:#ff0000">not connected</span>||HB02_P||
 
−
|-
 
−
| F23||<span style="color:#ff0000">not connected</span>||HB02_N||
 
−
|-
 
−
| F24||DGND||GND||
 
−
|-
 
−
| F25||<span style="color:#ff0000">not connected</span>||HB04_P||
 
−
|-
 
−
| F26||<span style="color:#ff0000">not connected</span>||HB04_N||
 
−
|-
 
−
| F27||DGND||GND||
 
−
|-
 
−
| F28||<span style="color:#ff0000">not connected</span>||HB08_P||
 
−
|-
 
−
| F29||<span style="color:#ff0000">not connected</span>||HB08_N||
 
−
|-
 
−
| F30||DGND||GND||
 
−
|-
 
−
| F31||<span style="color:#ff0000">not connected</span>||HB12_P||
 
−
|-
 
−
| F32||<span style="color:#ff0000">not connected</span>||HB12_N||
 
−
|-
 
−
| F33||DGND||GND||
 
−
|-
 
−
| F34||<span style="color:#ff0000">not connected</span>||HB16_P||
 
−
|-
 
−
| F35||<span style="color:#ff0000">not connected</span>||HB16_N||
 
−
|-
 
−
| F36||DGND||GND||
 
−
|-
 
−
| F37||<span style="color:#ff0000">not connected</span>||HB20_P||
 
−
|-
 
−
| F38||<span style="color:#ff0000">not connected</span>||HB20_N||
 
−
|-
 
−
| F39||DGND||GND||
 
−
|-
 
−
| F40||FMC_VADJ||VADJ||
 
−
|}
 
−
 
−
==== LPC Row G ====
 
−
 
−
{| class="wikitable"
 
−
|-
 
−
!Pin#
 
−
!Pin name
 
−
!Function
 
−
!Notes
 
−
|-
 
−
| G1||DGND||GND||
 
−
|-
 
−
| G2||IO_L11P_T1_SRCC_34||CLK0_C2M_P||
 
−
|-
 
−
| G3||IO_L11N_T1_SRCC_34||CLK0_C2M_N||
 
−
|-
 
−
| G4||DGND||GND||
 
−
|-
 
−
| G5||DGND||GND||
 
−
|-
 
−
| G6||IO_L13P_T1_MRCC_34||LA00_P_CC||
 
−
|-
 
−
| G7||IO_L13N_T1_MRCC_34||LA00_N_CC||
 
−
|-
 
−
| G8||DGND||GND||
 
−
|-
 
−
| G9||IO_L4P_T0_34||LA03_P||
 
−
|-
 
−
| G10||IO_L4N_T0_34||LA03_N||
 
−
|-
 
−
| G11||DGND||GND||
 
−
|-
 
−
| G12||IO_L3P_T0_DQS_PUDC_B_34||LA08_P||
 
−
|-
 
−
| G13||IO_L3N_T0_DQS_34||LA08_N||
 
−
|-
 
−
| G14||DGND||GND||
 
−
|-
 
−
| G15||IO_L22P_T3_34||LA12_P||
 
−
|-
 
−
| G16||IO_L22N_T3_34||LA12_N||
 
−
|-
 
−
| G17||DGND||GND||
 
−
|-
 
−
| G18||IO_L19P_T3_34||LA16_P||
 
−
|-
 
−
| G19||IO_L19N_T3_VREF_34||LA16_N||
 
−
|-
 
−
| G20||DGND||GND||
 
−
|-
 
−
| G21||IO_L17P_T2_34||LA20_P||
 
−
|-
 
−
| G22||IO_L17N_T2_34||LA20_N||
 
−
|-
 
−
| G23||DGND||GND||
 
−
|-
 
−
| G24||IO_L1P_T0_AD0P_35||LA22_P||
 
−
|-
 
−
| G25||IO_L1N_T0_AD0N_35||LA22_N||
 
−
|-
 
−
| G26||DGND||GND||
 
−
|-
 
−
| G27||IO_L4P_T0_35||LA25_P||
 
−
|-
 
−
| G28||IO_L4N_T0_35||LA25_N||
 
−
|-
 
−
| G29||DGND||GND||
 
−
|-
 
−
| G30||IO_L8P_T1_AD10P_35||LA29_P||
 
−
|-
 
−
| G31||IO_L8N_T1_AD10N_35||LA29_N||
 
−
|-
 
−
| G32||DGND||GND||
 
−
|-
 
−
| G33||IO_L10P_T1_AD11P_35||LA31_P||
 
−
|-
 
−
| G34||IO_L10N_T1_AD11N_35||LA31_N||
 
−
|-
 
−
| G35||DGND||GND||
 
−
|-
 
−
| G36||IO_L16P_T2_35||LA33_P||
 
−
|-
 
−
| G37||IO_L16N_T2_35||LA33_N||
 
−
|-
 
−
| G38||DGND||GND||
 
−
|-
 
−
| G39||FMC_VADJ||VADJ||
 
−
|-
 
−
| G40||DGND||GND||
 
−
|}
 
−
 
−
==== LPC Row H ====
 
−
 
−
{| class="wikitable"
 
−
|-
 
−
!Pin#
 
−
!Pin name
 
−
!Function
 
−
!Notes
 
−
|-
 
−
| H1||FMC_VREF_A_M2C||VREF_A_M2C||
 
−
|-
 
−
| H2||FMC_PRSNT_M2C_L||PRSNT_M2C_L||
 
−
|-
 
−
| H3||DGND||GND||
 
−
|-
 
−
| H4||IO_L12P_T1_MRCC_34||CLK0_M2C_P||
 
−
|-
 
−
| H5||IO_L12N_T1_MRCC_34||CLK0_M2C_N||
 
−
|-
 
−
| H6||DGND||GND||
 
−
|-
 
−
| H7||IO_L7P_T1_34||LA02_P||
 
−
|-
 
−
| H8||IO_L7N_T1_34||LA02_N||
 
−
|-
 
−
| H9||DGND||GND||
 
−
|-
 
−
| H10||IO_L5P_T0_34||LA04_P||
 
−
|-
 
−
| H11||IO_L5N_T0_34||LA04_N||
 
−
|-
 
−
| H12||DGND||GND||
 
−
|-
 
−
| H13||IO_L8P_T1_34||LA07_P||
 
−
|-
 
−
| H14||IO_L8N_T1_34||LA07_N||
 
−
|-
 
−
| H15||DGND||GND||
 
−
|-
 
−
| H16||IO_L21P_T3_DQS_34||LA11_P||
 
−
|-
 
−
| H17||IO_L21N_T3_DQS_34||LA11_N||
 
−
|-
 
−
| H18||DGND||GND||
 
−
|-
 
−
| H19||IO_L18P_T2_34||LA15_P||
 
−
|-
 
−
| H20||IO_L18N_T2_34||LA15_N||
 
−
|-
 
−
| H21||DGND||GND||
 
−
|-
 
−
| H22||IO_L24P_T3_34||LA19_P||
 
−
|-
 
−
| H23||IO_L24N_T3_34||LA19_N||
 
−
|-
 
−
| H24||DGND||GND||
 
−
|-
 
−
| H25||IO_L10P_T1_34||LA21_P||
 
−
|-
 
−
| H26||IO_L10N_T1_34||LA21_N||
 
−
|-
 
−
| H27||DGND||GND||
 
−
|-
 
−
| H28||IO_L3P_T0_DQS_AD1P_35||LA24_P||
 
−
|-
 
−
| H29||IO_L3N_T0_DQS_AD1N_35||LA24_N||
 
−
|-
 
−
| H30||DGND||GND||
 
−
|-
 
−
| H31||IO_L7P_T1_AD2P_35||LA28_P||
 
−
|-
 
−
| H32||IO_L7N_T1_AD2N_35||LA28_N||
 
−
|-
 
−
| H33||DGND||GND||
 
−
|-
 
−
| H34||IO_L9P_T1_DQS_AD3P_35||LA30_P||
 
−
|-
 
−
| H35||IO_L9N_T1_DQS_AD3N_35||LA30_N||
 
−
|-
 
−
| H36||DGND||GND||
 
−
|-
 
−
| H37||IO_L15P_T2_DQS_AD12P_35||LA32_P||
 
−
|-
 
−
| H38||IO_L15N_T2_DQS_AD12N_35||LA32_N||
 
−
|-
 
−
| H39||DGND||GND||
 
−
|-
 
−
| H40||FMC_VADJ||VADJ||
 
−
|}
 
−
 
−
==== HPC Row J ====
 
−
 
−
{| class="wikitable"
 
−
|-
 
−
!Pin#
 
−
!Pin name
 
−
!Function
 
−
!Notes
 
−
|-
 
−
| J1||DGND||GND||
 
−
|-
 
−
| J2||IO_L11P_T1_SRCC_35||CLK1_C2M_P||
 
−
|-
 
−
| J3||IO_L11N_T1_SRCC_35||CLK1_C2M_N||
 
−
|-
 
−
| J4||DGND||GND||
 
−
|-
 
−
| J5||DGND||GND||
 
−
|-
 
−
| J6||IO_L18P_T2_AD13P_35||HA03_P||
 
−
|-
 
−
| J7||IO_L18N_T2_AD13N_35||HA03_N||
 
−
|-
 
−
| J8||DGND||GND||
 
−
|-
 
−
| J9||IO_L22P_T3_AD7P_35||HA07_P||
 
−
|-
 
−
| J10||IO_L22N_T3_AD7N_35||HA07_N||
 
−
|-
 
−
| J11||DGND||GND||
 
−
|-
 
−
| J12||<span style="color:#ff0000">not connected</span>||HA11_P||
 
−
|-
 
−
| J13||<span style="color:#ff0000">not connected</span>||HA11_N||
 
−
|-
 
−
| J14||DGND||GND||
 
−
|-
 
−
| J15||<span style="color:#ff0000">not connected</span>||HA14_P||
 
−
|-
 
−
| J16||<span style="color:#ff0000">not connected</span>||HA14_N||
 
−
|-
 
−
| J17||DGND||GND||
 
−
|-
 
−
| J18||<span style="color:#ff0000">not connected</span>||HA18_P||
 
−
|-
 
−
| J19||<span style="color:#ff0000">not connected</span>||HA18_N||
 
−
|-
 
−
| J20||DGND||GND||
 
−
|-
 
−
| J21||<span style="color:#ff0000">not connected</span>||HA22_P||
 
−
|-
 
−
| J22||<span style="color:#ff0000">not connected</span>||HA22_N||
 
−
|-
 
−
| J23||DGND||GND||
 
−
|-
 
−
| J24||<span style="color:#ff0000">not connected</span>||HB01_P||
 
−
|-
 
−
| J25||<span style="color:#ff0000">not connected</span>||HB01_N||
 
−
|-
 
−
| J26||DGND||GND||
 
−
|-
 
−
| J27||<span style="color:#ff0000">not connected</span>||HB07_P||
 
−
|-
 
−
| J28||<span style="color:#ff0000">not connected</span>||HB07_N||
 
−
|-
 
−
| J29||DGND||GND||
 
−
|-
 
−
| J30||<span style="color:#ff0000">not connected</span>||HB11_P||
 
−
|-
 
−
| J31||<span style="color:#ff0000">not connected</span>||HB11_N||
 
−
|-
 
−
| J32||DGND||GND||
 
−
|-
 
−
| J33||<span style="color:#ff0000">not connected</span>||HB15_P||
 
−
|-
 
−
| J34||<span style="color:#ff0000">not connected</span>||HB15_N||
 
−
|-
 
−
| J35||DGND||GND||
 
−
|-
 
−
| J36||<span style="color:#ff0000">not connected</span>||HB18_P||
 
−
|-
 
−
| J37||<span style="color:#ff0000">not connected</span>||HB18_N||
 
−
|-
 
−
| J38||DGND||GND||
 
−
|-
 
−
| J39||<span style="color:#ff0000">not connected</span>||VIO_B_M2C||
 
−
|-
 
−
| J40||DGND||GND||
 
−
|}
 
−
 
−
==== HPC Row K ====
 
−
 
−
{| class="wikitable"
 
−
|-
 
−
!Pin#
 
−
!Pin name
 
−
!Function
 
−
!Notes
 
−
|-
 
−
| K1||<span style="color:#ff0000">not connected</span>||VREF_B_M2C||
 
−
|-
 
−
| K2||DGND||GND||
 
−
|-
 
−
| K3||DGND||GND||
 
−
|-
 
−
| K4||IO_L12P_T1_MRCC_35||CLK1_M2C_P||
 
−
|-
 
−
| K5||IO_L12N_T1_MRCC_35||CLK1_M2C_N||
 
−
|-
 
−
| K6||DGND||GND||
 
−
|-
 
−
| K7||IO_L17P_T2_AD5P_35||HA02_P||
 
−
|-
 
−
| K8||IO_L17N_T2_AD5N_35||HA02_N||
 
−
|-
 
−
| K9||DGND||GND||
 
−
|-
 
−
| K10||IO_L21P_T3_DQS_AD14P_35||HA06_P||
 
−
|-
 
−
| K11||IO_L21N_T3_DQS_AD14N_35||HA06_N||
 
−
|-
 
−
| K12||DGND||GND||
 
−
|-
 
−
| K13||IO_25_VRP_35||HA10_P||
 
−
|-
 
−
| K14||<span style="color:#ff0000">not connected</span>||HA10_N||
 
−
|-
 
−
| K15||DGND||GND||
 
−
|-
 
−
| K16||<span style="color:#ff0000">not connected</span>||HA17_P_CC||
 
−
|-
 
−
| K17||<span style="color:#ff0000">not connected</span>||HA17_N_CC||
 
−
|-
 
−
| K18||DGND||GND||
 
−
|-
 
−
| K19||<span style="color:#ff0000">not connected</span>||HA21_P||
 
−
|-
 
−
| K20||<span style="color:#ff0000">not connected</span>||HA21_N||
 
−
|-
 
−
| K21||DGND||GND||
 
−
|-
 
−
| K22||<span style="color:#ff0000">not connected</span>||HA23_P||
 
−
|-
 
−
| K23||<span style="color:#ff0000">not connected</span>||HA23_N||
 
−
|-
 
−
| K24||DGND||GND||
 
−
|-
 
−
| K25||<span style="color:#ff0000">not connected</span>||HB00_P_CC||
 
−
|-
 
−
| K26||<span style="color:#ff0000">not connected</span>||HB00_N_CC||
 
−
|-
 
−
| K27||DGND||GND||
 
−
|-
 
−
| K28||<span style="color:#ff0000">not connected</span>||HB06_P_CC||
 
−
|-
 
−
| K29||<span style="color:#ff0000">not connected</span>||HB06_N_CC||
 
−
|-
 
−
| K30||DGND||GND||
 
−
|-
 
−
| K31||<span style="color:#ff0000">not connected</span>||HB10_P||
 
−
|-
 
−
| K32||<span style="color:#ff0000">not connected</span>||HB10_N||
 
−
|-
 
−
| K33||DGND||GND||
 
−
|-
 
−
| K34||<span style="color:#ff0000">not connected</span>||HB14_P||
 
−
|-
 
−
| K35||<span style="color:#ff0000">not connected</span>||HB14_N||
 
−
|-
 
−
| K36||DGND||GND||
 
−
|-
 
−
| K37||<span style="color:#ff0000">not connected</span>||HB17_P_CC||
 
−
|-
 
−
| K38||<span style="color:#ff0000">not connected</span>||HB17_N_CC||
 
−
|-
 
−
| K39||DGND||GND||
 
−
|-
 
−
| K40||<span style="color:#ff0000">not connected</span>||VIO_B_M2C||
 
−
|}
 
−
<section end=FMC/>
 
−
<section begin=PinStrip/>
 
 
=== Pin strip connectors ===
 
=== Pin strip connectors ===
  
Line 1,576: Line 692:
 
|-
 
|-
 
|}
 
|}
 +
  
 
==== Ethernet GPIO - JP18 ====
 
==== Ethernet GPIO - JP18 ====
Line 1,612: Line 729:
 
|-
 
|-
 
|}
 
|}
 +
  
 
==== SPI,NAND - JP19 ====
 
==== SPI,NAND - JP19 ====
Line 1,645: Line 763:
 
|}
 
|}
  
−
<section begin=RTC/>
 
−
<section end=PinStrip/>
 
 
==== FPGA, WatchDog, RTC, RST - JP22 ====
 
==== FPGA, WatchDog, RTC, RST - JP22 ====
 
JP22 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
 
JP22 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:
Line 1,688: Line 804:
 
|-
 
|-
 
|}
 
|}
−
<section end=RTC/>
 
  
 
==== AUX PINs - JP29 ====
 
==== AUX PINs - JP29 ====
Line 1,733: Line 848:
 
** Silicon Labs Si571 programmable clock generator: this clock si connected to PL to allow the user to easily experiment his/her own peripherals and IPs on FPGA
 
** Silicon Labs Si571 programmable clock generator: this clock si connected to PL to allow the user to easily experiment his/her own peripherals and IPs on FPGA
 
** resistive touch screen controller for LCD screen
 
** resistive touch screen controller for LCD screen
−
** consumption monitor: this is connected to shunt resistor put in series on BORA power rail, allowing to measure SoM consumption
+
** consumption monitor: this is connected to shunt resistor put in series on Bora power rail, allowing to measure SoM consumption
  
 
==== ADC - JP30, JP31, JP32 ====
 
==== ADC - JP30, JP31, JP32 ====
Line 1,839: Line 954:
 
|}
 
|}
  
−
<section begin=PMOD/>
 
 
=== Digilent Pmod™ Compatible headers ===
 
=== Digilent Pmod™ Compatible headers ===
  
Line 1,880: Line 994:
 
|-
 
|-
 
|}
 
|}
 +
  
 
==== Digilent Pmod™ Compatible - JP23 ====
 
==== Digilent Pmod™ Compatible - JP23 ====
Line 1,911: Line 1,026:
 
|-
 
|-
 
|}
 
|}
−
<section end=PMOD/>
 
−
 
−
===JP27 and JP28===
 
−
These connectors allow to select power voltage of PL's I/O banks. For more details please refer to [[#PL's I/O voltage selections|this section]].
 
−
 
−
==PL's I/O voltage selections==
 
−
<section begin=Voltage selections/>
 
−
PL's I/O banks voltage can be selected via configuration jumpers. It is worth remembering that:
 
−
*'''each bank must be powered even if none of its I/Os is used'''
 
−
*'''voltage selection must be done before powering up the board'''.
 
−
 
−
The following table recaps the characteristics of the PL's I/O banks, in terms of allowable power supplies.
 
−
 
−
{| class="wikitable" style="text-align: center;"
 
−
! rowspan="2" |SoM
 
−
! rowspan="2" style="text-align: center; font-weight: bold;" | Zynq p/n
 
−
! colspan="2" style="text-align: center; font-weight: bold;" | Bank #34
 
−
! colspan="2" style="text-align: center; font-weight: bold;" | Bank #13
 
−
! colspan="2" style="text-align: center; font-weight: bold;" | Bank #35
 
−
|-
 
−
| style="text-align: center; font-weight: bold;" | Type [1]
 
−
| style="text-align: center; font-weight: bold;" | I/O voltage setting
 
−
| style="text-align: center; font-weight: bold;" | Type [1]
 
−
| style="text-align: center; font-weight: bold;" | I/O voltage setting
 
−
| style="text-align: center; font-weight: bold;" | Type [1]
 
−
| style="text-align: center; font-weight: bold;" | I/O voltage setting
 
−
|-
 
−
| rowspan="2" |BoraX
 
−
| style="text-align: center;" | 7015
 
−
(CLG485 package)
 
−
| style="text-align: center;" | HR
 
−
(1.2 - 3.3V)
 
−
| style="text-align: center;" | User defined
 
−
| style="text-align: center;" | HR
 
−
(1.2 - 3.3V)
 
−
| style="text-align: center;" | User defined
 
−
| style="text-align: center;" | HR
 
−
(1.2 - 3.3V)
 
−
| style="text-align: center;" | User defined
 
−
|-
 
−
| style="text-align: center;" | 7030
 
−
(SBG485 package)
 
−
| style="text-align: center;" | HP
 
−
(1.2 - 1.8V)
 
−
| style="text-align: center;" | User defined
 
−
| style="text-align: center;" | HR
 
−
(1.2 - 3.3V)
 
−
| style="text-align: center;" | User defined
 
−
| style="text-align: center;" | HP
 
−
(1.2 - 1.8V)
 
−
| style="text-align: center;" | User defined
 
−
|-
 
−
| rowspan="2" |Bora Lite
 
−
| style="text-align: center;" | 7007S/7010
 
−
(CLG400 package)
 
−
| style="text-align: center;" | HR
 
−
(1.2 - 3.3V)
 
−
| style="text-align: center;" | User defined
 
−
| style="text-align: center;" | HR
 
−
(1.2 - 3.3V)
 
−
| style="text-align: center;" | User defined
 
−
| style="text-align: center;" | HR
 
−
(1.2 - 3.3V)
 
−
| style="text-align: center;" | User defined
 
−
|-
 
−
| style="text-align: center;" | 7014S/7020
 
−
(CLG400 package)
 
−
| style="text-align: center;" | HR
 
−
(1.2 - 3.3V)
 
−
| style="text-align: center;" | User defined
 
−
| style="text-align: center;" | HR
 
−
(1.2 - 3.3V)
 
−
| style="text-align: center;" | User defined
 
−
| style="text-align: center;" | HR
 
−
(1.2 - 3.3V)
 
−
| style="text-align: center;" | User defined
 
−
|}
 
−
[1]
 
−
*HR = High Range
 
−
*HP = High Performance
 
−
 
−
===BoraXEVB voltage selection jumpers===
 
−
BoraXEVB provides several configuration jumpers that allow to easily select the voltages used for PL's I/O banks. The following tables lists some of the allowed combinations used to select the most common voltage values. There are other combination available. However, '''some of them are not allowed and may cause permanent hardware damages to the Zynq part'''.
 
−
 
−
Since characteristics of PL's I/O banks differ between Zynq 7015 and 7030 parts, the valid combinations '''are not the same for all of the BoraX models'''. Please refer to the following sections for more details.
 
−
 
−
Even if PL's banks are independent, default configuration of BoraXEVB is such that
 
−
*bank 34 and bank 35 have the same supply voltage
 
−
*this voltage is selected via JP28.
 
−
This configuration is in accordance with default routing of signals used for FMC connector.
 
−
====Examples of valid combinations for Zynq 7030-based SOMs (default option for BXELK)====
 
−
{| class="wikitable" style="text-align: center;"
 
−
|+Bank #13 (HR)
 
−
|-
 
−
! style="text-align: center; font-weight: bold;" | Nominal voltage [V]
 
−
! style="text-align: center; font-weight: bold;" | JP25.1-2
 
−
! style="text-align: center; font-weight: bold;" | JP25.3-4
 
−
! style="text-align: center; font-weight: bold;" | JP25.5-6
 
−
! style="text-align: center; font-weight: bold;" | JP25.7-8
 
−
! style="text-align: center; font-weight: bold;" | JP25.9-10
 
−
! style="text-align: center; font-weight: bold;" | JP25.11-12
 
−
|-
 
−
| style="text-align: center;" | 1.2
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
|-
 
−
| style="text-align: center;" | 1.5
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
|-
 
−
| style="text-align: center;" | 1.8
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
|-
 
−
| style="text-align: center;" | 2.5
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
|-
 
−
| style="text-align: center;" | 3.3
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
|}
 
−
 
−
{| class="wikitable" style="text-align: center;"
 
−
|+Bank #35 (HP)
 
−
|-
 
−
! style="text-align: center; font-weight: bold;" | Nominal voltage [V]
 
−
! style="text-align: center; font-weight: bold;" | JP27.1-2
 
−
! style="text-align: center; font-weight: bold;" | JP27.3-4
 
−
! style="text-align: center; font-weight: bold;" | JP27.5-6
 
−
! style="text-align: center; font-weight: bold;" | JP27.7-8
 
−
! style="text-align: center; font-weight: bold;" | JP27.9-10
 
−
! style="text-align: center; font-weight: bold;" | JP27.11-12
 
−
|-
 
−
| style="text-align: center;" | 1.2
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
|-
 
−
| style="text-align: center;" | 1.5
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
|-
 
−
| style="text-align: center;" | 1.8
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
|}
 
−
 
−
{| class="wikitable" style="text-align: center;"
 
−
|+Bank #34 (HP)
 
−
|-
 
−
! style="text-align: center; font-weight: bold;" | Nominal voltage [V]
 
−
! style="text-align: center; font-weight: bold;" | JP28.1-2
 
−
! style="text-align: center; font-weight: bold;" | JP28.3-4
 
−
! style="text-align: center; font-weight: bold;" | JP28.5-6
 
−
! style="text-align: center; font-weight: bold;" | JP28.7-8
 
−
! style="text-align: center; font-weight: bold;" | JP28.9-10
 
−
! style="text-align: center; font-weight: bold;" | JP28.11-12
 
−
|-
 
−
| style="text-align: center;" | 1.2
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
|-
 
−
| style="text-align: center;" | 1.5
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
|-
 
−
| style="text-align: center;" | 1.8
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
|}
 
−
 
−
====Examples of valid combinations for Zynq 7015-based SOMs====
 
−
{| class="wikitable" style="text-align: center;"
 
−
|+Bank #13 (HR)
 
−
|-
 
−
! style="text-align: center; font-weight: bold;" | Nominal voltage [V]
 
−
! style="text-align: center; font-weight: bold;" | JP25.1-2
 
−
! style="text-align: center; font-weight: bold;" | JP25.3-4
 
−
! style="text-align: center; font-weight: bold;" | JP25.5-6
 
−
! style="text-align: center; font-weight: bold;" | JP25.7-8
 
−
! style="text-align: center; font-weight: bold;" | JP25.9-10
 
−
! style="text-align: center; font-weight: bold;" | JP25.11-12
 
−
|-
 
−
| style="text-align: center;" | 1.2
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
|-
 
−
| style="text-align: center;" | 1.5
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
|-
 
−
| style="text-align: center;" | 1.8
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
|-
 
−
| style="text-align: center;" | 2.5
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
|-
 
−
| style="text-align: center;" | 3.3
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
|}
 
−
 
−
{| class="wikitable" style="text-align: center;"
 
−
|+Bank #35 (HR)
 
−
|-
 
−
! style="text-align: center; font-weight: bold;" | Nominal voltage [V]
 
−
! style="text-align: center; font-weight: bold;" | JP27.1-2
 
−
! style="text-align: center; font-weight: bold;" | JP27.3-4
 
−
! style="text-align: center; font-weight: bold;" | JP27.5-6
 
−
! style="text-align: center; font-weight: bold;" | JP27.7-8
 
−
! style="text-align: center; font-weight: bold;" | JP27.9-10
 
−
! style="text-align: center; font-weight: bold;" | JP27.11-12
 
−
|-
 
−
| style="text-align: center;" | 1.2
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
|-
 
−
| style="text-align: center;" | 1.5
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
|-
 
−
| style="text-align: center;" | 1.8
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
|-
 
−
| style="text-align: center;" | 2.5
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
|-
 
−
| style="text-align: center;" | 3.3
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
 
−
|}
 
−
 
−
{| class="wikitable" style="text-align: center;"
 
−
|+Bank #34 (HR)
 
−
|-
 
−
! style="text-align: center; font-weight: bold;" | Nominal voltage [V]
 
−
! style="text-align: center; font-weight: bold;" | JP28.1-2
 
−
! style="text-align: center; font-weight: bold;" | JP28.3-4
 
−
! style="text-align: center; font-weight: bold;" | JP28.5-6
 
−
! style="text-align: center; font-weight: bold;" | JP28.7-8
 
−
! style="text-align: center; font-weight: bold;" | JP28.9-10
 
−
! style="text-align: center; font-weight: bold;" | JP28.11-12
 
−
|-
 
−
| style="text-align: center;" | 1.2
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
|-
 
−
| style="text-align: center;" | 1.5
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
|-
 
−
| style="text-align: center;" | 1.8
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
|-
 
−
| style="text-align: center;" | 2.5
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
|-
 
−
| style="text-align: center;" | 3.3
 
−
| style="text-align: center;" | '''closed'''
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
| style="text-align: center;" | open
 
−
|}
 
−
 
−
====Advanced information about voltage selection connectors====
 
−
===== Bank 13 VDDIO selection connector (JP25) =====
 
−
JP25 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector:
 
−
 
−
{| class="wikitable"
 
−
|-
 
−
!Pin#
 
−
!Pin name
 
−
!Function
 
−
!Notes
 
−
|-
 
−
|2 || LDO_B13_1V6|| adds +1.6V to VDDIO_BANK13 || -
 
−
|-
 
−
|4 || LDO_B13_800mV|| adds +800mV to VDDIO_BANK13 || -
 
−
|-
 
−
|6 || LDO_B13_400mV|| adds +400mV to VDDIO_BANK13 || -
 
−
|-
 
−
|8 || LDO_B13_200mV|| adds +200mV to VDDIO_BANK13 || -
 
−
|-
 
−
|10 || LDO_B13_100mV|| adds +100mV to VDDIO_BANK13 || -
 
−
|-
 
−
|12 || LDO_B13_50mV|| adds +50mV to VDDIO_BANK13 || -
 
−
|-
 
−
|1, 3, 5, 7, 9, 11 || DGND|| - || -
 
−
|-
 
−
|}
 
−
 
−
The jumper configurations are:
 
−
# No jumpers installed -> DC output for VDDIO_BANK13 is 500mV
 
−
# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK13 above the default 500mV
 
−
# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV
 
−
# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13 above the default 500mV
 
−
# Jumper on 7-8 -> adds 200mV to VDDIO_BANK13 above the default 500mV
 
−
# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13 above the default 500mV
 
−
# Jumper on 11-12 -> adds 50mV to VDDIO_BANK13 above the default 500mV
 
−
 
−
The default configuration is VDDIO_BANK13 @ 1.8V (500mV + 800mV + 400mV + 100mV):
 
−
# Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV
 
−
# Jumper on 5-6 -> adds 400mV to VDDIO_BANK13
 
−
# Jumper on 9-10 -> adds 100mV to VDDIO_BANK13
 
−
 
−
===== Bank 35 VDDIO selection connector (JP27) =====
 
−
JP27 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector:
 
−
 
−
{| class="wikitable"
 
−
|-
 
−
!Pin#
 
−
!Pin name
 
−
!Function
 
−
!Notes
 
−
|-
 
−
|2 || LDO_B35_1V6|| adds +1.6V to VDDIO_BANK35 || -
 
−
|-
 
−
|4 || LDO_B35_800mV|| adds +800mV to VDDIO_BANK35 || -
 
−
|-
 
−
|6 || LDO_B35_400mV|| adds +400mV to VDDIO_BANK35 || -
 
−
|-
 
−
|8 || LDO_B35_200mV|| adds +200mV to VDDIO_BANK35 || -
 
−
|-
 
−
|10 || LDO_B35_100mV|| adds +100mV to VDDIO_BANK35 || -
 
−
|-
 
−
|12 || LDO_B35_50mV|| adds +50mV to VDDIO_BANK35 || -
 
−
|-
 
−
|1, 3, 5, 7, 9, 11 || DGND|| - || -
 
−
|-
 
−
|}
 
−
 
−
The jumper configurations are:
 
−
# No jumpers installed -> DC output for VDDIO_BANK35 is 500mV
 
−
# Jumper on 1-2 -> adds 1.6V to VDDIO_BANK35 above the default 500mV
 
−
# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above the default 500mV
 
−
# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35 above the default 500mV
 
−
# Jumper on 7-8 -> adds 200mV to VDDIO_BANK35 above the default 500mV
 
−
# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35 above the default 500mV
 
−
# Jumper on 11-12 -> adds 50mV to VDDIO_BANK35 above the default 500mV
 
−
 
−
The DEFAULT configuration is VDDIO_BANK35 @ 1.8V (500mV + 800mV + 400mV + 100mV):
 
−
# Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above the default 500mV
 
−
# Jumper on 5-6 -> adds 400mV to VDDIO_BANK35
 
−
# Jumper on 9-10 -> adds 100mV to VDDIO_BANK35
 
−
 
−
{{ImportantMessage|text=Please note that by default VDDIO_BANK35 is supplied by VADJ Regulator. For using a dedicated VDDIO_BANK35, it is required to remove R343 and mount R344: check BORA Xpress Evaluation Kit schematics page 10.<br>
 
−
Then, check and/or properly configure JP27 for selecting the required VDDIO_BANK35}}
 
−
 
−
===== Bank 34 and VADJ VDDIO selection connector (JP28) =====
 
−
JP28 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector:
 
−
 
−
{| class="wikitable"
 
−
|-
 
−
!Pin#
 
−
!Pin name
 
−
!Function
 
−
!Notes
 
−
|-
 
−
|2 || VADJ_FB (22K)|| selects 3.3V VADJ || -
 
−
|-
 
−
|4 || VADJ_FB (30K9)|| selects 2.5V VADJ || -
 
−
|-
 
−
|6 || VADJ_FB (51K1)|| selects 1.8V VADJ || -
 
−
|-
 
−
|8 || VADJ_FB (68K)|| selects 1.5V VADJ || -
 
−
|-
 
−
|10 || VADJ_FB (100K)|| selects 1.2V VADJ || -
 
−
|-
 
−
|12 || RFU|| Reserved || -
 
−
|-
 
−
|1, 3, 5, 7, 9, 11 || DGND|| - || -
 
−
|-
 
−
|}
 
−
 
−
The jumper configurations are:
 
−
# Jumper on 1-2 -> supply VADJ with 3.3V
 
−
# Jumper on 3-4 -> supply VADJ with 2.5V
 
−
# Jumper on 5-6 -> supply VADJ with 1.8V
 
−
# Jumper on 7-8 -> supply VADJ with 1.5V
 
−
# Jumper on 9-10 -> supply VADJ with 1.2V
 
−
 
−
The default configuration is:
 
−
# Jumper on 5-6 -> supply VADJ with 1.8V
 
−
<section end=Voltage selections/>
 
−
 
−
<section begin=SOM/>
 
−
 
−
==SoM's signals mapping==
 
−
===Bora Lite===
 
−
As known, Bora Lite requires an [[BoraLite_Adapter_for_the_BoraXEVB_carrier_board|adapter]] to be mounted on the BoraXEVB carrier board. The adapter swap some signals to allow to use some carrier board peripherals routed on unavailable pins of the SoM. For this reason, it can be tricky to find out where the SoM's signals are routed at the carrier board level. The following table details such routing for PL banks. Here '''it is assumed to use an adapter with default mounting options'''.
 
−
 
−
{| class="wikitable"
 
−
|+
 
−
! colspan="2" |SoM's signal
 
−
! colspan="6" |Routing options at carrier board level
 
−
|-
 
−
! rowspan="2" |Bank
 
−
! rowspan="2" |Name
 
−
! colspan="3" |Option #1
 
−
(default)
 
−
! colspan="3" |Option #2
 
−
|-
 
−
!Name
 
−
!Pin
 
−
!Note
 
−
!Name
 
−
!Pin
 
−
!Note
 
−
|-
 
−
| rowspan="54" |34
 
−
| rowspan="2" |IO_0_34
 
−
| rowspan="2" |'''IO_0_VRN_34'''
 
−
|J31.2
 
−
|Header
 
−
| rowspan="2" |
 
−
| rowspan="2" |
 
−
| rowspan="2" |
 
−
|-
 
−
|J27D.H2
 
−
|FMC conn.
 
−
|-
 
−
| rowspan="2" |IO_25_34
 
−
| rowspan="2" |'''IO_25_VRP_35'''
 
−
|J31.4
 
−
|Header
 
−
| rowspan="2" |
 
−
| rowspan="2" |
 
−
| rowspan="2" |
 
−
|-
 
−
|J27B.D1
 
−
|FMC conn.
 
−
|-
 
−
|IO_L10N_T1_34
 
−
|IO_L10N_T1_34
 
−
|J27D.H26
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L10P_T1_34
 
−
|IO_L10P_T1_34
 
−
|J27D.H25
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L11N_T1_SRCC_34
 
−
|IO_L11N_T1_SRCC_34
 
−
|J27D.G3
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L11P_T1_SRCC_34
 
−
|IO_L11P_T1_SRCC_34
 
−
|J27D.G2
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L12N_T1_MRCC_34
 
−
|IO_L12N_T1_MRCC_34
 
−
|J27D.H5
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L12P_T1_MRCC_34
 
−
|IO_L12P_T1_MRCC_34
 
−
|J27D.H4
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L13N_T2_MRCC_34
 
−
|'''IO_L13N_T1_MRCC_34'''
 
−
|J27D.G7
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L13P_T2_MRCC_34
 
−
|'''IO_L13P_T1_MRCC_34'''
 
−
|J27D.G6
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L14N_T2_SRCC_34
 
−
|IO_L14N_T2_SRCC_34
 
−
|J27B.D9
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L14P_T2_SRCC_34
 
−
|IO_L14P_T2_SRCC_34
 
−
|J27B.D8
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L15N_T2_DQS_34
 
−
|IO_L15N_T2_DQS_34
 
−
|J27B.D21
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L15P_T2_DQS_34
 
−
|IO_L15P_T2_DQS_34
 
−
|J27B.D20
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L16N_T2_34
 
−
|IO_L16N_T2_34
 
−
|J27B.C23
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L16P_T2_34
 
−
|IO_L16P_T2_34
 
−
|J27B.C22
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L17N_T2_34
 
−
|IO_L17N_T2_34
 
−
|J27D.G22
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L17P_T2_34
 
−
|IO_L17P_T2_34
 
−
|J27D.G21
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L18N_T2_34
 
−
|IO_L18N_T2_34
 
−
|J27D.H20
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L18P_T2_34
 
−
|IO_L18P_T2_34
 
−
|J27D.H19
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
| rowspan="2" |IO_L19N_T3_VREF_34
 
−
| rowspan="2" |IO_L19N_T3_VREF_34
 
−
|J27D.G19
 
−
|FMC conn.
 
−
| rowspan="2" |
 
−
| rowspan="2" |
 
−
| rowspan="2" |
 
−
|-
 
−
|TP21
 
−
|TP SMD
 
−
|-
 
−
|IO_L19P_T3_34
 
−
|n/a
 
−
|n/a
 
−
|At the adapter level, this signal (as CAN_RX) is connected to a CAN transceiver. The CAN bus is available at J24.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L1N_T0_34
 
−
|IO_L1N_T0_34
 
−
|J27B.C19
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L1P_T0_34
 
−
|IO_L1P_T0_34
 
−
|J27B.C18
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L20N_T3_34
 
−
|IO_L20N_T3_34
 
−
|J27B.D18
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L20P_T3_34
 
−
|IO_L20P_T3_34
 
−
|J27B.D17
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L21N_T3_DQS_34
 
−
|IO_L21N_T3_DQS_34
 
−
|J27D.H17
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L21P_T3_DQS_34
 
−
|IO_L21P_T3_DQS_34
 
−
|J27D.H16
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L22N_T3_34
 
−
|IO_L22N_T3_34
 
−
|J27D.G16
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L22P_T3_34
 
−
|IO_L22P_T3_34
 
−
|J27D.G15
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L23N_T3_34
 
−
|IO_L23N_T3_34
 
−
|J27B.C11
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L23P_T3_34
 
−
|IO_L23P_T3_34
 
−
|J27B.C10
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L24N_T3_34
 
−
|IO_L24N_T3_34
 
−
|J27D.H23
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L24P_T3_34
 
−
|IO_L24P_T3_34
 
−
|J27D.H22
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L2N_T0_34
 
−
|IO_L2N_T0_34
 
−
|J27B.C15
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L2P_T0_34
 
−
|IO_L2P_T0_34
 
−
|J27B.C14
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L3N_T0_DQS_34
 
−
|IO_L3N_T0_DQS_34
 
−
|J27D.G13
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L3P_T0_DQS_PUDC_B_34
 
−
(10K pull-up on SoM)
 
−
|IO_L3P_T0_DQS_PUDC_B_34
 
−
|J27D.G12
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L4N_T0_34
 
−
|IO_L4N_T0_34
 
−
|J27D.G10
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L4P_T0_34
 
−
|IO_L4P_T0_34
 
−
|J27D.G9
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L5N_T0_34
 
−
|IO_L5N_T0_34
 
−
|J27D.H11
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L5P_T0_34
 
−
|IO_L5P_T0_34
 
−
|J27D.H10
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
| rowspan="2" |IO_L6N_T0_VREF_34
 
−
| rowspan="2" |IO_L6N_T0_VREF_34
 
−
|J27B.D15
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|TP22
 
−
|TP SMD
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L6P_T0_34
 
−
|n/a
 
−
|n/a
 
−
|At the adapter level, this signal (as CAN_TX) is connected to a CAN transceiver. The CAN bus is available at J24.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L7N_T1_34
 
−
|IO_L7N_T1_34
 
−
|J27D.H8
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L7P_T1_34
 
−
|IO_L7P_T1_34
 
−
|J27D.H7
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L8N_T1_34
 
−
|IO_L8N_T1_34
 
−
|J27D.H14
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L8P_T1_34
 
−
|IO_L8P_T1_34
 
−
|J27D.H13
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L9N_T1_DQS_34
 
−
|IO_L9N_T1_DQS_34
 
−
|J27B.D12
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L9P_T1_DQS_34
 
−
|IO_L9P_T1_DQS_34
 
−
|J27B.D11
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
| rowspan="54" |35
 
−
| rowspan="2" |IO_0_35
 
−
| rowspan="2" |'''IO_0_VRN_35'''
 
−
|J27C.F1
 
−
|FMC conn.
 
−
| rowspan="2" |
 
−
| rowspan="2" |
 
−
| rowspan="2" |
 
−
|-
 
−
|J31.1
 
−
|Header
 
−
|-
 
−
| rowspan="2" |IO_25_35
 
−
| rowspan="2" |'''IO_25_VRP_35'''
 
−
|J27E.K13
 
−
|FMC conn.
 
−
| rowspan="2" |
 
−
| rowspan="2" |
 
−
| rowspan="2" |
 
−
|-
 
−
|J31.3
 
−
|Header
 
−
|-
 
−
|IO_L10N_T1_AD11N_35
 
−
|IO_L10N_T1_AD11N_35
 
−
|J27D.G34
 
−
|FMC conn.
 
−
|FPGA_BANK35_AD11N
 
−
|JP32.3
 
−
|Header
 
−
|-
 
−
|IO_L10P_T1_AD11P_35
 
−
|IO_L10P_T1_AD11P_35
 
−
|J27D.G33
 
−
|FMC conn.
 
−
|FPGA_BANK35_AD11P
 
−
|JP32.1
 
−
|Header
 
−
|-
 
−
|IO_L11N_T1_SRCC_35
 
−
|IO_L11N_T1_SRCC_35
 
−
|J27E.J3
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L11P_T1_SRCC_35
 
−
|IO_L11P_T1_SRCC_35
 
−
|J27E.J2
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L12N_T1_MRCC_35
 
−
|IO_L12N_T1_MRCC_35
 
−
|J27E.K5
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L12P_T1_MRCC_35
 
−
|IO_L12P_T1_MRCC_35
 
−
|J27E.K4
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L13N_T2_MRCC_35
 
−
|IO_L13N_T2_MRCC_35
 
−
|J27C.F5
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L13P_T2_MRCC_35
 
−
|IO_L13P_T2_MRCC_35
 
−
|J27C.F4
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L14N_T2_AD4N_SRCC_35
 
−
|IO_L14N_T2_AD4N_SRCC_35
 
−
|J27C.E3
 
−
|FMC conn.
 
−
|FPGA_BANK35_AD4N
 
−
|JP30.16
 
−
|Header
 
−
|-
 
−
|IO_L14P_T2_AD4P_SRCC_35
 
−
|IO_L14P_T2_AD4P_SRCC_35
 
−
|J27C.E2
 
−
|FMC conn.
 
−
|FPGA_BANK35_AD4P
 
−
|JP30.14
 
−
|Header
 
−
|-
 
−
|IO_L15N_T2_DQS_AD12N_35
 
−
|IO_L15N_T2_DQS_AD12N_35
 
−
|J27D.H38
 
−
|FMC conn.
 
−
|FPGA_BANK35_AD12N
 
−
|JP32.8
 
−
|Header
 
−
|-
 
−
|IO_L15P_T2_DQS_AD12P_35
 
−
|IO_L15P_T2_DQS_AD12P_35
 
−
|J27D.H37
 
−
|FMC conn.
 
−
|FPGA_BANK35_AD12P
 
−
|JP32.6
 
−
|Header
 
−
|-
 
−
|IO_L16N_T2_35
 
−
|IO_L16N_T2_35
 
−
|J27D.G37
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L16P_T2_35
 
−
|IO_L16P_T2_35
 
−
|J27D.G36
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L17N_T2_AD5N_35
 
−
|IO_L17N_T2_AD5N_35
 
−
|J27E.K8
 
−
|FMC conn.
 
−
|FPGA_BANK35_AD5N
 
−
|JP31.1
 
−
|Header
 
−
|-
 
−
|IO_L17P_T2_AD5P_35
 
−
|IO_L17P_T2_AD5P_35
 
−
|J27E.K7
 
−
|FMC conn.
 
−
|FPGA_BANK35_AD5P
 
−
|JP30.15
 
−
|Header
 
−
|-
 
−
|IO_L18N_T2_AD13N_35
 
−
|IO_L18N_T2_AD13N_35
 
−
|J27E.J7
 
−
|FMC conn.
 
−
|FPGA_BANK35_AD13N
 
−
|JP32.9
 
−
|Header
 
−
|-
 
−
|IO_L18P_T2_AD13P_35
 
−
|IO_L18P_T2_AD13P_35
 
−
|J27E.J6
 
−
|FMC conn.
 
−
|FPGA_BANK35_AD13P
 
−
|JP32.7
 
−
|Header
 
−
|-
 
−
| rowspan="2" |IO_L19N_T3_VREF_35
 
−
| rowspan="2" |IO_L19N_T3_VREF_35
 
−
|J27C.F8
 
−
|FMC conn.
 
−
| rowspan="2" |
 
−
| rowspan="2" |
 
−
| rowspan="2" |
 
−
|-
 
−
|TP24
 
−
|TP SMD
 
−
|-
 
−
|IO_L19P_T3_35
 
−
|IO_L19P_T3_35
 
−
|J27C.F7
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L1N_T0_AD0N_35
 
−
|IO_L1N_T0_AD0N_35
 
−
|J27D.G25
 
−
|FMC conn.
 
−
|FPGA_BANK35_AD0P
 
−
|JP30.4
 
−
|Header
 
−
|-
 
−
|IO_L1P_T0_AD0P_35
 
−
|IO_L1P_T0_AD0P_35
 
−
|J27D.G24
 
−
|FMC conn.
 
−
|FPGA_BANK35_AD0N
 
−
|JP30.2
 
−
|Header
 
−
|-
 
−
|IO_L20N_T3_AD6N_35
 
−
|IO_L20N_T3_AD6N_35
 
−
|J27C.E7
 
−
|FMC conn.
 
−
|FPGA_BANK35_AD6N
 
−
|JP31.6
 
−
|Header
 
−
|-
 
−
|IO_L20P_T3_AD6P_35
 
−
|IO_L20P_T3_AD6P_35
 
−
|J27C.E6
 
−
|FMC conn.
 
−
|FPGA_BANK35_AD6P
 
−
|JP31.4
 
−
|Header
 
−
|-
 
−
|IO_L21N_T3_DQS_AD14N_35
 
−
|IO_L21N_T3_DQS_AD14N_35
 
−
|J27E.K11
 
−
|FMC conn.
 
−
|FPGA_BANK35_AD14N
 
−
|JP32.14
 
−
|Header
 
−
|-
 
−
|IO_L21P_T3_DQS_AD14P_35
 
−
|IO_L21P_T3_DQS_AD14P_35
 
−
|J27E.K10
 
−
|FMC conn.
 
−
|FPGA_BANK35_AD14P
 
−
|JP32.12
 
−
|Header
 
−
|-
 
−
|IO_L22N_T3_AD7N_35
 
−
|IO_L22N_T3_AD7N_35
 
−
|J27E.J10
 
−
|FMC conn.
 
−
|FPGA_BANK35_AD7N
 
−
|JP31.7
 
−
|Header
 
−
|-
 
−
|IO_L22P_T3_AD7P_35
 
−
|IO_L22P_T3_AD7P_35
 
−
|J27E.J9
 
−
|FMC conn.
 
−
|FPGA_BANK35_AD7P
 
−
|JP31.5
 
−
|Header
 
−
|-
 
−
|IO_L23N_T3_35
 
−
|IO_L23N_T3_35
 
−
|J27C.F11
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L23P_T3_35
 
−
|IO_L23P_T3_35
 
−
|J27C.F10
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L24N_T3_AD15N_35
 
−
|IO_L24N_T3_AD15N_35
 
−
|J27C.E10
 
−
|FMC conn.
 
−
|FPGA_BANK35_AD15N
 
−
|JP32.15
 
−
|Header
 
−
|-
 
−
|IO_L24P_T3_AD15P_35
 
−
|IO_L24P_T3_AD15P_35
 
−
|J27C.E9
 
−
|FMC conn.
 
−
|FPGA_BANK35_AD15P
 
−
|JP32.13
 
−
|Header
 
−
|-
 
−
|IO_L2N_T0_AD8N_35
 
−
|IO_L2N_T0_AD8N_35
 
−
|J27B.D24
 
−
|FMC conn.
 
−
|FPGA_BANK35_AD8N
 
−
|JP31.12
 
−
|Header
 
−
|-
 
−
|IO_L2P_T0_AD8P_35
 
−
|IO_L2P_T0_AD8P_35
 
−
|J27B.D23
 
−
|FMC conn.
 
−
|FPGA_BANK35_AD8P
 
−
|JP31.10
 
−
|Header
 
−
|-
 
−
|IO_L3N_T0_DQS_AD1N_35
 
−
|IO_L3N_T0_DQS_AD1N_35
 
−
|J27D.H29
 
−
|FMC conn.
 
−
|FPGA_BANK35_AD1N
 
−
|JP30.5
 
−
|Header
 
−
|-
 
−
|IO_L3P_T0_DQS_AD1P_35
 
−
|IO_L3P_T0_DQS_AD1P_35
 
−
|J27D.H28
 
−
|FMC conn.
 
−
|FPGA_BANK35_AD1P
 
−
|JP30.3
 
−
|Header
 
−
|-
 
−
|IO_L4N_T0_35
 
−
|IO_L4N_T0_35
 
−
|J27D.G28
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L4P_T0_35
 
−
|IO_L4P_T0_35
 
−
|J27D.G27
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L5N_T0_AD9N_35
 
−
|IO_L5N_T0_AD9N_35
 
−
|J27B.D27
 
−
|FMC conn.
 
−
|FPGA_BANK35_AD9N
 
−
|JP31.13
 
−
|Header
 
−
|-
 
−
|IO_L5P_T0_AD9P_35
 
−
|IO_L5P_T0_AD9P_35
 
−
|J27B.D26
 
−
|FMC conn.
 
−
|FPGA_BANK35_AD9P
 
−
|JP31.11
 
−
|Header
 
−
|-
 
−
| rowspan="2" |IO_L6N_T0_VREF_35
 
−
| rowspan="2" |IO_L6N_T0_VREF_35
 
−
|J27B.C27
 
−
|FMC conn.
 
−
| rowspan="2" |
 
−
| rowspan="2" |
 
−
| rowspan="2" |
 
−
|-
 
−
|TP23
 
−
|TP SMD
 
−
|-
 
−
|IO_L6P_T0_35
 
−
|IO_L6P_T0_35
 
−
|J27B.C26
 
−
|FMC conn.
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L7N_T1_AD2N_35
 
−
|IO_L7N_T1_AD2N_35
 
−
|J27D.H32
 
−
|FMC conn.
 
−
|FPGA_BANK35_AD2N
 
−
|JP30.10
 
−
|Header
 
−
|-
 
−
|IO_L7P_T1_AD2P_35
 
−
|IO_L7P_T1_AD2P_35
 
−
|J27D.H31
 
−
|FMC conn.
 
−
|FPGA_BANK35_AD2P
 
−
|JP30.8
 
−
|Header
 
−
|-
 
−
|IO_L8N_T1_AD10N_35
 
−
|IO_L8N_T1_AD10N_35
 
−
|J27D.G31
 
−
|FMC conn.
 
−
|FPGA_BANK35_AD10N
 
−
|JP32.2
 
−
|Header
 
−
|-
 
−
|IO_L8P_T1_AD10P_35
 
−
|IO_L8P_T1_AD10P_35
 
−
|J27D.G30
 
−
|FMC conn.
 
−
|FPGA_BANK35_AD10P
 
−
|JP31.16
 
−
|Header
 
−
|-
 
−
|IO_L9N_T1_DQS_AD3N_35
 
−
|IO_L9N_T1_DQS_AD3N_35
 
−
|J27D.H35
 
−
|FMC conn.
 
−
|FPGA_BANK35_AD3N
 
−
|JP30.11
 
−
|Header
 
−
|-
 
−
|IO_L9P_T1_DQS_AD3P_35
 
−
|IO_L9P_T1_DQS_AD3P_35
 
−
|J27D.H34
 
−
|FMC conn.
 
−
|FPGA_BANK35_AD3P
 
−
|JP30.9
 
−
|Header
 
−
|-
 
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
| rowspan="26" |13
 
−
'''(not available on Zynq 7007S and 7010)'''
 
−
|IO_L11P_T1_SRCC_13
 
−
|'''IO_L23P_T3_13'''
 
−
|JP17.3
 
−
|PMOD [A]
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L11N_T1_SRCC_13
 
−
|'''IO_L23N_T3_13'''
 
−
|JP17.4
 
−
|PMOD [A]
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|IO_L12P_T1_MRCC_13
 
−
|'''IO_L9P_T1_DQS_13'''
 
−
|JP17.2
 
−
|PMOD [A]
 
−
|IO_L9P_T1_DQS_13
 
−
|J30.1
 
−
|ONE PIECE
 
−
|-
 
−
|IO_L12N_T1_MRCC_13
 
−
|'''IO_L9N_T1_DQS_13'''
 
−
|JP17.1
 
−
|PMOD [A]
 
−
|IO_L9N_T1_DQS_13
 
−
|J30.3
 
−
|ONE PIECE
 
−
|-
 
−
|IO_L13P_T2_MRCC_13
 
−
|'''IO_L7P_T1_13'''
 
−
|JP17.7
 
−
|PMOD [A]
 
−
|IO_L7P_T1_13
 
−
|J30.24
 
−
|ONE PIECE
 
−
|-
 
−
|IO_L13N_T2_MRCC_13
 
−
|'''IO_L7N_T1_13'''
 
−
|JP17.8
 
−
|PMOD [A]
 
−
|IO_L7N_T1_13
 
−
|J30.26
 
−
|ONE PIECE
 
−
|-
 
−
|IO_L14P_T2_SRCC_13
 
−
|'''IO_L15P_T2_DQS_13'''
 
−
|n/a
 
−
|ETH1_RXCK
 
−
|IO_L15P_T2_DQS_13
 
−
|J30.25
 
−
|ONE PIECE
 
−
|-
 
−
|IO_L14N_T2_SRCC_13
 
−
|'''IO_L15N_T2_DQS_13'''
 
−
|n/a
 
−
|ETH1_RXCTL
 
−
|IO_L15N_T2_DQS_13
 
−
|J30.27
 
−
|ONE PIECE
 
−
|-
 
−
|IO_L15P_T2_DQS_13
 
−
|'''IO_L5P_T0_13'''
 
−
|JP17.6
 
−
|PMOD [A]
 
−
|IO_L5P_T0_13
 
−
|J30.20
 
−
|ONE PIECE
 
−
|-
 
−
|IO_L15N_T2_DQS_13
 
−
|'''IO_L5N_T0_13'''
 
−
|JP17.5
 
−
|PMOD [A]
 
−
|IO_L5N_T0_13
 
−
|J30.18
 
−
|ONE PIECE
 
−
|-
 
−
|IO_L16N_T2_13
 
−
|IO_L16N_T2_13
 
−
|n/a
 
−
|ETH1_TXCTL
 
−
|IO_L16N_T2_13
 
−
|J30.31
 
−
|ONE PIECE
 
−
|-
 
−
|IO_L16P_T2_13
 
−
|IO_L16P_T2_13
 
−
|n/a
 
−
|ETH1_TXCK
 
−
|IO_L16P_T2_13
 
−
|J30.29
 
−
|ONE PIECE
 
−
|-
 
−
|IO_L17N_T2_13
 
−
|IO_L17N_T2_13
 
−
|n/a
 
−
|ETH1_RXD1
 
−
|IO_L17N_T2_13
 
−
|J30.35
 
−
|ONE PIECE
 
−
|-
 
−
|IO_L17P_T2_13
 
−
|IO_L17P_T2_13
 
−
|n/a
 
−
|ETH1_RXD0
 
−
|IO_L17P_T2_13
 
−
|J30.33
 
−
|ONE PIECE
 
−
|-
 
−
|IO_L18N_T2_13
 
−
|IO_L18N_T2_13
 
−
|n/a
 
−
|ETH1_RXD3
 
−
|IO_L18N_T2_13
 
−
|J30.39
 
−
|ONE PIECE
 
−
|-
 
−
|IO_L18P_T2_13
 
−
|IO_L18P_T2_13
 
−
|n/a
 
−
|ETH1_RXD2
 
−
|IO_L18P_T2_13
 
−
|J30.37
 
−
|ONE PIECE
 
−
|-
 
−
|IO_L19N_T3_VREF_13
 
−
|IO_L19N_T3_VREF_13
 
−
|n/a
 
−
|ETH1_TXD1
 
−
|IO_L19N_T3_VREF_13
 
−
|J30.43
 
−
|ONE PIECE
 
−
|-
 
−
|IO_L19P_T3_13
 
−
|IO_L19P_T3_13
 
−
|n/a
 
−
|ETH1_TXD0
 
−
|IO_L19P_T3_13
 
−
|J30.41
 
−
|ONE PIECE
 
−
|-
 
−
|IO_L20N_T3_13
 
−
|IO_L20N_T3_13
 
−
|n/a
 
−
|ETH1_TXD3
 
−
|IO_L20N_T3_13
 
−
|J30.47
 
−
|ONE PIECE
 
−
|-
 
−
|IO_L20P_T3_13
 
−
|IO_L20P_T3_13
 
−
|n/a
 
−
|ETH1_TXD2
 
−
|IO_L20P_T3_13
 
−
|J30.45
 
−
|ONE PIECE
 
−
|-
 
−
|IO_L21N_T3_DQS_13
 
−
|IO_L21N_T3_DQS_13
 
−
|n/a
 
−
|ETH1_MDC
 
−
|IO_L21N_T3_DQS_13
 
−
|J30.51
 
−
|ONE PIECE
 
−
|-
 
−
|IO_L21P_T3_DQS_13
 
−
|IO_L21P_T3_DQS_13
 
−
|n/a
 
−
|ETH1_MDIO
 
−
|IO_L21P_T3_DQS_13
 
−
|J30.49
 
−
|ONE PIECE
 
−
|-
 
−
|IO_L22N_T3_13
 
−
|IO_L22N_T3_13
 
−
|
 
−
|
 
−
|IO_L22N_T3_13
 
−
|J30.55
 
−
|ONE PIECE
 
−
|-
 
−
|IO_L22P_T3_13
 
−
|IO_L22P_T3_13
 
−
|n/a
 
−
|DWM_WIFI_IRQ
 
−
|IO_L22P_T3_13
 
−
|J30.53
 
−
|ONE PIECE
 
−
|-
 
−
| rowspan="2" |IO_L6N_T0_VREF_13
 
−
| rowspan="2" |IO_L6N_T0_VREF_13
 
−
|JP23.3
 
−
|PMOD [B]
 
−
| rowspan="2" |IO_L6N_T0_VREF_13
 
−
| rowspan="2" |J30.30
 
−
| rowspan="2" |ONE PIECE
 
−
|-
 
−
|n/a
 
−
|USB1_OC
 
−
|}
 
−
 
−
==== BoraXEVB unavailable signals ====
 
−
Some BoraXEVB signals are unavailable when it is mated with Bora Lite SoM. The following signals are '''not''' routed to the SoM due to the limited pin count of the SODIMM connector.
 
−
 
−
{| class="wikitable"
 
−
|+
 
−
BoraXEVB's signal that are not available when mated with Bora Lite SoM
 
−
!Bank
 
−
!Carrier's signal
 
−
|-
 
−
|13
 
−
|IO_25_13
 
−
|-
 
−
|13
 
−
|IO_L1P_T0_13
 
−
|-
 
−
|13
 
−
|IO_L1N_T0_13
 
−
|-
 
−
|13
 
−
|IO_L2P_T0_13
 
−
|-
 
−
|13
 
−
|IO_L2N_T0_13
 
−
|-
 
−
|13
 
−
|IO_L3P_T0_DQS_13
 
−
|-
 
−
|13
 
−
|IO_L3N_T0_DQS_13
 
−
|-
 
−
|13
 
−
|IO_L4P_T0_13
 
−
|-
 
−
|13
 
−
|IO_L4N_T0_13
 
−
|-
 
−
|500
 
−
|NAND_CS0/SPI0_CS1
 
−
|-
 
−
|500
 
−
|NAND_IO3
 
−
|-
 
−
|500
 
−
|NAND_IO4
 
−
|-
 
−
|500
 
−
|NAND_IO5
 
−
|-
 
−
|500
 
−
|NAND_IO6
 
−
|-
 
−
|500
 
−
|NAND_IO7
 
−
|-
 
−
|500
 
−
|NAND_RD_B/VCFG1
 
−
|-
 
−
|500
 
−
|NAND_CLE/VCFG0
 
−
|}
 
−
<section end=SOM/>
 
−
 
−
<section begin=Schematics/>
 
  
 
==Schematics==
 
==Schematics==
−
* ORCAD: [https://www.dave.eu/links/p/yYW9VNsGutz6V0dd BORAXEVB-1.6.1-BELK-dsn.zip]
 
−
* PDF : [https://www.dave.eu/links/p/hClB4N7blBdSG6AH BoraXEVB-S-EVBBX0000C0R-1.6.1.pdf]
 
  
−
===BOM===
+
* ORCAD: '''TBD''' boraxevb-1.0.2-BELK-dsn.zip
−
* BoraXEVB: [https://www.dave.eu/links/p/PU08ewKLvX9Z9tZJ BORAXEVB_S.EVBBX0000C0R.1.6.0.CSV.zip]
+
* PDF : '''TBD''' BoraXEVB-S-EVBBX0000C0R-1.2.0.pdf
  
−
===Layout===
+
==BOM==
−
* [https://www.dave.eu/links/p/cPT5UVAFNiSzj4NR CS143714 Assembly view]
+
* BoraXEVB: '''TBD''' boraxevb-BOM_S.EVBBX0000C0R.1.2.0.CSV.zip
  
−
===PCB design (Mentor PADS)===
+
==Layout==
−
* [https://www.dave.eu/links/p/BCTblnPPoDiwPrAE CS143714]
+
* '''TBD''' boraxevb-CS143714_assembly_view.pdf
−
<section end=Schematics/>
 
−
<section begin=Mechanicals/>
 
  
 
==Mechanical==
 
==Mechanical==
−
* DXF: [https://www.dave.eu/links/p/s1k5AXL3AiCIo7Fj boraxevb-2D-CS143714]
+
* DXF: '''TBD''' boraxevb_2D_CS143714.zip
−
* IDF (3D): [https://www.dave.eu/links/p/xeQvq2IvKig5vlfd boraxevb-3D-CS143714]
+
* IDF (3D): '''TBD''' boraxevb_3D_CS143714.zip
−
* STEP (3D): [https://www.dave.eu/links/p/cj2s2AlBHkeY7tJ7 boraxevb_3D_step_cs143714]
 
−
<section end=Mechanicals/>
 

Revision as of 09:08, 5 November 2015

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BORA Xpress.png Applies to BORA Xpress

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Introduction[edit | edit source]

Bora Xpress EVB is a carrier board designed to host Bora Xpress system-on-module.

Block Diagram[edit | edit source]

The following picture shows Bora Xpress EVB block diagram:

File:Boraxevb-bd.png

Features[edit | edit source]

  • 10/100/1000 Ethernet #0 (PS)
  • 10/100/1000 Ethernet #1 (Routed through EMIO)
  • 1x USB 2.0 OTG (MicroAB connector)
  • 1x Serial port (RS232 DB9)
  • 1x MicroSD
  • 1x FPGA Mezzanine Card (FMC) Connector
  • XADC
    • Some signals of Bank 35 can be configured as XADC signals. For this reason they can be routed alternatively to 2.54mm-pitch connectors, instead of FMC connector.
  • State-of-the-art programmable MEMS clock generator (Silicon Labs Si504): this is an alternative clock source to allow the user to easily experiment his/her own peripherals and IPs on FPGA
  • JTAG port
  • Socket for DWM Wireless Module
  • Digilent Pmod™ Compatible expansion connectors
  • Headers for external for NAND flash and SPI NOR flash
  • 2.54mm-pitch pin-strip connectors for Bora Xpress PS and PL configurable peripherals (MIO and EMIO interfaces, GPIOs, custom IPs, ..)
  • Jumpers for voltage selection of the PL banks
  • +12V power connector

Known limitations[edit | edit source]

Board version CS040713A has the following limitations:

Issue Description
LCD_BKLT_PWM I/O voltage LCD_BKLT_PWM signal is derived from IO_0_13 on BANK13. In the case of LVDS signals for LCD the BANK 13 must be powered at 2.5V. So in this case LCD_BKLT_PWM is an LVCMOS 2.5V signal. It is recommended to place a voltage level translator to 3.3V if the signal voltages are not compatible with the LCD diplay backlight input.

Connectors pinout[edit | edit source]

J1[edit | edit source]

The pinout of the J1 connector of the Bora Xpress EVB is the same of the J1 connector on BORA Xpress module

J2[edit | edit source]

The pinout of the J2 connector of the Bora Xpress EVB is the same of the J2 connector on BORA Xpress module

J3[edit | edit source]

The pinout of the J3 connector of the Bora Xpress EVB is the same of the J3 connector on BORA Xpress module

Power supply - JP2[edit | edit source]

Power is provided through the JP2 connector.

JP2 connector is a standard 2.1mm/5.5mm DC power jack with positive center pin

Pin# Pin name Function Notes
1 VIN Power supply Nominal: +12V
2 , 3 DGND Ground -

Boot mode selection - S5[edit | edit source]

S5 is a dip-switch for the boot mode selection. The following table reports the available options and the related configurations:

S5.1 S5.2 S5.3 S5.4 S5.5 S5.6 S5.7 S5.8
SPI-NOR OFF ON OFF ON ON ON ON OFF
SD-card OFF ON OFF ON ON OFF ON OFF
NAND OFF ON OFF ON ON OFF ON ON
JTAG OFF ON OFF ON ON ON ON ON


Ethernet port #0 (ETH0) - J8[edit | edit source]

J8 is a RJ45 Gigabit Ethernet connector - incorporating magnetics - connected to the Bora Xpress integrated ethernet controller and PHY.

Pin# Pin name Function Notes
1 CT_TRD3 center tap TRD3 -
2 ETH_TXRX2_M - -
3 ETH_TXRX2_P - -
4 ETH_TXRX1_P - -
5 ETH_TXRX1_M - -
6 CT_TRD2 center tap TRD2 -
7 CT_TRD4 center tap TRD4 -
8 ETH_TXRX3_P - -
9 ETH_TXRX3_M - -
10 ETH_TXRX0_M - -
11 ETH_TXRX0_P - -
12 CT_TRD1 center tap TRD1 -
13 3.3V_ETH0_LED2 - -
15 3.3V_ETH0_LED1 - -
14, 16 +3.3V - -

Ethernet port #1 (ETH1) - J9[edit | edit source]

J9 is a RJ45 Gigabit Ethernet connector - incorporating magnetics - connected to Micrel KSZ9031 PHY (Gigabit Ethernet Transceiver). This, in turn, is connected to PL's bank 13 via RGMII interface. This is an example of EMIO routing showing how to route PS's MAC signals via PL subsystem.

Pin# Pin name Function Notes
1 CT_TRD3 center tap TRD3 -
2 ETH1_TXRX2_M - -
3 ETH1_TXRX2_P - -
4 ETH1_TXRX1_P - -
5 ETH1_TXRX1_M - -
6 CT_TRD2 center tap TRD2 -
7 CT_TRD4 center tap TRD4 -
8 ETH1_TXRX3_P - -
9 ETH1_TXRX3_M - -
10 ETH1_TXRX0_M - -
11 ETH1_TXRX0_P - -
12 CT_TRD1 center tap TRD1 -
13 3.3V_ETH1_LED2 - -
15 3.3V_ETH1_LED1 - -
14, 16 +3.3V - -

BANK's Power GOOD signals - J28[edit | edit source]

J28 is a 10-pin 5x2x2.54 pitch vertical header used for accessing to the POWER GOOD signals. The following table reports the pinout of the connector:

Pin# Pin name Function Notes
1 , 3 3.3V_SOM - -
2 SOM_PGOOD - -
4 1.8V_POWER_GOOD - -
5 3.3V_SBY - -
6 VADJ_PG - -
7 BANK13_PGOOD - -
8 BANK35_PGOOD - -
9 1V2_ETH1_PG - -
10 DGND - -

BANK13 VDDIO selector - JP25[edit | edit source]

JP25 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector:

Pin# Pin name Function Notes
2 LDO_B13_1V6 adds +1.6V to VDDIO_BANK13 -
4 LDO_B13_800mV adds +800mV to VDDIO_BANK13 -
6 LDO_B13_400mV adds +400mV to VDDIO_BANK13 -
8 LDO_B13_200mV adds +200mV to VDDIO_BANK13 -
10 LDO_B13_100mV adds +100mV to VDDIO_BANK13 -
12 LDO_B13_50mV adds +50mV to VDDIO_BANK13 -
1, 3, 5, 7, 9, 11 DGND - -

The jumper configurations are:

  1. No jumpers installed -> DC output for VDDIO_BANK13 is 500mV
  2. Jumper on 1-2 -> adds 1.6V to VDDIO_BANK13 above the default 500mV
  3. Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV
  4. Jumper on 5-6 -> adds 400mV to VDDIO_BANK13 above the default 500mV
  5. Jumper on 7-8 -> adds 200mV to VDDIO_BANK13 above the default 500mV
  6. Jumper on 9-10 -> adds 100mV to VDDIO_BANK13 above the default 500mV
  7. Jumper on 11-12 -> adds 50mV to VDDIO_BANK13 above the default 500mV

The DEFAULT configuration is VDDIO_BANK13 @ 1.8V (500mV + 800mV + 400mV + 100mV):

  1. Jumper on 3-4 -> adds 800mV to VDDIO_BANK13 above the default 500mV
  2. Jumper on 5-6 -> adds 400mV to VDDIO_BANK13
  3. Jumper on 9-10 -> adds 100mV to VDDIO_BANK13

BANK35 VDDIO selector - JP27[edit | edit source]

JP27 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector:

Pin# Pin name Function Notes
2 LDO_B35_1V6 adds +1.6V to VDDIO_BANK35 -
4 LDO_B35_800mV adds +800mV to VDDIO_BANK35 -
6 LDO_B35_400mV adds +400mV to VDDIO_BANK35 -
8 LDO_B35_200mV adds +200mV to VDDIO_BANK35 -
10 LDO_B35_100mV adds +100mV to VDDIO_BANK35 -
12 LDO_B35_50mV adds +50mV to VDDIO_BANK35 -
1, 3, 5, 7, 9, 11 DGND - -

The jumper configurations are:

  1. No jumpers installed -> DC output for VDDIO_BANK35 is 500mV
  2. Jumper on 1-2 -> adds 1.6V to VDDIO_BANK35 above the default 500mV
  3. Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above the default 500mV
  4. Jumper on 5-6 -> adds 400mV to VDDIO_BANK35 above the default 500mV
  5. Jumper on 7-8 -> adds 200mV to VDDIO_BANK35 above the default 500mV
  6. Jumper on 9-10 -> adds 100mV to VDDIO_BANK35 above the default 500mV
  7. Jumper on 11-12 -> adds 50mV to VDDIO_BANK35 above the default 500mV

The DEFAULT configuration is VDDIO_BANK35 @ 1.8V (500mV + 800mV + 400mV + 100mV):

  1. Jumper on 3-4 -> adds 800mV to VDDIO_BANK35 above the default 500mV
  2. Jumper on 5-6 -> adds 400mV to VDDIO_BANK35
  3. Jumper on 9-10 -> adds 100mV to VDDIO_BANK35

Please note that:

  • By default VDDIO_BANK35 is supplied by VADJ Regulator

VADJ VDDIO selector - JP28[edit | edit source]

JP28 is a 12-pin 6x2x2.54 pitch vertical header used for the selection - through jumpers - of the bank supply voltages. The following table reports the pinout of the connector:

Pin# Pin name Function Notes
2 VADJ_FB (22K) selects 3.3V VADJ -
4 VADJ_FB (30K9) selects 2.5V VADJ -
6 VADJ_FB (51K1) selects 1.8V VADJ -
8 VADJ_FB (68K) selects 1.5V VADJ -
10 VADJ_FB (100K) selects 1.2V VADJ -
12 RFU Reserved -
1, 3, 5, 7, 9, 11 DGND - -

The jumper configurations are:

  1. Jumper on 1-2 -> supply VADJ with 3.3V
  2. Jumper on 3-4 -> supply VADJ with 2.5V
  3. Jumper on 5-6 -> supply VADJ with 1.8V
  4. Jumper on 7-8 -> supply VADJ with 1.5V
  5. Jumper on 9-10 -> supply VADJ with 1.2V

The DEFAULT configuration is:

  1. Jumper on 5-6 -> supply VADJ with 1.8V

JTAG[edit | edit source]

JTAG port is available as two different mechanical connectors:

  • 2.00mm-pitch 7x2 header (Xilinx standard)
  • 2.54mm-pitch 10x2 header (ARM standard): http://www2.lauterbach.com/pdf/arm_app_jtag.pdf
  • This port is connected to Zynq's native JTAG signals. Please note that Zynq's internal JTAG chain supports differents configurations, depending on bootstrap signals. In case split mode is selected, CPU JTAG can be routed separately via PL. For more details please refer to Zynq Technical Reference Manual.
  • JTAG on Bora Xpress EVB is also connected to the FMC connector. For more details on how to connect JTAG on a custom FMC card please refer to ANSI/VITA FPGA Mezzanine Card (FMC) Standard.

JTAG XILINX - J13[edit | edit source]

J13 is a 14-pin 7x2x2 pitch vertical header. The following table reports the pinout of the connector:

Pin# Pin name Function Notes
1, 3, 5, 7, 9, 11, 13 DGND - -
2 3.3V - -
4 JTAG_TMS - -
6 JTAG_TCK - -
8 JTAG_TDO - -
10 JTAG_TDI - -
12 N.C. - -
14 JTAG_TRSTn - -

JTAG ARM - J18[edit | edit source]

J18 is a 20-pin 10x2x2.54 pitch vertical header. The following table reports the pinout of the connector:

Pin# Pin name Function Notes
1 3.3V - -
2 3.3V - -
3, 11, 17, 19 N.C. - -
4, 6 ,8 ,10 ,12,
14, 16, 18, 20		 DGND - -
5 JTAG_TDI - -
7 JTAG_TMS - -
9 JTAG_TCK - -
13 JTAG_TDO - -
15 JTAG_TRSTn - -

UART1 - J17[edit | edit source]

J17 is a standard DB9 connector that routes the signals coming from the RS232 transceiver that is connected to the PS MIO signals of the UART1 port.

Pin# Pin name Function Notes
1, 6, 4, 9 N.C. N.C.
2 UART_EXT_RX Receive line Connected to protection diode array
3 UART_EXT_TX Transmit line Connected to protection diode array
5 DGND Ground
7, 8 N.C. N.C. Connected to protection diode array

USB OTG - J19[edit | edit source]

J19 is a standard USB MICRO AB connector. It is connected to the Bora Xpress USB 2.0 OTG peripheral. The following table reports the pinout of the connector:

Pin# Pin name Function Notes
1 USB_OTG_VBUS - -
2 USBM1 - -
3 USBP1 - -
4 OTG_ID - -
5 USB_OTG_DGND - -
6, 7, 8, 9 USB_OTG_SHIELD - -

MicroSD - J21[edit | edit source]

J21 is a microSD memory card connector. It is connected to the Bora Xpress SOM through a bidirectional 1.8V/3.3V voltage-level translator mounted on the Bora Xpress EVB. Level shifter is required because MIO signals are 1.8V. The following table reports the pinout of the connector:

Pin# Pin name Function Notes
1 PS_SD0_DAT2 - -
2 PS_SD0_DAT3 - -
3 PS_SD0_CMD - -
4 3.3V - -
5 PS_SD0_CLK - -
6, 9, 10, 11, 12 DGND - -
7 PS_SD0_DAT0 - -
8 PS_SD0_DAT1 - -
3.3V - Pull up to 3.3V with 10K Ohm -

DWM (DAVE Wifi/BT module) socket - J23[edit | edit source]

J23 is a 52991-0308 connector type (30 pins, vertical, 0.50mm picth). This socket connects the DWM Wireless Module (optional) to the Bora Xpress EVB. The following table reports the pinout of the connector:

Pin# Pin name Function Notes
1, 2 5V - -
3, 4 3.3V - -
5, 6,
9, 10,
19		 DGND - -
7 DWM_SD_CMD - -
8 DWM_SD_CLK - -
11 DWM_SD_DAT0 - -
12, 14,
16, 18,
20, 22		 N.C. - -
13 DWM_SD_DAT1 - -
15 DWM_SD_DAT2 - -
17 DWM_SD_DAT3 - -
21 DWM_UART_RX - -
23 DWM_UART_CTS - -
24 DWM_BT_F5 - -
25 DWM_UART_TX - -
26 DWM_BT_F2 - -
27 DWM_UART_RTS - -
28 DWM_WIFI_IRQ - -
29 DWM_BT_EN - -
30 DWM_WIFI_EN - -

CAN - J24[edit | edit source]

J24 is a 10-pin 5x2x2.54mm pitch vertical header directly connected to Bora Xpress SoM's transceiver for the CAN interface. This 2.5mm-pitch header is compatible with commonly available IDC-10/DB9 flat cables. The following table reports the pinout of the connector:

Pin# Pin name Function Notes
1, 6,
7, 8,
9, 10		 N.C. - -
2, 5 CAN_SHIELD - -
3 CAN_L - -
4 CAN_H - -

Touch screen - J25[edit | edit source]

J25 is a ZIF 4-pin 1.0mm pitch connector that connects the touchscreen drive lines to the touch screen controller on the Bora Xpress EVB. The following table reports the pinout of the connector:

Pin# Pin name Function Notes
1 TSC_YP - -
2 TSC_XP - -
3 TSC_YM - -
4 TSC_XM - -

LVDS - J26[edit | edit source]

J26 is a vertical double row straight 20-pin 1.25mm pitch header. This interface shows how to implement a differential connection to an LCD screen. As known, Zynq does not implement an LCD controller, however this can be integrated in FPGA fabric as shown by this example: https://wiki.analog.com/resources/tools-software/linux-drivers/platforms/zynq. The following table reports the pinout of the connector:

Pin# Pin name Function Notes
1, 2 3.3V_LCD - -
3, 4, 7, 10,
13, 16, 19		 DGND Ground -
5 LCD_LVDS_D0- - -
6 LCD_LVDS_D0+ - -
8 LCD_LVDS_D1- - -
9 LCD_LVDS_D1+ - -
11 LCD_LVDS_D2- - -
12 LCD_LVDS_D2+ - -
15 LCD_LVDS_CLK+ - -
17 LCD_P17 - -
18 LCD_P18 - -
20 LCD_P20 - -
21,22 DGND Ground Shield

Pin strip connectors[edit | edit source]

SPI,NAND - JP13[edit | edit source]

JP13 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:

Pin# Pin name Function Notes
1, 4, 9, 12 DGND Ground -
2 SPI0_CS0n - -
3 ZYNQ_SPI0_SCLK/NAND_IO1 - -
5 ZYNQ_SPI0_DQ0/NAND_ALE - -
6 NAND_CS0/SPI0_CS1 - -
7 ZYNQ_SPI0_DQ2/NAND_IO2 - -
8 ZYNQ_SPI0_DQ1/NAND_WE - -
10 ZYNQ_SPI0_DQ3/NAND_IO0 - -
11 ZYNQ_NAND_RD_B - -

Voltage Monitor - JP15[edit | edit source]

JP15 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:

Pin# Pin name Function Notes
1 MON_VCCPLL - -
2 MON_3.3V - -
3 MON_XADC_VCC - -
4 MON_1V2_ETH - -
5 MON_FPGA_VDDIO_BANK35 - -
6 MON_VDDQ_1V5 - -
7 MON_FPGA_VDDIO_BANK34 - -
8 MON_1.8V - -
9 MON_FPGA_VDDIO_BANK13 - -
10 MON_1.0V - -
11 MON_1.8V_IO - -
12 MON_MGTAVCC - -
13 MON_MGTAVTT - -
14 MON_MGTAVCCAUX - -
15, 16 DGND Ground -


Ethernet GPIO - JP18[edit | edit source]

JP18 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:

Pin# Pin name Function Notes
1, 2, 5,
6, 16		 DGND Ground -
3 CLK125_NDO - -
4 ETH1_CLK125_NDO - -
7 ETH_MDC - -
8 ETH1_MDC - -
9 ETH_MDIO - -
10 ETH1_MDIO - -
11 ETH_INTn - -
12 ETH1_INTn - -
13 PS_MIO51_501 - -
14 ETH1_RESETn - -
15 PS_MIO50_501 - -


SPI,NAND - JP19[edit | edit source]

JP19 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:

Pin# Pin name Function Notes
1, 11, 12 DGND Ground -
2 NAND_BUSY - -
3 ZYNQ_NAND_CLE - -
4 NAND_IO3 - -
5 NAND_IO4 - -
6 NAND_IO5 - -
7 NAND_IO6 - -
8 NAND_IO7 - -
9 CONN_SPI_RSTn - -
10 MEM_WPn - -

FPGA, WatchDog, RTC, RST - JP22[edit | edit source]

JP22 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:

Pin# Pin name Function Notes
1 FPGA_INIT_B - -
2 RTC_32KHZ - -
3 FPGA_PROGRAM_B - -
4 RTC_RST - -
5 FPGA_DONE - -
6 RTC_INT/SQW - -
7, 8 DGND Ground -
9 WD_SET0 - -
10 SYS_RSTn - -
11 WD_SET1 - -
12 PORSTn - -
13 WD_SET2 - -
14 MRSTn - -
15 PS_MIO15_500 - -
16 CB_PWR_GOOD - -

AUX PINs - JP29[edit | edit source]

JP29 is a 16-pin 8x2x2.54 pitch vertical header. The following table reports the pinout of the connector:

Pin# Pin name Function Notes
1 EVB_1.8V - -
2 3.3V - -
3 PS_I2C0_DAT - -
4 I2C0_SDA - -
5 PS_I2C0_CK - -
6 I2C0_SCL - -
7, 8,
13		 DGND Ground -
9 EXT_VMON2_V1 - Mount option
10, 16 XADC_AGND Analog Ground -
11 EXT_VMON2_V2 - Mount option
12 XADC_VN_R - -
14 XADC_VP_R - -
15 INA_ALERT - -

Please note that:

  • Three devices are connected to I2C0 bus (this is level shifted from 1.8V to 3.3V):
    • Silicon Labs Si571 programmable clock generator: this clock si connected to PL to allow the user to easily experiment his/her own peripherals and IPs on FPGA
    • resistive touch screen controller for LCD screen
    • consumption monitor: this is connected to shunt resistor put in series on Bora power rail, allowing to measure SoM consumption

ADC - JP30, JP31, JP32[edit | edit source]

JP30, JP31, JP32 are 16-pin 8x2x2.54 pitch vertical header. The following tables reports the pinout of the connectors:

JP30:

Pin# Pin name Function Notes
2 FPGA_BANK35_AD0N AD0_N Mount option
3 FPGA_BANK35_AD1P AD1_P Mount option
4 FPGA_BANK35_AD0P AD0_P Mount option
5 FPGA_BANK35_AD1N AD1_N Mount option
8 FPGA_BANK35_AD2P AD2_P Mount option
9 FPGA_BANK35_AD3P AD3_P Mount option
10 FPGA_BANK35_AD2N AD2_N Mount option
11 FPGA_BANK35_AD3N AD3_N Mount option
14 FPGA_BANK35_AD4P AD4_P Mount option
15 FPGA_BANK35_AD5P AD5_P Mount option
16 FPGA_BANK35_AD4N AD4_N Mount option
1, 6, 7,
12, 13		 DGND - -

JP31:

Pin# Pin name Function Notes
1 FPGA_BANK35_AD5N AD5_N Mount option
4 FPGA_BANK35_AD6P AD6_P Mount option
5 FPGA_BANK35_AD7P AD7_P Mount option
6 FPGA_BANK35_AD6N AD6_N Mount option
7 FPGA_BANK35_AD7N AD7_N Mount option
10 FPGA_BANK35_AD8P AD8_P Mount option
11 FPGA_BANK35_AD9P AD9_P Mount option
12 FPGA_BANK35_AD8N AD8_N Mount option
13 FPGA_BANK35_AD9N AD9_N Mount option
16 FPGA_BANK35_AD10P AD10_P Mount option
2, 3, 8,
9, 14, 15		 DGND - -

JP32:

Pin# Pin name Function Notes
1 FPGA_BANK35_AD11P AD11_P Mount option
2 FPGA_BANK35_AD10N AD10_N Mount option
3 FPGA_BANK35_AD11N AD11_N Mount option
6 FPGA_BANK35_AD12P AD12_P Mount option
7 FPGA_BANK35_AD13P AD13_P Mount option
8 FPGA_BANK35_AD12N AD12_N Mount option
9 FPGA_BANK35_AD13N AD13_N Mount option
12 FPGA_BANK35_AD14P AD14_P Mount option
13 FPGA_BANK35_AD15P AD15_P Mount option
14 FPGA_BANK35_AD14N AD14_N Mount option
15 FPGA_BANK35_AD15N AD15_N Mount option
4, 5, 10,
11, 16		 DGND - -

Digilent Pmod™ Compatible headers[edit | edit source]

Please note that:

Digilent Pmod™ Compatible - JP17[edit | edit source]

JP17 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:

Pin# Pin name Function Notes
1 PMOD_A0 -
2 PMOD_A4 -
3 PMOD_A1 -
4 PMOD_A5 -
5 PMOD_A2 -
6 PMOD_A6 -
7 PMOD_A3 -
8 PMOD_A7 -
9, 10 DGND Ground -
11, 12 3.3V -


Digilent Pmod™ Compatible - JP23[edit | edit source]

JP23 is a 12-pin 6x2x2.54 pitch vertical header. The following table reports the pinout of the connector:

Pin# Pin name Function Notes
1 PMOD_B0 - -
2 PMOD_B4 - -
3 PMOD_B1 - -
4 PMOD_B5 - -
5 PMOD_B2 - -
6 PMOD_B6 - -
7 PMOD_B3 - -
8 PMOD_B7 - -
9, 10 DGND Ground -
11, 12 3.3V - -

Schematics[edit | edit source]

  • ORCAD: TBD boraxevb-1.0.2-BELK-dsn.zip
  • PDF : TBD BoraXEVB-S-EVBBX0000C0R-1.2.0.pdf

BOM[edit | edit source]

  • BoraXEVB: TBD boraxevb-BOM_S.EVBBX0000C0R.1.2.0.CSV.zip

Layout[edit | edit source]

  • TBD boraxevb-CS143714_assembly_view.pdf

Mechanical[edit | edit source]

  • DXF: TBD boraxevb_2D_CS143714.zip
  • IDF (3D): TBD boraxevb_3D_CS143714.zip
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