dave_user
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Changes
m
Some releated with some related control signals are avaible:
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* '''PMIC_ON_REQ''', to start a PMIC power sequence, so that reboot the SoC
* '''CPU_PORn''', to force memories and peripherals to reset, in order to bring them in a known condition
* '''SOM_PGOOD''', to turn on circuitry external to the SOM
* '''PMIC_INTn''', to manage PMIC register interrupts
and provides these power control signals:
* '''PMIC_STBY_REQ''', to generate proper power for the SoC sleep mode
* '''ONOFF''', to turn off the SoC in a low-power use cases
Voltage monitors can trigger a power reset If a voltage drop occurs.
This causes SoC reboot.
|-
|'''CPU_PORn'''
|PMIC Input
pulled-down with 100 kohm inside the SOM
|Externally or SoC
|PMIC
|PMIC enters in standby mode when PMIC_STBY_REQ is asserted high.
|Externally
|SoC
|SoC enters in power down when ONOFF is asserted highlow. The main power must remain active so that some data can be stored even if the processor is turned off. See Battery-Backed Non-Secure Module (BBNSM) on reference manual.
|}