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=== CPU_PORn ===
The following devices can assert this active-low signal:
* PMIC
* multiple-voltage monitor: this device monitors critical power voltages and triggers a reset pulse in case any of these exhibits a brownout condition
Since SPI NOR flash can be used as a boot device, CPU_PORn is connected to this device too. This guarantees it is in a known state when reset signal is released.
Ciclo di reset completo utilizzare
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== Reset scheme and control signals ==
The following picture shows the simplified block diagram of the reset scheme , power control signal and voltage monitoring.
[[File:AURA-reset-scheme.png | 800px]]
AURA SOM provides the following reset signals:
* '''SYS_nRST''', to performs a PMIC reset (cold or warm reset depends on PIMIC configuration register)* '''WDOG_B''', pulled-up with 100 kohm* '''CPU_PORn''', pulled-up with 100 kohm. This signal, pilot by the to performs a PMIC, reset SoC's CPU and onboard eMMC and ethernet PHY.* '''PMIC_INTn''', pulled-up with 10 kohmFurthermore, some control signals are avaible:* '''SOM_PGOOD''', (cold or warm reset depends on PIMIC configuration register)
* '''PMIC_ON_REQ''', pulled-down to start a PMIC power sequence, so that reboot the SoC* '''CPU_PORn''', to force memories and peripherals to reset, in order to bring them in a known conditionwith 100 kohmsome related control signals:* '''SOM_PGOOD''', to turn on circuitry external to the SOM * '''PMIC_INTn''', to manage PMIC register interruptsand provides these power control signals:* '''PMIC_STBY_REQ''', pulled-down with 100 kohmto generate proper power for the SoC sleep mode* '''ONOFF''', pulledto turn off the SoC in a low-up with 100 kohmpower use cases
The electrical and functional characteristics of these signals are listed in the following table:
{| class="wikitable" 50style="width:53%"
|+
!style="width:15%" |Signal!style="width:25%" |Type!style="width:15%" |Driven!style="width:15%" |Affect!style="width:30%" |Purpose
|-
|'''SYS_nRST'''
|PMIC Input, pulled-up inside the PMIC
|Externally
|PMIC
|PMIC performs reset (cold or warm reset depends on its configuration register) when SYS_nRST is asserted low.
|-
|'''WDOG_B'''
|PMIC Input, pulled-up with 100 kohm inside the SOM
|Externally or SoC
|PMIC
|PMIC performs reset (cold or warm reset depends on its configuration register) when WDOG_B is asserted low. |-|'''PMIC_ON_REQ'''|PMIC Inputpulled-down with 100 kohm inside the SOM|Externally or SoC|PMIC|PMIC starts power on sequence when PMIC_ON_REQ is asserted high. Voltage monitors can trigger a power reset If a voltage drop occurs. This causes SoC reboot.
|-
|'''CPU_PORn'''
|PMIC Output, open drain, pulled-up with 100 kohm inside the SOM
|PMIC
|SoC, onboard eMMC and PHY ETH, External
|Reset memories and peripherals internal and external to the SOM after a power-on sequence. This guarantees it is in a known state when reset signal is released.
|-
|'''SOM_PGOOD'''
|SOM
|External
|Turn on the external circuitry of the SOMwhen the SoC is ready, in order to prevent backpower.
|-
|'''PMIC_INTn'''
|PMIC Output, open drain, pulled-up with 10 kohm inside the SOM
|PMIC
|SoC and External
||-|'''PMIC_ON_REQ''PMIC_INTn is asserted low when an interrupt bit status in PMIC'|PMIC Input, pulled-down with 100 kohm inside the SOM|Externally or SoC|PMIC|s register is changed.
|-
|'''PMIC_STBY_REQ'''
|PMIC Input, pulled-down with 100 kohm inside the SOM|Externally or SoC
|PMIC
|PMIC enters in standby mode when PMIC_STBY_REQ is asserted high. This allows the SoC to enter sleep mode.
|-
|'''ONOFF'''
|SoC Input, pulled-up with 100 kohm inside the SOM
|Externally
|SoC
|SoC enters in power down when ONOFF is asserted low. The main power must remain active so that some data can be stored even if the processor is turned off. See Battery-Backed Non-Secure Module (BBNSM) on reference manual.
|}
=== Handling CPU-initiated software reset ===