The following picture shows the simplified block diagram of the reset scheme , power control signal and voltage monitoring.

* '''SYS_nRST'''* '''CPU_PORn''', pulled-up with 100 kohm. This signal, pilot by the to performs a PMIC, reset SoC's CPU and onboard eMMC and ethernet PHY.(cold or warm reset depends on PIMIC configuration register)* '''WDOG_B''', pulled-up with 100 kohm* '''PMIC_INTn''', pulled-up with 10 kohmFurthermore, the following control signals are present:* '''SOM_PGOOD''', to performs a PMIC reset (cold or warm reset depends on PIMIC configuration register)

* '''PMIC_ON_REQ''', pulled-down to start a PMIC power sequence, so that reboot the SoC* '''CPU_PORn''', to force memories and peripherals to reset, in order to bring them in a known conditionwith 100 kohmsome related control signals:* '''SOM_PGOOD''', to turn on circuitry external to the SOM * '''PMIC_INTn''', to manage PMIC register interruptsand provides these power control signals:* '''PMIC_STBY_REQ''', pulled-down with 100 kohmto generate proper power for the SoC sleep mode* '''ONOFF''', pulledto turn off the SoC in a low-up with 100 kohmpower use cases

The electrical and functional characteristics of these signals are listed in the following table:{| class="wikitable" style="width:53%" |+! style="width:15%" |Signal! style="width:25%" |Type! style="width:15%" |Driven! style="width:15%" |Affect! style="width:30%" |Purpose|-|'''SYS_nRST'''|PMIC Inputpulled-up inside the PMIC|Externally|PMIC|PMIC performs reset (cold or warm reset depends on its configuration register) when SYS_nRST is asserted low.|-|'''WDOG_B'''TBD: indicare le connessioni del segnale di |PMIC Inputpulled-up with 100 kohm inside the SOM|Externally or SoC|PMIC|PMIC performs reset verso altri device interni (come per esempio la NOR SPIcold or warm reset depends on its configuration register) when WDOG_B is asserted low. |-|'''PMIC_ON_REQ'''|PMIC Inputpulled-down with 100 kohm inside the SOM|Externally or SoC|PMIC|PMIC starts power on sequence when PMIC_ON_REQ is asserted high.

The following devices can assert this activeThis causes SoC reboot.|-low signal:* |'''CPU_PORn'''|PMICOutput, open drain* multiplepulled-voltage monitor: this device monitors critical power voltages and triggers a reset pulse in case any of these exhibits a brownout condition up with 100 kohm inside the SOM |PMICSince SPI NOR flash can be used as a boot device|SoC, onboard eMMC and PHY ETH, CPU_PORn is connected External|Reset memories and peripherals internal and external to this device toothe SOM after a power-on sequence. This guarantees it is in a known state when reset signal is released. |-|'''SOM_PGOOD'''|Monitor Output, 3V3 LVTTL|SOM|External|Turn on the external circuitry of the SOM when the SoC is ready, in order to prevent backpower.|-|'''PMIC_INTn'''|PMIC Output, open drainpulled-up with 10 kohm inside the SOM|PMIC|SoC and External|PMIC_INTn is asserted low when an interrupt bit status in PMIC's register is changed.|-|'''PMIC_STBY_REQ'''|PMIC Inputpulled-down with 100 kohm inside the SOM|SoC|PMIC|PMIC enters in standby mode when PMIC_STBY_REQ is asserted high.