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''TBD: qui di seguito vanno inserite le sezioni che includano la descrizione dei segnali coinvolti nella fase di Reset, ad esempioAURA SOM provides the following reset signals:
The following devices Voltage monitors can assert this active-low signal:* PMIC* multiple-voltage monitor: this device monitors critical trigger a power voltages and triggers a reset pulse in case any of these exhibits If a brownout condition voltage drop occurs.
Since SPI NOR flash can be used as a boot deviceThis causes SoC reboot.|-|'''CPU_PORn'''|PMIC Output, open drainpulled-up with 100 kohm inside the SOM |PMIC|SoC, onboard eMMC and PHY ETH, CPU_PORn is connected External|Reset memories and peripherals internal and external to this device toothe SOM after a power-on sequence. This guarantees it is in a known state when reset signal is released. |-|'''SOM_PGOOD'''|Monitor Output, 3V3 LVTTL|SOM|External|Turn on the external circuitry of the SOM when the SoC is ready, in order to prevent backpower.|-|'''PMIC_INTn'''|PMIC Output, open drainpulled-up with 10 kohm inside the SOM|PMIC|SoC and External|PMIC_INTn is asserted low when an interrupt bit status in PMIC's register is changed.|-|'''PMIC_STBY_REQ'''|PMIC Inputpulled-down with 100 kohm inside the SOM|SoC|PMIC|PMIC enters in standby mode when PMIC_STBY_REQ is asserted high.
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<section begin="History" />
{| style="border-collapse:collapse; "
!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History
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!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes
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|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|2024/02/dd|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|First documentation release
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<section end="History" />
__FORCETOC__
<section begin="Body" />
[[File:TBD.png | center | 400px]]
== Reset scheme and control signals ==
The following picture shows the simplified block diagram of the reset scheme , power control signal and voltage monitoring.
[[File:AURA-reset-scheme.png | 800px]]
* '''SYS_nRST''', to performs a PMIC reset (cold or warm reset depends on PIMIC configuration register)* CPU_PORn* SNVS* ...'''WDOG_B''', to performs a PMIC reset (cold or warm reset depends on PIMIC configuration register)
* '''TBDPMIC_ON_REQ''', to start a PMIC power sequence, so that reboot the SoC* '''CPU_PORn''', to force memories and peripherals to reset, in order to bring them in a known conditionwith some related control signals: indicare le connessioni del segnale di reset verso altri device interni (come per esempio la NOR SPI* '''SOM_PGOOD''', to turn on circuitry external to the SOM * '''PMIC_INTn''', to manage PMIC register interruptsand provides these power control signals:* '''PMIC_STBY_REQ''', to generate proper power for the SoC sleep mode* '''ONOFF''', to turn off the SoC in a low-power use cases
The electrical and functional characteristics of these signals are listed in the following table:{| class="wikitable" style="width:53%" |+! style= CPU_PORn "width:15%" |Signal! style="width:25%" |Type! style="width:15%" |Driven! style="width:15%" |Affect! style="width:30%" |Purpose|-|'''SYS_nRST'''|PMIC Inputpulled-up inside the PMIC|Externally|PMIC|PMIC performs reset (cold or warm reset depends on its configuration register) when SYS_nRST is asserted low.|-|'''WDOG_B'''|PMIC Inputpulled-up with 100 kohm inside the SOM|Externally or SoC|PMIC|PMIC performs reset (cold or warm reset depends on its configuration register) when WDOG_B is asserted low. |-|'''PMIC_ON_REQ'''|PMIC Inputpulled-down with 100 kohm inside the SOM|Externally or SoC|PMIC|PMIC starts power on sequence when PMIC_ON_REQ is asserted high.
This allows the SoC to enter sleep mode.
|-
|'''ONOFF'''
|SoC Input
pulled-up with 100 kohm inside the SOM
|Externally
|SoC
|SoC enters in power down when ONOFF is asserted low. The main power must remain active so that some data can be stored even if the processor is turned off. See Battery-Backed Non-Secure Module (BBNSM) on reference manual.
|}
=== Handling CPU-initiated software reset ===
This technique is implemented in [[DESK-MX9-L]]. At the software level, U-Boot and Linux kernel software reset routines make use of the processor's WDT #1 to assert the WDOG1_WDOG reset signal. This signal in turn is routed to WDOG_ANY pad (MUX mode ALT_0). At the hardware level, this signal is connected to the WDOG_B PMIC pin driving a PMIC reset.
<section end="Body" />
[[Category:AURA]]