<section begin="History" />

!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History

!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes

|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Year2024/Month02/Daydd|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|TBDFirst documentation release

<section end="History" />

<section begin="Body" /> [[File:TBD.png | center | 400px]]

The following picture shows the simplified block diagram of the reset scheme , power control signal and voltage monitoring.

''TBD: qui di seguito vanno inserite le sezioni che includano la descrizione dei segnali coinvolti nella fase di Reset, ad esempioAURA SOM provides the following reset signals:

* MRST'''SYS_nRST''', to performs a PMIC reset (cold or warm reset depends on PIMIC configuration register)* POR* SNVS* SYSRST* ...'''WDOG_B''', to performs a PMIC reset (cold or warm reset depends on PIMIC configuration register)

* '''TBDPMIC_ON_REQ''', to start a PMIC power sequence, so that reboot the SoC* '''CPU_PORn''', to force memories and peripherals to reset, in order to bring them in a known conditionwith some related control signals: indicare le connessioni del segnale di reset verso altri device interni (come per esempio la NOR SPI* '''SOM_PGOOD''', to turn on circuitry external to the SOM * '''PMIC_INTn''', to manage PMIC register interruptsand provides these power control signals:* '''PMIC_STBY_REQ''', to generate proper power for the SoC sleep mode* '''ONOFF''', to turn off the SoC in a low-power use cases

The electrical and functional characteristics of these signals are listed in the following table:{| class="wikitable" style="width:53%" |+! style="width:15%" |Signal! style="width:25%" |Type! style="width:15%" |Driven! style="width:15%" |Affect! style="width:30%" |Purpose|-|'''SYS_nRST''TBD: di seguito la pagina di AXEL Lite da rivedere nel caso di altri '|PMIC Inputpulled-up inside the PMIC|Externally|PMIC|PMIC performs reset (cold or warm reset depends on its configuration register) when SYS_nRST is asserted low.|-|'''WDOG_B'''|PMIC Inputpulled-up with 100 kohm inside the SOM|Externally or SoC|PMIC|PMIC performs reset (cold or warm reset depends on its configuration register) when WDOG_B is asserted low. |-|'''PMIC_ON_REQ'''|PMIC Inputpulled-down with 100 kohm inside the SOM|Externally or SoC|PMIC|PMIC starts power on sequence when PMIC_ON_REQ is asserted high.

=== PMIC_VSNVS ===Some signals that are related to Voltage monitors can trigger a power reset circuitry are pulled-up to PMIC_VSNVS. This voltage is generated by PMIC PF0100's VSNVS LDO/Switch and its actual value depends on:* voltage applied to PMICS's VIN pin** in case of AxelLite this pin is connected to 3.3VIN power rail* If a voltage applied to PMICS's LICELL pin** in case of AxelLite this pin is connected to pin 14 of SODIMM connector (PMIC_LICELL)* PMIC's VSNVSCTL register configuration.Hence '''it is recommended that system designer takes into account these factors in order to properly manage these signals at carrier board level'''drop occurs.

For more details please refer to section This causes SoC reboot.|-|''VSNVS LDO/Switch'' of 'CPU_PORn'MMPF0100 Advance Information'' document.|PMIC Output, open drain=== CPU_PORn === The following devices can assert this activepulled-low signal:up with 100 kohm inside the SOM * |PMIC* multiple-voltage monitor: this device monitors critical power voltages |SoC, onboard eMMC and triggers a reset pulse in case any of these exhibits a brownout condition PHY ETH, External Since SPI NOR flash can be used as boot device, CPU_PORn is connected |Reset memories and peripherals internal and external to this device toothe SOM after a power-on sequence. This guarantees it is in a known state when reset signal is released. |-|'''SOM_PGOOD'''|Monitor Output, 3V3 LVTTL|SOM|External|Turn on the external circuitry of the SOM when the SoC is ready, in order to prevent backpower.|-|'''PMIC_INTn'''|PMIC Output, open drainpulled-up with 10 kohm inside the SOM|PMIC|SoC and External|PMIC_INTn is asserted low when an interrupt bit status in PMIC's register is changed.|-|'''PMIC_STBY_REQ'''|PMIC Inputpulled-down with 100 kohm inside the SOM|SoC|PMIC|PMIC enters in standby mode when PMIC_STBY_REQ is asserted high.

'''By default, MX6 i.MX93 processor does not assert any external signal when it initiates a software reset sequence. Also , default software reset implementation does not guarantee that all processor registers are reset properly. '''.

This technique is implemented in [[DESK-MX9-L]]. At the software level, U-Boot and Linux kernel software reset routines make use of the processor's WDT #2 1 to assert the WDOG2_B WDOG1_WDOG reset signal. This signal in turn is routed to GPIO_1 WDOG_ANY pad (MUX mode = 1ALT_0). At the hardware level, this signal is AC-coupled connected to the WDOG_B PMIC pin driving a 3-state output buffer (please refer to U22 chip of [[AxelEVB-Lite]] carrier board), driving PMIC_PWRONPMIC reset.

<section end="Body" />