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! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |ID#
[[File:TBD.png|thumb|300px|center]]
* {||A: PIMX9352CVUXMAA* |1.7GHz|Dual Core|Tj: (-40+105)|Full Feature (Preliminary samples)|-|B: MIMX9352DVVxMAB* |1.7GHz|Dual Core|Tj: (0+95)|Full Feature|-|C: MIMX9352CVVxMAB* |1.7GHz|Dual Core|Tj: (-40+105)|Full Feature|-|D: MIMX9352XVVxMAB* |1.7GHz|Dual Core|Tj: (-40+125)|Full Feature|-|E: MIMX9351DVVxMAB* |1.7GHz|Single Core|Tj: (0+95)|Full Feature|-|F: MIMX9351CVVxMAB* |1.7GHz|Single Core|Tj: (-40+105)|Full Feature|-|G: MIMX9351XVVxMAB* |1.7GHz|Single Core|Tj: (-40+125)|Full Feature|-|H: MIMX9332DVVxMAB* |1.7GHz|Dual Core|Tj: (0+95)|No NPU|-|I: MIMX9332CVVxMAB* |1.7GHz|Dual Core|Tj: (-40+105)|No NPU|-|J: MIMX9332XVVxMAB* |1.7GHz|Dual Core|Tj: (-40+125)|No NPU|-|K: MIMX9331DVVxMAB* |1.7GHz|Single Core|Tj: (0+95)|No NPU|-|L: MIMX9331CVVxMAB* |1.7GHz|Single Core|Tj: (-40+105)|No NPU|-|M: MIMX9331XVVxMAB* |1.7GHz|Single Core|Tj: (-40+125)|No NPU|-|N: MIMX9302DVVxDAB* |900 MHz|Dual Core|Tj: (0+95)|Reduced Features|-|O: MIMX9302CVVxDAB* |900 MHz|Dual Core|Tj: (-40+105)|Reduced Features|-|P: MIMX9301DVVxDAB* |900 MHz|Single Core|Tj: (0+95)|Reduced Features|-|Q: MIMX9301CVVxDAB* |900 MHz|Single Core|Tj: (-40+105)|Reduced Features|}
no edit summary
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
|-
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |{{oldid|17886|17886}}| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" | 152023/05/202317}}
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" | Preliminary information
|-
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" | {{oldid|18662|2023/08/31}}
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" | Official release
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" | 2024/02/09
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" | Added more details about P/N structure.
|}
<section end="History" />__FORCETOC__<section begin="Body" />
==Part number composition==
AURA SOM module part number is identified composed by several fields as follows. [Family][SOC][RAM][Storage][Boot Mode][RFU][RFU][Temperature range][PCB revision][Manufacturing option][Software Configuration] Each field is detailed in the following digit-code table:.{| class="wikitable" style="width:5053%" "
! style="width:10%" |Part number structure
! style="width:4050%" |Options
! style="width:20%" |Description
|-
!SOC
|
*
|These options depends on NXP P/N description [https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-9-processors/i-mx-93-applications-processor-family-arm-cortex-a55-ml-acceleration-power-efficient-mpu:i.MX93?tab=Buy_Parametric_Tab#/ available here]. Other versions can be available, please contact [https://www.dave.eu/helpdesk technical support]
* 1: on board eMMC
* 2: on board SPI NAND
|The boot modes listed here are "single boot", meaning that the Cortex-A55 is the first core to boot. Other options are available on-demand, however. DAVE Embedded Systems' team is available for additional information on this matter. If necessary, please contact [mailto:sales@dave.eu sales@dave.eu].
|-
!RFU
=== Example ===
AURA SOM code '''DAUA13100I0RDAUB13100I0R-00'''
* A - B MIMX9352DVVxMAB 1.7GHz Dual Core Tj: (0+95) Full Feature
* 1 - 1GB LPDDR4
* 3 - 8GB eMMC