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<section begin=Body/>
 
{{ImportantMessage|text=Vivado installation path, in this documentation, is the <code>/opt</code> directory. If you have chosen a different one, set it properly. The commands reported here below have been used on a native server running Ubuntu 20.04.}}
 
== Creating and building the Vivado project ==
* reproduce hardware design output (FPGA bitstream, XSA) using TCL scripts
To Development kit TCL scripts supported are the following one: {| class="wikitable"|-! Script! Boot|-| <code>recreate_prj_bora.tcl</code>| uSD and QSPI-NOR|-| <code>recreate_prj_borax_BASE.tcl</code>| uSD and QSPI-NOR|-| <code>recreate_prj_boralite_BASE.tcl</code>| uSD and QSPI-NOR|-| <code>recreate_prj_boralite_NAND.tcl</code>| uSD and NAND|} As an example, to reproduce the buildfor the ''Bora'' platform, user just need tohere below are the steps:
* clone the repository:
<syntaxhighlight lang="bash">
git clone git@git.dave.eu:sdv12desk-xz-l/vivado.git -b desk-xz7-l-rel-1.0.01
cd vivado
</syntaxhighlight>
* (only once as first tools setup) copy Bora hardware definition into or clone the Vivado installation.:repository when you clone Petalinux repository 
<syntaxhighlight lang="bash">
cp git clone -r boards-recursive git@git.dave.eu:desk-xz-l/ /opt/Xilinx/2021petalinux.git -b desk-xz7-l-1.2/Vivado/20210.2/data1cd petalinux/vivado
</syntaxhighlight>
 * lunch (only once as first tools setup) copy ''Bora'' hardware definition into Vivado Design Suite with the following commandinstallation path:
<syntaxhighlight lang="bash">
cp -r boards/ <vivado directory installation>/Xilinx/2021.2/Vivado/2021.2/data/</syntaxhighlight>* lunch Vivado Design Suite with the following commands and parameters:<syntaxhighlight lang="bash">source /opt<vivado directory installation>/Xilinx/2021.2/Vivado/2021.2/settings64.sh
vivado -mode tcl -source scripts/recreate_prj_bora_BASE.tcl -notrace -tclargs "gen_bitstream"
</syntaxhighlight>
* at the end of the bitstream build process, the script automatically exports the Xilinx Support Archive ('''XSA''') hardwaredesign** The the Vivado project ready for customization through Vivado GUI is available into <code>vivado/bora.xpr</code>is ready for customization through the Vivado GUI** The the bitstream file is now present infiles are
*** <code>vivado/bora.runs/impl_1/bora_wrapper.bit</code>
*** <code>vivado/bora.runs/impl_1/bora_wrapper.bin</code>
** The the hardware export, ready for import into Petalinux, is available in design file <code>vivado/bora.xsa</code>is ready for the import into Petalinux === CAN0 and UART0 routing example project === The following pictures show a simple PL design used to route PS' CAN0 and UART0 signals through EMIO. [[File:Belk-default-vivado-project.png|thumb|center|400px|Block diagram of BORA example project]][[File:Belk-borax-default-vivado-project.png|thumb|center|400px|Block diagram of BORA Xpress example project]][[File:Boralite-default-vivado-project.png|thumb|center|400px|Block diagram of BORA Lite example project]] 
<section end=Body/>
---- [[Category:BORA]] [[Category:BORA Xpress]][[Category:BORA Lite]]
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