Bureaucrats, dave_user, Administrators
8,286
edits
Changes
no edit summary
!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History
|-
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes
|-
|-
|}
__FORCETOC__
<section begin=Body/>
{{ImportantMessage|text=Vivado installation path, in this documentation, is the <code>/opt</code> directory. If you have chosen a different one, set it properly. The commands reported here below have been used on a native server running Ubuntu 20.04.}}
== Creating and building the Vivado project ==
* reproduce hardware design output (FPGA bitstream, XSA) using TCL scripts
As an example, to reproduce the build for the ''Bora'' platform, here below are the steps:
* clone the repository:
<pre classsyntaxhighlight lang="workstation-terminalbash">git clone git@git.dave.eu:sdv12desk-xz-l/vivado.git -b desk-xz7-l-rel-1.0.01
cd vivado
</presyntaxhighlight> or clone the Vivado repository when you clone Petalinux repository <syntaxhighlight lang="bash">git clone --recursive git@git.dave.eu:desk-xz-l/petalinux.git -b desk-xz7-l-1.0.1cd petalinux/vivado</syntaxhighlight> * (only once as first tools setup) copy ''Bora '' hardware definition into Vivado installation.path:<pre classsyntaxhighlight lang="workstation-terminalbash">cp -r boards/ /opt<vivado directory installation>/Xilinx/2021.2/Vivado/2021.2/data/</presyntaxhighlight>* lunch Vivado Design Suite with the following commandcommands and parameters:<pre classsyntaxhighlight lang="workstation-terminalbash">source /opt<vivado directory installation>/Xilinx/2021.2/Vivado/2021.2/settings64.sh
vivado -mode tcl -source scripts/recreate_prj_bora_BASE.tcl -notrace -tclargs "gen_bitstream"
</presyntaxhighlight>* at the end of the bitstream build process, the script automatically exports the Xilinx Support Archive ('''XSA''') hardwaredesign** The the Vivado project ready for customization through Vivado GUI is available into <code>vivado/bora.xpr</code>is ready for customization through the Vivado GUI** The the bitstream file is now present infiles are
*** <code>vivado/bora.runs/impl_1/bora_wrapper.bit</code>
*** <code>vivado/bora.runs/impl_1/bora_wrapper.bin</code>
** The the hardware export, ready for import into Petalinux, is available in design file <code>vivado/bora.xsa</code>is ready for the import into Petalinux === CAN0 and UART0 routing example project === The following pictures show a simple PL design used to route PS' CAN0 and UART0 signals through EMIO. [[File:Belk-default-vivado-project.png|thumb|center|400px|Block diagram of BORA example project]][[File:Belk-borax-default-vivado-project.png|thumb|center|400px|Block diagram of BORA Xpress example project]][[File:Boralite-default-vivado-project.png|thumb|center|400px|Block diagram of BORA Lite example project]]
[[Category:BORA]] [[Category:BORA Xpress]][[Category:BORA Lite]]