<section begin="History" />

!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History

!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Version!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes

|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|X.Y.Z2020/12/30|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Month Year|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|TBDFirst Release

<section end="History" /><section begin="Body" />

''TBD: qui di seguito vanno inserite le sezioni che includano la descrizione dei segnali coinvolti nella fase di Reset=== VDD ===Some signals that are related to reset circuitry are pulled-up to VDD rail. This voltage is generated by the PMIC and act as power good to switch on/off the all the peripheral that could back power the CPU. === NRST ===Open drain rest signal, ad esempio:tie to DGND to reset the system.

It is driven by:* MRSTthe PMIC to force the CPU in reset state* PORthe CPU over a soft reset to restart the application* SNVSThis signal is also used to reset the following on board peripherals:* SYSRSTSPI NOR* ...'''eMMC

=== PMIC_VSNVS NRST_CORE ===Some signals that are related Reset signal for the core, to be used if the VDD_CORE is not disabled during the reset circuitry are pulled-up to PMIC_VSNVS. This voltage is generated by PMIC PF0100's VSNVS LDO/Switch and its actual value depends on:* voltage applied to PMICS's VIN pin** in case of AxelLite this pin is connected to 3.3VIN power rail* voltage applied to PMICS's LICELL pin** in case of AxelLite this pin is connected to pin 14 of SODIMM connector (PMIC_LICELL)* PMIC's VSNVSCTL register configuration.Hence '''it is recommended that system designer takes into account these factors in order Internally tied to properly manage these signals at carrier board level'''NRST signal.

For more details please refer to section ''VSNVS LDO/Switch'' === PWR_ON ===Power on CPU output signal, The state of ''MMPF0100 Advance Information'' documentthis signal depends on power state of the processor.

=== CPU_PORn PDR_ON ===Input pin that disables the VDD internal voltage monitor. When this signal is set to logic 1 the processor does not issue a reset cycle when the VDD goes below the VVD_OK threshold.

The following devices can assert this active-low signal:* Driven by default by PMIC* multiple-voltage monitor: this device monitors critical power voltages and triggers a reset pulse in case any of these exhibits a brownout condition , internally used for deep sleep modes.

Since SPI NOR flash can be used as boot device, CPU_PORn === PDR_ON_CORE ===Input pin that disables the VDD_CORE internal voltage monitor. When this signal is connected set to this device too. This guarantees it is in logic 1 the processor does not issue a known state core reset cycle when reset signal is releasedthe VDD_CORE goes below the VVD_OK threshold.

=== Handling CPU-initiated software reset PWR_LP ==='''By default, MX6 processor does not assert any external signal when it initiates a software reset sequence. Also default software reset implementation does not guarantee that all processor registers are reset properly'''.

For these reasonsCPU low power mode output, it is strongly recommended internally used by the PMIC to use a different approach that, in combination with check the use of a processor's watchdog timer (WDT), provides a full hardware reset in case a software reset is issuedCPU low power state.

This technique is implemented in [[DESK-ETRA-L]]. At software level=== WAKEUP ===PMIC power on signal from CPU, U-Boot and Linux kernel software reset routines make use of processor's WDT #2 to assert the WDOG2_B reset signal. This signal used in turn is routed to GPIO_1 pad (MUX low power mode = 1). At hardware level, this signal is AC-coupled by the CPU internal RTC to a 3-state output buffer (please refer to U22 chip of [[AxelEVB-Lite]] carrier board), driving PMIC_PWRONrestart the PMIC.