Difference between revisions of "BORA Lite SOM/BORA Lite Evaluation Kit/Interfaces and Connectors/LVDS"
| (One intermediate revision by the same user not shown) | |||
| Line 1: | Line 1: | ||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
| − | |||
<section begin=Body/> | <section begin=Body/> | ||
| − | |||
{{#lst:BoraXEVB|LVDS}} | {{#lst:BoraXEVB|LVDS}} | ||
<section end=Body/> | <section end=Body/> | ||
Revision as of 13:23, 22 September 2021
| HOME | SOMs | SBCs | ToloMEO Embedded Assistant |  GET A QUOTE
|
 ONLINE HELPDESK
|
| Roadmap | IoT Services | ML/AI services | Embedded Design Services |
LVDS - J26[edit | edit source]
J26 is a vertical double row straight 20-pin 1.25mm pitch header. This interface shows how to implement a differential connection to an LCD screen. As known, Zynq does not implement an LCD controller, however this can be integrated in FPGA fabric as shown by this example: https://wiki.analog.com/resources/tools-software/linux-drivers/platforms/zynq. The following table reports the pinout of the connector:
| Pin# | Pin name | Function | Notes |
|---|---|---|---|
| 1, 2 | 3.3V_LCD | - | - |
| 3, 4, 7, 10, 13, 16, 19 |
DGND | Ground | - |
| 5 | LCD_LVDS_D0- | - | - |
| 6 | LCD_LVDS_D0+ | - | - |
| 8 | LCD_LVDS_D1- | - | - |
| 9 | LCD_LVDS_D1+ | - | - |
| 11 | LCD_LVDS_D2- | - | - |
| 12 | LCD_LVDS_D2+ | - | - |
| 14 | LCD_LVDS_CLK- | - | - |
| 15 | LCD_LVDS_CLK+ | - | - |
| 17 | LCD_P17 | - | - |
| 18 | LCD_P18 | - | - |
| 20 | LCD_P20 | - | - |
| 21,22 | DGND | Ground | Shield |
