Difference between revisions of "BORA Lite SOM/BORA Lite Evaluation Kit/General Information/Block Diagram and Features"

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!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes
 
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|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|New documentation layout
 
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{{#lst:BoraXEVB|Block Diagram}}
 
{{#lst:BoraXEVB|Block Diagram}}
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Revision as of 10:39, 22 September 2021


Block Diagram[edit | edit source]

The following picture shows BORA Xpress EVB block diagram:

BoraXEVB simplified block diagram

Configurable routing options[edit | edit source]

FPGA banks #12, #34 and #35 supports different routing options as shown in the following picture.

For a detailed description of FMC connector routing, please refer to this section.

BoraX[edit | edit source]

Configurable routing options diagram

Bora Lite[edit | edit source]

Configurable routing options diagram for BoraLite SoM