Difference between revisions of "Pinout (Bora)"

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(→‎SOM J2 EVEN pins (2 to 140) declaration)
(Replaced content with "{{subst:Pinout | nome-som=BORA | kit-code=BELK}}")
(Tag: Replaced)
(20 intermediate revisions by the same user not shown)
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−
<section begin="Body" />
+
<section begin=History/>
 +
{| style="border-collapse:collapse; "
 +
!colspan="4" style="width:100%; text-align:left"; border-bottom:solid 2px #ededed"|History
 +
|-
 +
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Version
 +
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Issue Date
 +
!style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white"|Notes
 +
|-
 +
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|X.Y.Z
 +
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Month Year
 +
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|TBD
 +
|-
 +
|-
 +
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|[TBD_link X.Y.Z]
 +
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|Month Year
 +
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|TBD
 +
|-
 +
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|...
 +
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|...
 +
|style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000"|...
 +
|-
 +
|}
 +
<section end=History/>
 +
<section begin=Body/>
 +
''TBD:  modificare la tabella seguente con le caratteristiche dei pin del SOM''
 +
 
 +
''TBD:  modificare le due tabelle ODD e EVEN con la mappa completa dei pins''
 +
 
 +
'''TBD:  nella tabella naming conventions,  inserire il codice dei vari IC presenti (PMIC, PHY ETH, ecc.)'''
 +
 
 
==Connectors and Pinout Table==
 
==Connectors and Pinout Table==
−
This chapter contains the pinout description of the Bora module, grouped in six tables (two – odd and even pins – for each connector) that report the pin mapping of the three 140-pin Bora connectors.
 
  
 
=== Connectors description ===
 
=== Connectors description ===
−
In the following table are described the interface connectors on [[:Category:Bora | Bora]] SOM:
+
In the following table are described all available connectors integrated on [[BORA]]:
 
{| class="wikitable"
 
{| class="wikitable"
 
|-
 
|-
Line 12: Line 40:
 
!Carrier board counterpart
 
!Carrier board counterpart
 
|-
 
|-
−
|J1, J2, J3
+
|J1
−
|Hirose FX8C-140S-SV<br>3x140 pins 0.6mm pitch connectors
+
|SODIMM DDR3 edge connector 204 pin
 
|
 
|
−
|Hirose FX8C-140P-SV''<x>''
+
|TE Connectivity 2-2013289-1
−
where ''<x''> stays for:
+
|-
−
* ''empty'' = 5 mm board-to-board height
+
|Jxx
−
* 1 = 6 mm board-to-board height
+
|TBD
−
* 2 = 7 mm board-to-board height
+
|TBD
−
* 4 = 9 mm board-to-board height
+
|TBD
−
* 6 = 11 mm board-to-board height
+
|-
 +
|Jxx
 +
|TBD
 +
|TBD
 +
|TBD
 +
|-
 +
|Jxx
 +
|TBD
 +
|TBD
 +
|TBD
 +
|-
 +
|Jxx
 +
|TBD
 +
|TBD
 +
|TBD
 
|}
 
|}
 
The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to BORA pinout specifications. See the images below for reference:
 
The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to BORA pinout specifications. See the images below for reference:
  
−
[[File:BORA_BOTTOM.png|700px|thumb|BORA BOTTOM view - J1, J2, J3 connectors (pins 1-139, 2-140)|none]]
+
[[File:BORA-top.png|500px|thumb|BORA TOP view|none]]
 +
[[File:BORA-bottom.png|500px|thumb|BORA BOTTOM view|none]]
  
 
===Pinout table naming conventions ===
 
===Pinout table naming conventions ===
 +
 +
This chapter contains the pinout description of the BORA module, grouped in two tables (odd and even pins) that report the pin mapping of the ''TBD: connector type'' BORA connector.
  
 
Each row in the pinout tables contains the following information:
 
Each row in the pinout tables contains the following information:
  
−
{| class="wikitable" style="width:50%;"
+
{|class="wikitable" style="width:50%;"
 
|-
 
|-
 
|'''Pin'''
 
|'''Pin'''
Line 37: Line 82:
 
|-
 
|-
 
|'''Pin Name'''  
 
|'''Pin Name'''  
−
| Pin (signal) name on the AxelLite connectors
+
| Pin (signal) name on the BORA connectors
 
|-
 
|-
 
|'''Internal<br>connections'''  
 
|'''Internal<br>connections'''  
−
| Connections to the components
+
| Connections to the BORA components
 
* CPU.<x> : pin connected to CPU pad named <x>
 
* CPU.<x> : pin connected to CPU pad named <x>
−
* CAN.<x> : pin connected to the CAN transceiver (TI SN65HVD232)
+
* CAN.<x> : pin connected to the CAN transceiver (''manufacturer'' ''part number'')
−
* LAN.<x> : pin connected to the LAN PHY (Microchip KSZ9031)
+
* PMIC.<x> : pin connected to the Power Manager IC (''manufacturer'' ''part number'')
−
* USB.<x>: pin connected to the USB PHY (Microchip USB3317)
+
* LAN.<x> : pin connected to the LAN PHY (''manufacturer'' ''part number'')
−
* NOR.<x>: pin connected to the NOR flash
+
* NOR.<x>: pin connected to the flash NOR
−
* NAND.<x>: pin connected to the NAND flash
+
* SV.<x>: pin connected to voltage supervisor
−
* IO_L<x>: pin connected to PL (FPGA)
 
 
* MTR: pin connected to voltage monitors
 
* MTR: pin connected to voltage monitors
−
* MON_<x>: pin for external voltage monitoring
 
 
|-
 
|-
 
|'''Ball/pin #'''  
 
|'''Ball/pin #'''  
 
| Component ball/pin number connected to signal
 
| Component ball/pin number connected to signal
 
|-
 
|-
−
|'''Voltage''' || I/O voltage levels
+
|'''Voltage''' || I/O voltage levels  
−
* 1.8V
 
−
* 3.3V
 
−
* U.D. = User Defined
 
 
|-
 
|-
 
|'''Type'''  
 
|'''Type'''  
Line 68: Line 108:
 
* G = Ground
 
* G = Ground
 
* A = Analog signal
 
* A = Analog signal
−
* A/G = Analog Ground
 
 
|-
 
|-
 
|'''Notes'''
 
|'''Notes'''
 
|Remarks on special pin characteristics
 
|Remarks on special pin characteristics
 +
|-
 +
|'''Pin MUX alternative functions'''
 +
|Muxes:
 +
* Pin ALT-0
 +
* ...
 +
* Pin ALT-N
 +
The number of functions depends on platform
 
|-
 
|-
 
|}
 
|}
  
−
==SOM J1 ODD pins (1 to 139) declaration ==
+
==Pinout Table ODD pins declaration ==
  
−
{| class="wikitable" {| {{table}}
+
{| class="wikitable"  
−
| style="background:#f0f0f0;" align="center" |'''Pin'''
+
! latexfontsize="scriptsize"| Pin
−
| style="background:#f0f0f0;" align="center" |'''Pin Name'''
+
! latexfontsize="scriptsize"| Pin Name
−
| style="background:#f0f0f0;" align="center" |'''Internal Connections'''
+
! latexfontsize="scriptsize"| Internal Connections
−
| style="background:#f0f0f0;" align="center" |'''Ball/pin #'''
+
! latexfontsize="scriptsize"| Ball/pin #  
−
| style="background:#f0f0f0;" align="center" |'''Supply Group'''
+
! latexfontsize="scriptsize"| Voltage domain
−
| style="background:#f0f0f0;" align="center" |'''Type'''
+
! latexfontsize="scriptsize"| Type
−
| style="background:#f0f0f0;" align="center" |'''Voltage'''
+
! latexfontsize="scriptsize"| Notes
−
| style="background:#f0f0f0;" align="center" |'''Note'''
+
! colspan="2" latexfontsize="scriptsize"| Alternative Functions
 +
|-
 +
|rowspan="5"|J1.1
 +
|rowspan="5"|SD2_CMD
 +
|rowspan="5"|CPU.SD2_CMD
 +
|rowspan="5"|F19
 +
|rowspan="5"|AXEL_IO_3V3
 +
|rowspan="5"|IO
 +
|rowspan="5"|Notes
 +
|Pin ALT-0
 +
|SD2_CMD
 +
|-
 +
|Pin ALT-1
 +
|ECSPI5_MOSI
 +
|-
 +
|Pin ALT-2
 +
|KEY_ROW5
 +
|-
 +
|Pin ALT-3
 +
|AUD4_RXC
 +
|-
 +
|Pin ALT-5
 +
|GPIO1_IO11
 +
|-
 +
|rowspan="5"|J1.3
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.5
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.7
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.9
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.11
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.13
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.15
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.17
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.19
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.21
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.23
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.25
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.27
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.29
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.31
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.33
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.35
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.37
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.39
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.31
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.33
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.35
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.37
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.39
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.41
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.43
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.45
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.47
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.49
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.51
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.53
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.55
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.57
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.59
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.61
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.63
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.65
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.67
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.69
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.71
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.73
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.75
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.77
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.79
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.81
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.83
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.85
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.87
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.89
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.91
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.93
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.95
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.97
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.99
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.101
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.103
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.105
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.107
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.109
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.111
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.113
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.115
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.117
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.119
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.121
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.123
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.125
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.127
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.129
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.131
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.133
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.135
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.137
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.139
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.141
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.143
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J1.1||DGND||DGND||-||||G||||
+
|rowspan="5"|J1.145
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J1.3||IO_L7P_T1_AD2P_35||FPGA.IO_L7P_T1_AD2P_35||M19||BANK35
+
|Pin ALT-1
−
|I/O
+
|TBD
−
|U.D.||
 
 
|-
 
|-
−
|J1.5||IO_L10P_T1_AD11P_35||FPGA.IO_L10P_T1_AD11P_35||K19||BANK35
+
|Pin ALT-2
−
|I/O
+
|TBD
−
|U.D.||
 
 
|-
 
|-
−
|J1.7||IO_L11P_T1_SRCC_35||FPGA.IO_L11P_T1_SRCC_35||L16||BANK35
+
|Pin ALT-3
−
|I/O
+
|TBD
−
|U.D.||
 
 
|-
 
|-
−
|J1.9||IO_L8N_T1_AD10N_35||FPGA.IO_L8N_T1_AD10N_35||M18||BANK35
+
|Pin ALT-5
−
|I/O
+
|TBD
−
|U.D.||
 
 
|-
 
|-
−
|J1.11||IO_L7N_T1_AD2N_35||FPGA.IO_L7N_T1_AD2N_35||M20||BANK35
+
|rowspan="5"|J1.147
−
|I/O
+
|rowspan="5"|TBD
−
|U.D.||
+
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J1.13||DGND||DGND||-||||G||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J1.15||IO_L9P_T1_DQS_AD3P_35||FPGA.IO_L9P_T1_DQS_AD3P_35||L19||BANK35
+
|Pin ALT-2
−
|I/O
+
|TBD
−
|U.D.||
 
 
|-
 
|-
−
|J1.17||IO_L9N_T1_DQS_AD3N_35||FPGA.IO_L9N_T1_DQS_AD3N_35||L20||BANK35
+
|Pin ALT-3
−
|I/O
+
|TBD
−
|U.D.||
 
 
|-
 
|-
−
|J1.19||DGND||DGND||-||||G||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J1.21||IO_L20P_T3_AD6P_35||FPGA.IO_L20P_T3_AD6P_35||K14||BANK35
+
|rowspan="5"|J1.149
−
|I/O
+
|rowspan="5"|TBD
−
|U.D.||
+
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J1.23||IO_L20N_T3_AD6N_35||FPGA.IO_L20N_T3_AD6N_35||J14||BANK35
+
|Pin ALT-1
−
|I/O
+
|TBD
−
|U.D.||
 
 
|-
 
|-
−
|J1.25||IO_L22P_T3_AD7P_35||FPGA.IO_L22P_T3_AD7P_35||L14||BANK35
+
|Pin ALT-2
−
|I/O
+
|TBD
−
|U.D.||
 
 
|-
 
|-
−
|J1.27||IO_L12N_T1_MRCC_35||FPGA.IO_L12N_T1_MRCC_35||K18||BANK35
+
|Pin ALT-3
−
|I/O
+
|TBD
−
|U.D.||
 
 
|-
 
|-
−
|J1.29||DGND||DGND||-||||G||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J1.31||IO_L21P_T3_DQS_AD14P_35||FPGA.IO_L21P_T3_DQS_AD14P_35||N15||BANK35
+
|rowspan="5"|J1.151
−
|I/O
+
|rowspan="5"|TBD
−
|U.D.||
+
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J1.33||IO_L21N_T3_DQS_AD14N_35||FPGA.IO_L21N_T3_DQS_AD14N_35||N16||BANK35
+
|Pin ALT-1
−
|I/O
+
|TBD
−
|U.D.||
 
 
|-
 
|-
−
|J1.35||DGND||DGND||-||||G||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J1.37||IO_L17N_T2_AD5N_35||FPGA.IO_L17N_T2_AD5N_35||H20||BANK35
+
|Pin ALT-3
−
|I/O
+
|TBD
−
|U.D.||
 
 
|-
 
|-
−
|J1.39||IO_L13N_T2_MRCC_35||FPGA.IO_L13N_T2_MRCC_35||H17||BANK35
+
|Pin ALT-5
−
|I/O
+
|TBD
−
|U.D.||
 
 
|-
 
|-
−
|J1.41||IO_L19P_T3_35||FPGA.IO_L19P_T3_35||H15||BANK35
+
|rowspan="5"|J1.153
−
|I/O
+
|rowspan="5"|TBD
−
|U.D.||
+
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J1.43||IO_L18P_T2_AD13P_35||FPGA.IO_L18P_T2_AD13P_35||G19||BANK35
+
|Pin ALT-1
−
|I/O
+
|TBD
−
|U.D.||
 
 
|-
 
|-
−
|J1.45||IO_L16P_T2_35||FPGA.IO_L16P_T2_35||G17||BANK35
+
|Pin ALT-2
−
|I/O
+
|TBD
−
|||
 
 
|-
 
|-
−
|J1.47||IO_L15N_T2_DQS_AD12N_35||FPGA.IO_L15N_T2_DQS_AD12N_35||F20||BANK35
+
|Pin ALT-3
−
|I/O
+
|TBD
−
|U.D.||
 
 
|-
 
|-
−
|J1.49||DGND||DGND||-||||G||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J1.51||IO_L2N_T0_AD8N_35||FPGA.IO_L2N_T0_AD8N_35||A20||BANK35
+
|rowspan="5"|J1.155
−
|I/O
+
|rowspan="5"|TBD
−
|U.D.||
+
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J1.53||IO_L1N_T0_AD0N_35||FPGA.IO_L1N_T0_AD0N_35||B20||BANK35
+
|Pin ALT-1
−
|I/O
+
|TBD
−
|U.D.||
 
 
|-
 
|-
−
|J1.55||IO_L5N_T0_AD9N_35||FPGA.IO_L5N_T0_AD9N_35||E19||BANK35
+
|Pin ALT-2
−
|I/O
+
|TBD
−
|U.D.||
 
 
|-
 
|-
−
|J1.57||IO_L5P_T0_AD9P_35||FPGA.IO_L5P_T0_AD9P_35||E18||BANK35
+
|Pin ALT-3
−
|I/O
+
|TBD
−
|U.D.||
 
 
|-
 
|-
−
|J1.59||DGND||DGND||-||||G||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J1.61||IO_L3P_T0_DQS_AD1P_35||FPGA.IO_L3P_T0_DQS_AD1P_35||E17||BANK35
+
|rowspan="5"|J1.157
−
|I/O
+
|rowspan="5"|TBD
−
|U.D.||
+
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J1.63||IO_L3N_T0_DQS_AD1N_35||FPGA.IO_L3N_T0_DQS_AD1N_35||D18||BANK35
+
|Pin ALT-1
−
|I/O
+
|TBD
−
|U.D.||
 
 
|-
 
|-
−
|J1.65||DGND||DGND||-||||G||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J1.67||VDDIO_BANK35||FPGA.VCCO_35||C19<br>F18<br>H14<br>J17<br>K20<br>M16||BANK35
+
|Pin ALT-3
−
|S||||User Defined: 1.8V to 3.3V (see [[Programmable logic (Bora)#Introduction|Programmable logic (Bora)]] )
+
|TBD
 
|-
 
|-
−
|J1.69||XADC_AGND||FPGA.GNDADC_0||J10||||A / G||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J1.71||XADC_AGND||FPGA.GNDADC_0||J10||||A / G||||
+
|rowspan="5"|J1.159
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J1.73||PS_MIO45_501 ||CPU.PS_MIO45_501||B15||BANK501
+
|Pin ALT-1
−
|I/O
+
|TBD
−
|1.8V
+
|-
−
|
+
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.161
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.163
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.165
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.167
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.169
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.171
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.173
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.175
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.177
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.179
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.181
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.183
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.185
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.187
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.189
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.191
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J1.75||PS_MIO44_501||CPU.PS_MIO44_501||F13||BANK501
+
|Pin ALT-2
−
|I/O
+
|TBD
−
|1.8V
 
−
|
 
 
|-
 
|-
−
|J1.77||PS_MIO43_501||CPU.PS_MIO43_501||A9||BANK501
+
|Pin ALT-3
−
|I/O
+
|TBD
−
|1.8V
 
−
|
 
 
|-
 
|-
−
|J1.79||PS_MIO42_501||CPU.PS_MIO42_501||E12||BANK501
+
|Pin ALT-5
−
|I/O
+
|TBD
−
|1.8V
 
−
|
 
 
|-
 
|-
−
|J1.81||PS_MIO41_501||CPU.PS_MIO41_501||C17||BANK501
+
|rowspan="5"|J1.193
−
|I/O
+
|rowspan="5"|TBD
−
|1.8V
+
|rowspan="5"|TBD
−
|
+
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J1.83||DGND||DGND||-||||G||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J1.85||PS_MIO40_501||CPU.PS_MIO40_501||D14||BANK501
+
|Pin ALT-2
−
|I/O
+
|TBD
−
|1.8V
 
−
|
 
 
|-
 
|-
−
|J1.87||ETH_MDIO||CPU.PS_MIO53_501<br>LAN.MDIO||C11<br>37||BANK501
+
|Pin ALT-3
−
|I/O
+
|TBD
−
|1.8V
 
−
|
 
 
|-
 
|-
−
|J1.89||ETH_MDC||CPU.PS_MIO12_501<br>LAN.MDC||C10<br>36||BANK501
+
|Pin ALT-5
−
|I/O
+
|TBD
−
|1.8V
 
−
|
 
 
|-
 
|-
−
|J1.91||ETH_LED1||LAN.LED1 / PME_N1||17||||I/O||1.8V||Internal 10K pull-up to DVDDH (i.e. PHYAD0 = 1) . Level translator needed if used @ 3V3
+
|rowspan="5"|J1.195
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J1.93||ETH_LED2||LAN.LED2||15||||I/O||1.8V||Internal 10K pull-up to DVDDH (i.e. PHYAD1 = 1) . Level translator needed if used @ 3V3
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J1.95||DGND||DGND||-||||G||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J1.97||ETH_TXRX1_M||LAN.TXRXM_B||6||||D||3.3V||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J1.99||ETH_TXRX1_P||LAN.TXRXP_B||5||||D||3.3V||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J1.101||DGND||DGND||-||||G||||
+
|rowspan="5"|J1.197
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J1.103||ETH_TXRX0_M||LAN.TXRXM_A||3||||D||3.3V||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J1.105||ETH_TXRX0_P||LAN.TXRXP_A||2||||D||3.3V||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J1.107||D.N.C||-|||||||| ||Do Not Connect (reserved for internal use)
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J1.109||N.C.||Not Connected||-||||||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J1.111||USBOTG_CPEN||USB.CPEN||7||||O||1.8V||External 5V suply enable. For further details, please refer to the Microchip USB3317 datasheet.
+
|rowspan="5"|J1.199
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J1.113||OTG_VBUS||USB.OTG_VBUS||2||||I/O||5V||USB VBUS comparator. For further details, please refer to the Microchip USB3317 datasheet.
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J1.115||OTG_ID||USB.ID||1||||I||5V||ID of the USB cable. For further details, please refer to the Microchip USB3317 datasheet.
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J1.117||DGND||DGND||-||||G||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J1.119||SPI0_DQ3/MODE0/NAND_IO0||CPU.PS_MIO5_500||A6||BANK500
+
|Pin ALT-5
−
|I/O||3.3V
+
|TBD
−
| Internally connected as NAND I/O (if populated)
 
−
This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)
 
 
|-
 
|-
−
|J1.121||SPI0_DQ2/MODE2/NAND_IO2||CPU.PS_MIO4_500||B7||BANK500
+
|rowspan="5"|J1.201
−
|I/O||3.3V
+
|rowspan="5"|TBD
−
| Internally connected as NAND I/O (if populated)
+
|rowspan="5"|TBD
−
This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)
+
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J1.123||SPI0_DQ1/MODE1/NAND_WE||CPU.PS_MIO3_500||D6||BANK500
+
|Pin ALT-1
−
|I/O||3.3V
+
|TBD
−
| Internally connected as NAND I/O (if populated)
 
−
This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)
 
 
|-
 
|-
−
|J1.125||SPI0_DQ0/MODE3/NAND_ALE||CPU.PS_MIO2_500||B8||BANK500
+
|Pin ALT-2
−
|I/O||3.3V
+
|TBD
−
| Internally connected as NAND I/O (if populated)
 
−
This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)
 
 
|-
 
|-
−
|J1.127||DGND||DGND||-||||G||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J1.129||SPI0_SCLK/MODE4/NAND_IO1||CPU.PS_MIO6_500||A5||BANK500
+
|Pin ALT-5
−
|I/O||3.3V
+
|TBD
−
| Internally connected as NAND I/O (if populated)
 
−
This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)
 
 
|-
 
|-
−
|J1.131||NAND_BUSY||CPU.PS_MIO14_500||C5||BANK500
+
|rowspan="5"|J1.203
−
|I/O||3.3V
+
|rowspan="5"|TBD
−
|Internally connected as NAND I/O (if populated)
+
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J1.133||PS_MIO15_500||CPU.PS_MIO15_500<br>WDT.WDI||C8<br>1||BANK500
+
|Pin ALT-1
−
|I/O||3.3V
+
|TBD
−
|See also [[Watchdog_(Bora)|this page]]
 
 
|-
 
|-
−
|J1.135||N.C.||Not Connected||-||||||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J1.137||MEM_WPN||NAND.WP - NOR.WP/IO2||19 - C4||||I/O||||Internally connected to NAND and NOR WP
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J1.139||DGND||DGND||-||||G||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
 
|}
 
|}
  
−
==SOM J1 EVEN pins (2 to 140) declaration ==
+
==Pinout Table EVEN pins declaration ==
  
−
{| class="wikitable" {| {{table}}
+
{| class="wikitable"  
−
| style="background:#f0f0f0;" align="center" |'''Pin'''
+
! latexfontsize="scriptsize"| Pin
−
| style="background:#f0f0f0;" align="center" |'''Pin Name'''
+
! latexfontsize="scriptsize"| Pin Name
−
| style="background:#f0f0f0;" align="center" |'''Internal Connections'''
+
! latexfontsize="scriptsize"| Internal Connections
−
| style="background:#f0f0f0;" align="center" |'''Ball/pin #'''
+
! latexfontsize="scriptsize"| Ball/pin #  
−
| style="background:#f0f0f0;" align="center" |'''Supply Group'''
+
! latexfontsize="scriptsize"| Voltage domain
−
| style="background:#f0f0f0;" align="center" |'''Type'''
+
! latexfontsize="scriptsize"| Type
−
| style="background:#f0f0f0;" align="center" |'''Voltage'''
+
! latexfontsize="scriptsize"| Notes
−
| style="background:#f0f0f0;" align="center" |'''Note'''
+
! colspan="2" latexfontsize="scriptsize"| Alternative Functions
 +
|-
 +
|rowspan="5"|J1.1
 +
|rowspan="5"|SD2_CMD
 +
|rowspan="5"|CPU.SD2_CMD
 +
|rowspan="5"|F19
 +
|rowspan="5"|AXEL_IO_3V3
 +
|rowspan="5"|IO
 +
|rowspan="5"|Notes
 +
|Pin ALT-0
 +
|SD2_CMD
 +
|-
 +
|Pin ALT-1
 +
|ECSPI5_MOSI
 +
|-
 +
|Pin ALT-2
 +
|KEY_ROW5
 +
|-
 +
|Pin ALT-3
 +
|AUD4_RXC
 +
|-
 +
|Pin ALT-5
 +
|GPIO1_IO11
 +
|-
 +
|rowspan="5"|J1.3
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.5
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.7
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.9
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.11
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.13
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.15
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.17
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.19
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.21
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.23
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.25
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.27
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.29
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.31
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.33
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J1.2||VDDIO_BANK35||FPGA.VCCO_35||C19<br>F18<br>H14<br>J17<br>K20<br>M16||BANK35
+
|Pin ALT-3
−
|S||||User Defined: 1.8V to 3.3V (see [[Programmable logic (Bora)#Introduction|Programmable logic (Bora)]] )
+
|TBD
 
|-
 
|-
−
|J1.4||DGND||DGND||-||||G||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J1.6||IO_L10N_T1_AD11N_35||FPGA.IO_L10N_T1_AD11N_35||J19||BANK35
+
|rowspan="5"|J1.35
−
|I/O||U.D.||
+
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J1.8||IO_L12P_T1_MRCC_35||FPGA.IO_L12P_T1_MRCC_35||K17||BANK35
+
|Pin ALT-1
−
|I/O||U.D.||
+
|TBD
 
|-
 
|-
−
|J1.10||IO_L11N_T1_SRCC_35||FPGA.IO_L11N_T1_SRCC_35||L17||BANK35
+
|Pin ALT-2
−
|I/O||U.D.||
+
|TBD
 
|-
 
|-
−
|J1.12||IO_L8P_T1_AD10P_35||FPGA.IO_L8P_T1_AD10P_35||M17||BANK35
+
|Pin ALT-3
−
|I/O||U.D.||
+
|TBD
 
|-
 
|-
−
|J1.14||DGND||DGND||-||||G||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J1.16||IO_L24N_T3_AD15N_35||FPGA.IO_L24N_T3_AD15N_35||J16||BANK35
+
|rowspan="5"|J1.37
−
|I/O||U.D.||
+
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J1.18||IO_25_35||FPGA.IO_25_35||J15||BANK35
+
|Pin ALT-1
−
|I/O||U.D.||
+
|TBD
 
|-
 
|-
−
|J1.20||IO_L24P_T3_AD15P_35||FPGA.IO_L24P_T3_AD15P_35||K16||BANK35
+
|Pin ALT-2
−
|I/O||U.D.||
+
|TBD
 
|-
 
|-
−
|J1.22||IO_L23N_T3_35||FPGA.IO_L23N_T3_35||M15||BANK35
+
|Pin ALT-3
−
|I/O||U.D.||
+
|TBD
 
|-
 
|-
−
|J1.24||DGND||DGND||-||||G||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J1.26||IO_L22N_T3_AD7N_35||FPGA.IO_L22N_T3_AD7N_35||L15||BANK35
+
|rowspan="5"|J1.39
−
|I/O||U.D.||
+
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J1.28||IO_L23P_T3_35||FPGA.IO_L23P_T3_35||M14||BANK35
+
|Pin ALT-1
−
|I/O||U.D.||
+
|TBD
 
|-
 
|-
−
|J1.30||DGND||DGND||-||||G||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J1.32||IO_L17P_T2_AD5P_35||FPGA.IO_L17P_T2_AD5P_35||J20||BANK35
+
|Pin ALT-3
−
|I/O||U.D.||
+
|TBD
 
|-
 
|-
−
|J1.34||IO_L14P_T2_AD4P_SRCC_35||FPGA.IO_L14P_T2_AD4P_SRCC_35||J18||BANK35
+
|Pin ALT-5
−
|I/O||U.D.||
+
|TBD
 
|-
 
|-
−
|J1.36||IO_L14N_T2_AD4N_SRCC_35||FPGA.IO_L14N_T2_AD4N_SRCC_35||H18||BANK35
+
|rowspan="5"|J1.31
−
|I/O||U.D.||
+
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J1.38||DGND||DGND||-||||G||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J1.40||IO_L13P_T2_MRCC_35||FPGA.IO_L13P_T2_MRCC_35||H16||BANK35
+
|Pin ALT-2
−
|I/O||U.D.||
+
|TBD
 
|-
 
|-
−
|J1.42||IO_L18N_T2_AD13N_35||FPGA.IO_L18N_T2_AD13N_35||G20||BANK35
+
|Pin ALT-3
−
|I/O||U.D.||
+
|TBD
 
|-
 
|-
−
|J1.44||IO_L16N_T2_35||FPGA.IO_L16N_T2_35||G18||BANK35
+
|Pin ALT-5
−
|I/O||U.D.||
+
|TBD
 
|-
 
|-
−
|J1.46||IO_L15P_T2_DQS_AD12P_35||FPGA.IO_L15P_T2_DQS_AD12P_35||F19||BANK35
+
|rowspan="5"|J1.33
−
|I/O||U.D.||
+
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J1.48||DGND||DGND||-||||G||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J1.50||IO_L1P_T0_AD0P_35||FPGA.IO_L1P_T0_AD0P_35||C20||BANK35
+
|Pin ALT-2
−
|I/O||U.D.||
+
|TBD
 
|-
 
|-
−
|J1.52||IO_L2P_T0_AD8P_35||FPGA.IO_L2P_T0_AD8P_35||B19||BANK35
+
|Pin ALT-3
−
|I/O||U.D.||
+
|TBD
 
|-
 
|-
−
|J1.54||IO_L4N_T0_35||FPGA.IO_L4N_T0_35||D20||BANK35
+
|Pin ALT-5
−
|I/O||U.D.||
+
|TBD
 
|-
 
|-
−
|J1.56||IO_L4P_T0_35||FPGA.IO_L4P_T0_35||D19||BANK35
+
|rowspan="5"|J1.35
−
|I/O||U.D.||
+
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J1.58||IO_L6P_T0_35||FPGA.IO_L6P_T0_35||F16||BANK35
+
|Pin ALT-1
−
|I/O||U.D.||
+
|TBD
 
|-
 
|-
−
|J1.60||DGND||DGND||-||||G||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J1.62||IO_L6N_T0_VREF_35||FPGA.IO_L6N_T0_VREF_35||F17||BANK35
+
|Pin ALT-3
−
|I/O||U.D.||
+
|TBD
 
|-
 
|-
−
|J1.64||IO_L19N_T3_VREF_35||FPGA.IO_L19N_T3_VREF_35||G15||BANK35
+
|Pin ALT-5
−
|I/O||U.D.||
+
|TBD
 
|-
 
|-
−
|J1.66||VDDIO_BANK35||FPGA.VCCO_35||C19<br>F18<br>H14<br>J17<br>K20<br>M16||BANK35
+
|rowspan="5"|J1.37
−
|S||||User Defined: 1.8V to 3.3V (see [[Programmable logic (Bora)#Introduction|Programmable logic (Bora)]] )
+
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J1.68||VDDIO_BANK35||FPGA.VCCO_35||C19<br>F18<br>H14<br>J17<br>K20<br>M16||BANK35
+
|Pin ALT-1
−
|S||||User Defined: 1.8V to 3.3V (see [[Programmable logic (Bora)#Introduction|Programmable logic (Bora)]] )
+
|TBD
 
|-
 
|-
−
|J1.70||XADC_AGND||FPGA.GNDADC_0||J10||||A/G||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J1.72||XADC_AGND||FPGA.GNDADC_0||J10||||A/G||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J1.74||IO_0_35||FPGA.IO_0_35||G14||BANK35||I/O||U.D.||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J1.76||N.C.||Not Connected||-||||||||
+
|rowspan="5"|J1.39
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J1.78||N.C.||Not Connected||-||||||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J1.80||PS_MIO49_501||CPU.PS_MIO49_501||C12||BANK501||I/O||1.8V||Configured as UART1_RX on BELK BSP
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J1.82||PS_MIO48_501||CPU.PS_MIO48_501||B12||BANK501||I/O||1.8V||Configured as UART1_TX on BELK BSP
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J1.84||PS_MIO47_501||CPU.PS_MIO47_501||B14||BANK501||I/O||1.8V||Internally connected as I2C0_SDA (10K pull-up)
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J1.86||DGND||DGND||-||||G||||
+
|rowspan="5"|J1.41
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J1.88||PS_MIO46_501||CPU.PS_MIO46_501||D16||BANK501||I/O||1.8V||Internally connected as I2C0_CLK (10K pull-up)
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J1.90||ETH_INTN||LAN.INT_N / PME_N2||38||||O||1.8V||Internal pull-up 4K7 (by default not connected)
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J1.92||DGND||DGND||-||||G||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J1.94||ETH_TXRX3_M||LAN.TXRXM_D||11||||D||3.3V||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J1.96||ETH_TXRX3_P||LAN.TXRXP_D||10||||D||3.3V||
+
|rowspan="5"|J1.43
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J1.98||DGND||DGND||-||||G||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J1.100||ETH_TXRX2_M||LAN.TXRXM_C||8||||D||3.3V||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J1.102||ETH_TXRX2_P||LAN.TXRXP_C||7||||D||3.3V||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J1.104||DGND||DGND||-||||G||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J1.106||CLK125_NDO||LAN.CLK125_NDO||41||||I/O||1.8V||
+
|rowspan="5"|J1.45
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J1.108||N.C.||Not Connected||-||||||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J1.110||N.C.||Not Connected||-||||||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J1.112||DGND||DGND||-||||G||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J1.114||USBP1||USB.DP||6||||D||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J1.116||USBM1||USB.DM||5||||D||||
+
|rowspan="5"|J1.47
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J1.118||DGND||DGND||-||||G||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J1.120||SPI0_CS0N||CPU.PS_MIO1_500<br>NOR.CS#||A7<br>C2||BANK500
+
|Pin ALT-2
−
|I/O||3.3V
+
|TBD
−
|Internally connected as NOR chip select (if populated)
 
 
|-
 
|-
−
|J1.122||NAND_CS0/SPI0_CS1||CPU.PS_MIO0_500<br>NAND.~CE||E6<br>9||BANK500
+
|Pin ALT-3
−
|I/O||3.3V
+
|TBD
−
|Internally connected as NAND chip select (if populated)
 
 
|-
 
|-
−
|J1.124||NAND_IO3||CPU.PS_MIO13_500<br>NAND.I/O3||E8<br>32||BANK500
+
|Pin ALT-5
−
|I/O||3.3V
+
|TBD
−
|Internally connected as NAND I/O (if populated)
 
 
|-
 
|-
−
|J1.126||NAND_IO4||CPU.PS_MIO9_500<br>NAND.I/O4||B5<br>41||BANK500
+
|rowspan="5"|J1.49
−
|I/O||3.3V
+
|rowspan="5"|TBD
−
|Internally connected as NAND I/O (if populated)
+
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J1.128||NAND_IO5||CPU.PS_MIO10_500<br>NAND.I/O5||E9<br>42||BANK500
+
|Pin ALT-1
−
|I/O||3.3V
+
|TBD
−
|Internally connected as NAND I/O (if populated)
 
 
|-
 
|-
−
|J1.130||DGND||DGND||-||||G||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J1.132||NAND_IO6||CPU.PS_MIO11_500<br>NAND.I/O6||C6<br>43||BANK500
+
|Pin ALT-3
−
|I/O||3.3V
+
|TBD
−
|Internally connected as NAND I/O (if populated)
 
 
|-
 
|-
−
|J1.134||NAND_IO7||CPU.PS_MIO12_500<br>NAND.I/O7||D9<br>44||BANK500
+
|Pin ALT-5
−
|I/O||3.3V
+
|TBD
−
|Internally connected as NAND I/O (if populated)
 
 
|-
 
|-
−
|J1.136||NAND_RD_B/VCFG1||CPU.PS_MIO8_500<br>NAND.~RE||D5<br>8||BANK500
+
|rowspan="5"|J1.51
−
|I/O||3.3V
+
|rowspan="5"|TBD
−
| This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)
+
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J1.138||NAND_CLE/VCFG0||CPU.PS_MIO7_500<br>NAND.CLE||D8<br>16||BANK500
+
|Pin ALT-1
−
|I/O||3.3V
+
|TBD
−
| This signal is internally pulled up or down by 20kOhm resistor depending on order code (selecting then the bootstrap configuration)
 
 
|-
 
|-
−
|J1.140||DGND||DGND||-||||G||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|}
+
|Pin ALT-3
−
 
+
|TBD
−
==SOM J2 ODD pins (1 to 139) declaration ==
+
|-
−
 
+
|Pin ALT-5
−
{| class="wikitable" {| {{table}}
+
|TBD
−
| style="background:#f0f0f0;" align="center" |'''Pin'''
+
|-
−
| style="background:#f0f0f0;" align="center" |'''Pin Name'''
+
|rowspan="5"|J1.53
−
| style="background:#f0f0f0;" align="center" |'''Internal Connections'''
+
|rowspan="5"|TBD
−
| style="background:#f0f0f0;" align="center" |'''Ball/pin #'''
+
|rowspan="5"|TBD
−
| style="background:#f0f0f0;" align="center" |'''Supply Group'''
+
|rowspan="5"|TBD
−
| style="background:#f0f0f0;" align="center" |'''Type'''
+
|rowspan="5"|TBD
−
| style="background:#f0f0f0;" align="center" |'''Voltage'''
+
|rowspan="5"|TBD
−
| style="background:#f0f0f0;" align="center" |'''Note'''
+
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.55
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.57
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.59
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.61
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.63
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.65
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.67
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.69
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.71
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.73
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.75
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.77
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.79
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.81
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.83
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.85
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.87
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.89
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
|rowspan="5"|J1.91
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 +
|-
 +
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J2.1||DGND||DGND||-||||G||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J2.3||DGND||DGND||-||||G||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J2.5||IO_L8P_T1_34||FPGA.IO_L8P_T1_34||W14||BANK34||I/O||3.3V||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J2.7||IO_L8N_T1_34||FPGA.IO_L8N_T1_34||Y14||BANK34||I/O||3.3V||
+
|rowspan="5"|J1.93
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J2.9||IO_L6P_T0_34||CAN.D<br>FPGA.IO_L6P_T0_34||1<br>P14||BANK34||I/O||3.3V||By default used as CAN.TX with internal CAN PHY transceiver (mount option)
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J2.11||IO_L6N_T0_VREF_34||FPGA.IO_L6N_T0_VREF_34||R14||BANK34||I/O||3.3V||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J2.13||DGND||DGND||-||||G||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J2.15||IO_L3P_T0_DQS_PUDC_B_34||FPGA.IO_L3P_T0_DQS_PUDC_B_34||U13||BANK34||I/O||3.3V||Internal 10K resistor pull-up
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J2.17||IO_L3N_T0_DQS_34||FPGA.IO_L3N_T0_DQS_34||V13||BANK34||I/O||3.3V||
+
|rowspan="5"|J1.95
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J2.19||IO_L2P_T0_34||FPGA.IO_L2P_T0_34||T12||BANK34||I/O||3.3V||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J2.21||IO_L2N_T0_34||FPGA.IO_L2N_T0_34||U12||BANK34||I/O||3.3V||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J2.23||DGND||DGND||-||||G||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J2.25||IO_L22P_T3_34||FPGA.IO_L22P_T3_34||W18||BANK34||I/O||3.3V||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J2.27||IO_L22N_T3_34||FPGA.IO_L22N_T3_34||W19||BANK34||I/O||3.3V||
+
|rowspan="5"|J1.97
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J2.29||IO_L21P_T3_DQS_34||FPGA.IO_L21P_T3_DQS_34||V17||BANK34||I/O||3.3V||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J2.31||IO_L21N_T3_DQS_34||FPGA.IO_L21N_T3_DQS_34||V18||BANK34||I/O||3.3V||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J2.33||DGND||DGND||-||||G||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J2.35||IO_L19P_T3_34||CAN.R<br>FPGA.IO_L19P_T3_34||4<br>R16||BANK34||I/O||3.3V||By default used as CAN.RX with internal CAN PHY transceiver (mount option)
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J2.37||IO_L19N_T3_VREF_34||FPGA.IO_L19N_T3_VREF_34||R17||BANK34||I/O||3.3V||
+
|rowspan="5"|J1.99
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J2.39||IO_L18P_T2_34||FPGA.IO_L18P_T2_34||V16||BANK34||I/O||3.3V||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J2.41||IO_L18N_T2_34||FPGA.IO_L18N_T2_34||W16||BANK34||I/O||3.3V||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J2.43||DGND||DGND||-||||G||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J2.45||IO_L15P_T2_DQS_34||FPGA.IO_L15P_T2_DQS_34||T20||BANK34||I/O||3.3V||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J2.47||IO_L15N_T2_DQS_34||FPGA.IO_L15N_T2_DQS_34||U20||BANK34||I/O||3.3V||
+
|rowspan="5"|J1.101
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J2.49||DGND||DGND||-||||||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J2.51||IO_L13P_T1_MRCC_34||FPGA.IO_L13P_T1_MRCC_34||N18||BANK34||I/O||3.3V||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J2.53||IO_L13N_T1_MRCC_34||FPGA.IO_L13N_T1_MRCC_34||P19||BANK34||I/O||3.3V||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J2.55||DGND||DGND||-||||||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J2.57||IO_L11P_T1_SRCC_34||FPGA.IO_L11P_T1_SRCC_34||U14||BANK34||I/O||3.3V||
+
|rowspan="5"|J1.103
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J2.59||IO_L11N_T1_SRCC_34||FPGA.IO_L11N_T1_SRCC_34||U15||BANK34||I/O||3.3V||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J2.61||DGND||DGND||-||||||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J2.63||IO_L10P_T1_34||FPGA.IO_L10P_T1_34||V15||BANK34||I/O||3.3V||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J2.65||IO_L10N_T1_34||FPGA.IO_L10N_T1_34||W15||BANK34||I/O||3.3V||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J2.67||IO_25_34||FPGA.IO_25_34||T19||BANK34||I/O||3.3V||
+
|rowspan="5"|J1.105
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J2.69||IO_0_34||FPGA.IO_0_34||R19||BANK34||I/O||3.3V||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J2.71||DGND||DGND||-||||G||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J2.73||N.C.||Not Connected||-||||||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J2.75||N.C.||Not Connected||-||||||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J2.77||N.C.||Not Connected||-||||||||
+
|rowspan="5"|J1.107
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J2.79||N.C.||Not Connected||-||||||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J2.81||N.C.||Not Connected||-||||||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J2.83||N.C.||Not Connected||-||||||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J2.85||N.C.||Not Connected||-||||||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J2.87||N.C.||Not Connected||-||||||||
+
|rowspan="5"|J1.109
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J2.89||N.C.||Not Connected||-||||||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J2.91||N.C.||Not Connected||-||||||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J2.93||RTC_32KHZ||RTC.32KHZ||1||||O||3.3V||It can be left open if not used. For further details, please refer to the Maxim Integrated DS3232 datasheet.
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J2.95||RTC_RST||RTC.~RST ||4||||I/O||3.3V||It can be left open if not used. For further details, please refer to the Maxim Integrated DS3232 datasheet.
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J2.97||XADC_VN_R||FPGA.VN_0||L10||||A / I||VREFP
+
|rowspan="5"|J1.111
−
|See [[BELK-TN-012: Using XADC signal module|BELK-TN-012 Using XADC signal module]]
+
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J2.99||XADC_VP_R||FPGA.VP_0||K9||||A / I||VREFP
+
|Pin ALT-1
−
|See [[BELK-TN-012: Using XADC signal module|BELK-TN-012 Using XADC signal module]]
+
|TBD
 
|-
 
|-
−
|J2.101||N.C.||Not Connected||-||||||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J2.103||CONN_SPI_RSTn||NOR.~RESET/RFU ||A4||||||3.3V||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J2.105||CAN_L||CAN.L||6||||I/O||3.3V||For further details, please refer to the Texas Instruments SN65HVD232 datasheet.
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J2.107||CAN_H||CAN.H||7||||I/O||3.3V||For further details, please refer to the Texas Instruments SN65HVD232 datasheet.
+
|rowspan="5"|J1.113
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J2.109||DGND||DGND||-||||G||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J2.111||RTC_INT/SQW||RTC.RTC_INT/SQW||3||||I/O||3.3V|| It can be left open if not used. When used, a proper pull-up resistor is required on the carrier board. For further details, please refer to the Maxim Integrated DS3232 datasheet.
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J2.113||RTC_VBAT||RTC.VBAT||6||||S||3.0V||Connect to ground if not used. For further details, please refer to the Maxim Integrated DS3232 datasheet.
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J2.115||VBAT||CPU.VCCBATT_0||F11|| ||S|| ||This pin is connected to the VCCBATT_0 (for the battery-backed RAM - BBRAM) pin of the Zynq SOC. For additional information, please refer to the Zynq datasheet and TRM.
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J2.117||DGND||DGND||-||||G||||
+
|rowspan="5"|J1.115
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J2.119||3.3VIN||+3.3 V||-||||S||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J2.121||3.3VIN||+3.3 V||-||||S||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J2.123||3.3VIN||+3.3 V||-||||S||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J2.125||DGND||DGND||-||||G||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J2.127||3.3VIN||+3.3 V||-||||S||||
+
|rowspan="5"|J1.117
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J2.129||3.3VIN||+3.3 V||-||||S||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J2.131||3.3VIN||+3.3 V||-||||S||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J2.133||3.3VIN||+3.3 V||-||||S||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J2.135||3.3VIN||+3.3 V||-||||S||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J2.137||3.3VIN||+3.3 V||-||||S||||
+
|rowspan="5"|J1.119
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J2.139||DGND||DGND||-||||G||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|}
+
|Pin ALT-2
−
 
+
|TBD
−
==SOM J2 EVEN pins (2 to 140) declaration==
 
−
 
 
−
{| class="wikitable" {| {{table}}
 
−
| style="background:#f0f0f0;" align="center" |'''Pin'''
 
−
| style="background:#f0f0f0;" align="center" |'''Pin Name'''
 
−
| style="background:#f0f0f0;" align="center" |'''Internal Connections'''
 
−
| style="background:#f0f0f0;" align="center" |'''Ball/pin #'''
 
−
| style="background:#f0f0f0;" align="center" |'''Supply Group'''
 
−
| style="background:#f0f0f0;" align="center" |'''Type'''
 
−
| style="background:#f0f0f0;" align="center" |'''Voltage'''
 
−
| style="background:#f0f0f0;" align="center" |'''Note'''
 
 
|-
 
|-
−
|J2.2||DGND||DGND||-||||G||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J2.4||IO_L9P_T1_DQS_34||FPGA.IO_L9P_T1_DQS_34||T16||BANK34||I/O||3.3V||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J2.6||IO_L9N_T1_DQS_34||FPGA.IO_L9N_T1_DQS_34||U17||BANK34||I/O||3.3V||
+
|rowspan="5"|J1.121
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J2.8||IO_L7P_T1_34||FPGA.IO_L7P_T1_34||Y16||BANK34||I/O||3.3V||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J2.10||IO_L7N_T1_34||FPGA.IO_L7N_T1_34||Y17||BANK34||I/O||3.3V||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J2.12||DGND||DGND||-||||G||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J2.14||IO_L5P_T0_34||FPGA.IO_L5P_T0_34||T14||BANK34||I/O||3.3V||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J2.16||IO_L5N_T0_34||FPGA.IO_L5N_T0_34||T15||BANK34||I/O||3.3V||
+
|rowspan="5"|J1.123
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J2.18||IO_L4P_T0_34||FPGA.IO_L4P_T0_34||V12||BANK34||I/O||3.3V||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J2.20||IO_L4N_T0_34||FPGA.IO_L4N_T0_34||W13||BANK34||I/O||3.3V||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J2.22||DGND||DGND||-||||G||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J2.24||IO_L24P_T3_34||FPGA.IO_L24P_T3_34||P15||BANK34||I/O||3.3V||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J2.26||IO_L24N_T3_34||FPGA.IO_L24N_T3_34||P16||BANK34||I/O||3.3V||
+
|rowspan="5"|J1.125
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J2.28||IO_L23P_T3_34||FPGA.IO_L23P_T3_34||N17||BANK34||I/O||3.3V||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J2.30||IO_L23N_T3_34||FPGA.IO_L23N_T3_34||P18||BANK34||I/O||3.3V||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J2.32||DGND||DGND||-||||G||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J2.34||IO_L20P_T3_34||FPGA.IO_L20P_T3_34||T17||BANK34||I/O||3.3V||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J2.36||IO_L20N_T3_34||FPGA.IO_L20N_T3_34||R18||BANK34||I/O||3.3V||
+
|rowspan="5"|J1.127
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J2.38||IO_L1P_T0_34||FPGA.IO_L1P_T0_34||T11||BANK34||I/O||3.3V||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J2.40||IO_L1N_T0_34||FPGA.IO_L1N_T0_34||T10||BANK34||I/O||3.3V||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J2.42||DGND||DGND||-||||G||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J2.44||IO_L17P_T2_34||FPGA.IO_L17P_T2_34||Y18||BANK34||I/O||3.3V||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J2.46||IO_L17N_T2_34||FPGA.IO_L17N_T2_34||Y19||BANK34||I/O||3.3V||
+
|rowspan="5"|J1.129
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J2.48||IO_L16P_T2_34||FPGA.IO_L16P_T2_34||V20||BANK34||I/O||3.3V||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J2.50||IO_L16N_T2_34||FPGA.IO_L16N_T2_34||W20||BANK34||I/O||3.3V||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J2.52||DGND||DGND||-||||G||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J2.54||IO_L14P_T2_SRCC_34||FPGA.IO_L14P_T2_SRCC_34||N20||BANK34||I/O||3.3V||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J2.56||IO_L14N_T2_SRCC_34||FPGA.IO_L14N_T2_SRCC_34||P20||BANK34||I/O||3.3V||
+
|rowspan="5"|J1.131
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J2.58||DGND||DGND||-||||G||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J2.60||IO_L12P_T1_MRCC_34||FPGA.IO_L12P_T1_MRCC_34||U18||BANK34||I/O||3.3V||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J2.62||IO_L12N_T1_MRCC_34||FPGA.IO_L12N_T1_MRCC_34||U19||BANK34||I/O||3.3V||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J2.64||DGND||DGND||-||||G||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J2.66||VDDIO_BANK34||FPGA.VCCO_34||N19<br>R15<br>T18<br>V14<br>W17<br>Y20||BANK34||S||||Mounting option (please contact [mailto:sales@dave.eu sales dept.] for more information)
+
|rowspan="5"|J1.133
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J2.68||VDDIO_BANK34||FPGA.VCCO_34||N19<br>R15<br>T18<br>V14<br>W17<br>Y20||BANK34||S||||Mounting option (please contact [mailto:sales@dave.eu sales dept.] for more information)
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J2.70||VDDIO_BANK34||FPGA.VCCO_34||N19<br>R15<br>T18<br>V14<br>W17<br>Y20||BANK34||S||||Mounting option (please contact [mailto:sales@dave.eu sales dept.] for more information)
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J2.72||VDDIO_BANK34||FPGA.VCCO_34||N19<br>R15<br>T18<br>V14<br>W17<br>Y20||BANK34||S||||Mounting option (please contact [mailto:sales@dave.eu sales dept.] for more information)
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J2.74||N.C.||Not Connected||-||||||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J2.76||N.C.||Not Connected||-||||||||
+
|rowspan="5"|J1.135
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J2.78||N.C.||Not Connected||-||||||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J2.80||JTAG_TDO||CPU.TDO_0||F6||||||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J2.82||JTAG_TDI||CPU.TDI_0||G6||||||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J2.84||JTAG_TMS||CPU.TMS_0||J6||||||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J2.86||JTAG_TCK||CPU.TCK_0||F9||||||||
+
|rowspan="5"|J1.137
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J2.88||DGND||DGND||-||||G||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J2.90||FPGA_INIT_B||FPGA.INIT_B_0||R10||||||||For further details, please refer to [[PL_initialization_signals_(Bora/BoraX/BoraLite) | PL initialization signals]]
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J2.92||FPGA_PROGRAM_B||FPGA.PROGRAM_B_0||L6||||||||For further details, please refer to [[PL_initialization_signals_(Bora/BoraX/BoraLite) | PL initialization signals]]
+
|Pin ALT-3
−
 
+
|TBD
−
(10 kΩ pull-up resistor is already mounted on BORA module)
 
 
|-
 
|-
−
|J2.94||FPGA_DONE||FPGA.DONE_0||R11||||||||For further details, please refer to [[PL_initialization_signals_(Bora/BoraX/BoraLite) | PL initialization signals]]
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J2.96||WD_SET2||WDT.SET2||6||||I||3.3V||Internal 10K pull-up. For further details, please refer to the Maxim Integrated MAX6373 datasheet.
+
|rowspan="5"|J1.139
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J2.98||WD_SET1||WDT.SET1||5||||I||3.3V||Internal 10K pull-up. For further details, please refer to the Maxim Integrated MAX6373 datasheet.
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J2.100||WD_SET0||WDT.SET0||4||||I||3.3V||Internal 10K pull-down. For further details, please refer to the Maxim Integrated MAX6373 datasheet.
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J2.102||DGND||DGND||-||||G||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J2.104||PS_MIO50_501||CPU.PS_MIO50_501<br>USBOTG.RESETB||B13<br>22||BANK501||I/O||1.8V|| For further details, please refer to [[Reset_scheme_(Bora)#PS_MIO50_501_.28J2.104.29 | Reset_scheme_(Bora)#PS_MIO50_501]]
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J2.106||PS_MIO51_501||CPU.PS_MIO51_501<br>ETHPHY1GB.RESET_N||B9<br>42||BANK501||I/O||1.8V|| For further details, please refer to [[Reset_scheme_(Bora)#PS_MIO51_501_.28J2.106.29 | Reset_scheme_(Bora)#PS_MIO51_501]]
+
|rowspan="5"|J1.141
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J2.108||BOARD_PGOOD||PSUSWITCHFPGABANK13.ON<br>PSUSWITCHFPGABANK35.ON<br>PSUSWITCHFPGABANK500/34.ON<br>PSUSWITCHFPGABANK501.ON<br>DDRVREFREGULATOR.PGOOD||3<br>3<br>3<br>3<br>9||||O||3.3V||For further details, please refer to [[Power (Bora/BoraLite)|Power Supply (Bora)]]
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J2.110||CB_PWR_GOOD ||1V0REGULATOR.ENABLE ||-||||I||3.3V||For further details, please refer to [[Power (Bora/BoraLite)|Power Supply (Bora)]]
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J2.112||SYS_RSTN||CPU.PS_SRST_B_501<br>MTR.~RST||B10<br>5||||I||1.8V||For further details, please refer to  [[Reset scheme (Bora/BoraLite)#Reset signals|Reset signals]]
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J2.114||PORSTN||CPU.PS_POR_B_500||C7||||I/O||3.3V||For further details, please refer to  [[Reset scheme (Bora/BoraLite)#Reset signals|Reset signals]]
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J2.116||MRSTN||MTR.MR||6||||I||3.3V||For further details, please refer to  [[Reset scheme (Bora/BoraLite)#Reset signals|Reset signals]]
+
|rowspan="5"|J1.143
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J2.118||DGND||DGND||-||||G||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J2.120||3.3VIN||+3.3 V||-||||S||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J2.122||3.3VIN||+3.3 V||-||||S||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J2.124||DGND||DGND||-||||G||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J2.126||3.3VIN||+3.3 V||-||||S||||
+
|rowspan="5"|J1.145
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J2.128||3.3VIN||+3.3 V||-||||S||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J2.130||3.3VIN||+3.3 V||-||||S||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J2.132||3.3VIN||+3.3 V||-||||S||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J2.134||3.3VIN||+3.3 V||-||||S||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J2.136||3.3VIN||+3.3 V||-||||S||||
+
|rowspan="5"|J1.147
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J2.138||3.3VIN||+3.3 V||-||||S||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J2.140||DGND||DGND||-||||G||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|}
+
|Pin ALT-3
−
 
+
|TBD
−
==SOM J3 ODD pins (1 to 139)declaration==
 
−
 
 
−
{| class="wikitable" {| {{table}}
 
−
| style="background:#f0f0f0;" align="center" |'''Pin'''
 
−
| style="background:#f0f0f0;" align="center" |'''Pin Name'''
 
−
| style="background:#f0f0f0;" align="center" |'''Internal Connections'''
 
−
| style="background:#f0f0f0;" align="center" |'''Ball/pin #'''
 
−
| style="background:#f0f0f0;" align="center" |'''Supply Group'''
 
−
| style="background:#f0f0f0;" align="center" |'''Type'''
 
−
| style="background:#f0f0f0;" align="center" |'''Voltage'''
 
−
| style="background:#f0f0f0;" align="center" |'''Note'''
 
 
|-
 
|-
−
|J3.1||N.C.||Not Connected||-||||||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J3.3||N.C.||Not Connected||-||||||||
+
|rowspan="5"|J1.149
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J3.5||N.C.||Not Connected||-||||||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J3.7||N.C.||Not Connected||-||||||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J3.9||N.C.||Not Connected||-||||||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J3.11||N.C.||Not Connected||-||||||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J3.13||N.C.||Not Connected||-||||||||
+
|rowspan="5"|J1.151
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J3.15||N.C.||Not Connected||-||||||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J3.17||N.C.||Not Connected||-||||||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J3.19||N.C.||Not Connected||-||||||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J3.21||N.C.||Not Connected||-||||||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J3.23||N.C.||Not Connected||-||||||||
+
|rowspan="5"|J1.153
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J3.25||N.C.||Not Connected||-||||||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J3.27||N.C.||Not Connected||-||||||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J3.29||N.C.||Not Connected||-||||||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J3.31||N.C.||Not Connected||-||||||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J3.33||N.C.||Not Connected||-||||||||
+
|rowspan="5"|J1.155
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J3.35||N.C.||Not Connected||-||||||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J3.37||N.C.||Not Connected||-||||||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J3.39||N.C.||Not Connected||-||||||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J3.41||N.C.||Not Connected||-||||||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J3.43||N.C.||Not Connected||-||||||||
+
|rowspan="5"|J1.157
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J3.45||N.C.||Not Connected||-||||||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J3.47||N.C.||Not Connected||-||||||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J3.49||N.C.||Not Connected||-||||||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J3.51||N.C.||Not Connected||-||||||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J3.53||N.C.||Not Connected||-||||||||
+
|rowspan="5"|J1.159
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J3.55||N.C.||Not Connected||-||||||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J3.57||N.C.||Not Connected||-||||||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J3.59||N.C.||Not Connected||-||||||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J3.61||N.C.||Not Connected||-||||||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J3.63||N.C.||Not Connected||-||||||||
+
|rowspan="5"|J1.161
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J3.65||N.C.||Not Connected||-||||||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J3.67||DGND||DGND||-||||||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J3.69||N.C.||Not Connected||-||||||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J3.71||N.C.||Not Connected||-||||||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J3.73||N.C.||Not Connected||-||||||||
+
|rowspan="5"|J1.163
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J3.75||N.C.||Not Connected||-||||||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J3.77||N.C.||Not Connected||-||||||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J3.79||N.C.||Not Connected||-||||||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J3.81||N.C.||Not Connected||-||||||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J3.83||N.C.||Not Connected||-||||||||
+
|rowspan="5"|J1.165
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J3.85||N.C.||Not Connected||-||||||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J3.87||N.C.||Not Connected||-||||||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J3.89||N.C.||Not Connected||-||||||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J3.91||N.C.||Not Connected||-||||||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J3.93||DGND||DGND||-||||G||||
+
|rowspan="5"|J1.167
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J3.95||VDDIO_BANK13||FPGA.VCCO_13||T8<br>U11<br>W7<br>Y10||BANK13||S|||| N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J3.97||VDDIO_BANK13||FPGA.VCCO_13||T8<br>U11<br>W7<br>Y10||BANK13||S|||| N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J3.99||VDDIO_BANK13||FPGA.VCCO_13||T8<br>U11<br>W7<br>Y10||BANK13||S|||| N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J3.101||DGND||DGND||-||||G||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J3.103||DGND||DGND||-||||G||||
+
|rowspan="5"|J1.169
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J3.105||IO_L21P_T3_DQS_13||FPGA.IO_L21P_T3_DQS_13||V11||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J3.107||IO_L21N_T3_DQS_13||FPGA.IO_L21N_T3_DQS_13||V10||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J3.109||DGND||DGND||-||||G||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J3.111||IO_L19P_T3_13||FPGA.IO_L19P_T3_13||T5||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J3.113||IO_L19N_T3_VREF_13||FPGA.IO_L19N_T3_VREF_13||U5||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
+
|rowspan="5"|J1.171
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J3.115||DGND||DGND||-||||G||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J3.117||IO_L18P_T2_13||FPGA.IO_L18P_T2_13||W11||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J3.119||IO_L18N_T2_13||FPGA.IO_L18N_T2_13||Y11||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J3.121||DGND||DGND||-||||G||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J3.123||IO_L16P_T2_13||FPGA.IO_L16P_T2_13||W10||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
+
|rowspan="5"|J1.173
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J3.125||IO_L16N_T2_13||FPGA.IO_L16N_T2_13||W9||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J3.127||DGND||DGND||-||||G||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J3.129||IO_L14P_T2_SRCC_13||FPGA.IO_L14P_T2_SRCC_13||Y9||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J3.131||IO_L14N_T2_SRCC_13||FPGA.IO_L14N_T2_SRCC_13||Y8||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J3.133||DGND||DGND||-||||G||||
+
|rowspan="5"|J1.175
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J3.135||IO_L12P_T1_MRCC_13||FPGA.IO_L12P_T1_MRCC_13||T9||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J3.137||IO_L12N_T1_MRCC_13||FPGA.IO_L12N_T1_MRCC_13||U10||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J3.139||DGND||DGND||-||||G||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|}
+
|Pin ALT-5
−
 
+
|TBD
−
==SOM J3 EVEN pins (2 to 140) declaration==
 
−
 
 
−
{| class="wikitable" {| {{table}}
 
−
| style="background:#f0f0f0;" align="center" |'''Pin'''
 
−
| style="background:#f0f0f0;" align="center" |'''Pin Name'''
 
−
| style="background:#f0f0f0;" align="center" |'''Internal Connections'''
 
−
| style="background:#f0f0f0;" align="center" |'''Ball/pin #'''
 
−
| style="background:#f0f0f0;" align="center" |'''Supply Group'''
 
−
| style="background:#f0f0f0;" align="center" |'''Type'''
 
−
| style="background:#f0f0f0;" align="center" |'''Voltage'''
 
−
| style="background:#f0f0f0;" align="center" |'''Note'''
 
 
|-
 
|-
−
|J3.2||N.C.||Not Connected||-||||||||
+
|rowspan="5"|J1.177
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J3.4||N.C.||Not Connected||-||||||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J3.6||N.C.||Not Connected||-||||||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J3.8||N.C.||Not Connected||-||||||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J3.10||N.C.||Not Connected||-||||||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J3.12||N.C.||Not Connected||-||||||||
+
|rowspan="5"|J1.179
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J3.14||N.C.||Not Connected||-||||||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J3.16||N.C.||Not Connected||-||||||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J3.18||N.C.||Not Connected||-||||||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J3.20||N.C.||Not Connected||-||||||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J3.22||N.C.||Not Connected||-||||||||
+
|rowspan="5"|J1.181
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J3.24||N.C.||Not Connected||-||||||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J3.26||N.C.||Not Connected||-||||||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J3.28||N.C.||Not Connected||-||||||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J3.30||N.C.||Not Connected||-||||||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J3.32||N.C.||Not Connected||-||||||||
+
|rowspan="5"|J1.183
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J3.34||N.C.||Not Connected||-||||||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J3.36||N.C.||Not Connected||-||||||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J3.38||N.C.||Not Connected||-||||||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J3.40||N.C.||Not Connected||-||||||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J3.42||N.C.||Not Connected||-||||||||
+
|rowspan="5"|J1.185
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J3.44||N.C.||Not Connected||-||||||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J3.46||N.C.||Not Connected||-||||||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J3.48||N.C.||Not Connected||-||||||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J3.50||N.C.||Not Connected||-||||||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J3.52||N.C.||Not Connected||-||||||||
+
|rowspan="5"|J1.187
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J3.54||N.C.||Not Connected||-||||||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J3.56||N.C.||Not Connected||-||||||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J3.58||N.C.||Not Connected||-||||||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J3.60||N.C.||Not Connected||-||||||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J3.62||N.C.||Not Connected||-||||||||
+
|rowspan="5"|J1.189
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J3.64||N.C.||Not Connected||-||||||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J3.66||N.C.||Not Connected||-||||||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J3.68||DGND||DGND||-||||G||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J3.70||N.C.||Not Connected||-||||||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J3.72||MON_VCCPLL||n.a.||-|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
+
|rowspan="5"|J1.191
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J3.74||MON_XADC_VCC||n.a.||-|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J3.76||MON_FPGA_VDDIO_BANK35||n.a.||-|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J3.78||MON_FPGA_VDDIO_BANK34||n.a.||-|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J3.80||MON_FPGA_VDDIO_BANK13||n.a.||-|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J3.82||MON_1.8V_IO||n.a.||-|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
+
|rowspan="5"|J1.193
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J3.84||MON_3.3V||n.a.||-|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J3.86||MON_1V2_ETH||n.a.||-|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J3.88||MON_VDDQ_1V5||n.a.||-|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J3.90||MON_1.8V||n.a.||-|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J3.92||MON_1.0V||n.a.||-|||||||| By default this pin must not be connected. Optionally it can route power voltage generated by Bora PSU. This option is meant to allow monitoring such voltage by carrier board circuitry. It is not meant to power carrier board devices. For more information please contact technical support.
+
|rowspan="5"|J1.195
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J3.94||DGND||DGND||-||||G||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J3.96||VDDIO_BANK13||FPGA.VCCO_13||T8<br>U11<br>W7<br>Y10||BANK13||S|||| N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J3.98||VDDIO_BANK13||FPGA.VCCO_13||T8<br>U11<br>W7<br>Y10||BANK13||S|||| N.B. Although BANK 13 is not available on Bora SOMs equipped with the XC7Z010 SOC, VDDIO_BANK13 pin must not be left open and must be connected as described in [[Programmable_logic_(Bora)]].
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J3.100||IO_L6N_T0_VREF_13||FPGA.IO_L6N_T0_VREF_13||V5||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J3.102||DGND||DGND||-||||G||||
+
|rowspan="5"|J1.197
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J3.104||IO_L22P_T3_13||FPGA.IO_L22P_T3_13||V6||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J3.106||IO_L22N_T3_13||FPGA.IO_L22N_T3_13||W6||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J3.108||DGND||DGND||-||||G||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J3.110||IO_L20P_T3_13||FPGA.IO_L20P_T3_13||Y12||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J3.112||IO_L20N_T3_13||FPGA.IO_L20N_T3_13||Y13||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
+
|rowspan="5"|J1.199
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J3.114||DGND||DGND||-||||G||||
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J3.116||IO_L17P_T2_13||FPGA.IO_L17P_T2_13||U9||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J3.118||IO_L17N_T2_13||FPGA.IO_L17N_T2_13||U8||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J3.120||DGND||DGND||-||||G||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J3.122||IO_L15P_T2_DQS_13||FPGA.IO_L15P_T2_DQS_13||V8||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
+
|rowspan="5"|J1.201
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J3.124||IO_L15N_T2_DQS_13||FPGA.IO_L15N_T2_DQS_13||W8||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J3.126||DGND||DGND||-||||G||||
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J3.128||IO_L13P_T2_MRCC_13||FPGA.IO_L13P_T2_MRCC_13||Y7||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J3.130||IO_L13N_T2_MRCC_13||FPGA.IO_L13N_T2_MRCC_13||Y6||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
−
|J3.132||DGND||DGND||-||||G||||
+
|rowspan="5"|J1.203
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|rowspan="5"|TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|J3.134||IO_L11P_T1_SRCC_13||FPGA.IO_L11P_T1_SRCC_13||U7||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
+
|Pin ALT-1
 +
|TBD
 
|-
 
|-
−
|J3.136||IO_L11N_T1_SRCC_13||FPGA.IO_L11N_T1_SRCC_13||V7||BANK13||I/O||U.D.|| Not available on Bora SOMs equipped with the XC7Z010 SOC
+
|Pin ALT-2
 +
|TBD
 
|-
 
|-
−
|J3.138||DGND||DGND||-||||G||||
+
|Pin ALT-3
 +
|TBD
 
|-
 
|-
−
|J3.140||DGND||DGND||-||||G||||
+
|Pin ALT-5
 +
|TBD
 
|-
 
|-
 
|}
 
|}
−
<section end="Body" />
+
 
 +
----
 +
 
 +
[[Category:BORA]]

Revision as of 07:44, 30 July 2021

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History
Version Issue Date Notes
X.Y.Z Month Year TBD
[TBD_link X.Y.Z] Month Year TBD
... ... ...


TBD: modificare la tabella seguente con le caratteristiche dei pin del SOM

TBD: modificare le due tabelle ODD e EVEN con la mappa completa dei pins

TBD: nella tabella naming conventions, inserire il codice dei vari IC presenti (PMIC, PHY ETH, ecc.)

Connectors and Pinout Table[edit | edit source]

Connectors description[edit | edit source]

In the following table are described all available connectors integrated on BORA:

Connector name Connector Type Notes Carrier board counterpart
J1 SODIMM DDR3 edge connector 204 pin TE Connectivity 2-2013289-1
Jxx TBD TBD TBD
Jxx TBD TBD TBD
Jxx TBD TBD TBD
Jxx TBD TBD TBD

The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to BORA pinout specifications. See the images below for reference:

File:BORA-top.png
BORA TOP view
File:BORA-bottom.png
BORA BOTTOM view

Pinout table naming conventions[edit | edit source]

This chapter contains the pinout description of the BORA module, grouped in two tables (odd and even pins) that report the pin mapping of the TBD: connector type BORA connector.

Each row in the pinout tables contains the following information:

Pin Reference to the connector pin
Pin Name Pin (signal) name on the BORA connectors
Internal
connections 		Connections to the BORA components
  • CPU.<x> : pin connected to CPU pad named <x>
  • CAN.<x> : pin connected to the CAN transceiver (manufacturer part number)
  • PMIC.<x> : pin connected to the Power Manager IC (manufacturer part number)
  • LAN.<x> : pin connected to the LAN PHY (manufacturer part number)
  • NOR.<x>: pin connected to the flash NOR
  • SV.<x>: pin connected to voltage supervisor
  • MTR: pin connected to voltage monitors
Ball/pin # Component ball/pin number connected to signal
Voltage I/O voltage levels
Type Pin type:
  • I = Input
  • O = Output
  • D = Differential
  • Z = High impedance
  • S = Power supply voltage
  • G = Ground
  • A = Analog signal
Notes Remarks on special pin characteristics
Pin MUX alternative functions Muxes:
  • Pin ALT-0
  • ...
  • Pin ALT-N

The number of functions depends on platform

Pinout Table ODD pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage domain Type Notes Alternative Functions
J1.1 SD2_CMD CPU.SD2_CMD F19 AXEL_IO_3V3 IO Notes Pin ALT-0 SD2_CMD
Pin ALT-1 ECSPI5_MOSI
Pin ALT-2 KEY_ROW5
Pin ALT-3 AUD4_RXC
Pin ALT-5 GPIO1_IO11
J1.3 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.5 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.7 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.9 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.11 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.13 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.15 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.17 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.19 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.21 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.23 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.25 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.27 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.29 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.31 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.33 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.35 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.37 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.39 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.31 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.33 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.35 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.37 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.39 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.41 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.43 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.45 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.47 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.49 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.51 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.53 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.55 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.57 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.59 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.61 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.63 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.65 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.67 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.69 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.71 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.73 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.75 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.77 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.79 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.81 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.83 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.85 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.87 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.89 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.91 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.93 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.95 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.97 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.99 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.101 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.103 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.105 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.107 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.109 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.111 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.113 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.115 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.117 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.119 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.121 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.123 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.125 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.127 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.129 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.131 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.133 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.135 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.137 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.139 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.141 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.143 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.145 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.147 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.149 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.151 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.153 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.155 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.157 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.159 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.161 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.163 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.165 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.167 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.169 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.171 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.173 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.175 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.177 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.179 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.181 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.183 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.185 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.187 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.189 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.191 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.193 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.195 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.197 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.199 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.201 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.203 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD

Pinout Table EVEN pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage domain Type Notes Alternative Functions
J1.1 SD2_CMD CPU.SD2_CMD F19 AXEL_IO_3V3 IO Notes Pin ALT-0 SD2_CMD
Pin ALT-1 ECSPI5_MOSI
Pin ALT-2 KEY_ROW5
Pin ALT-3 AUD4_RXC
Pin ALT-5 GPIO1_IO11
J1.3 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.5 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.7 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.9 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.11 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.13 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.15 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.17 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.19 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.21 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.23 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.25 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.27 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.29 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.31 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.33 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.35 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.37 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.39 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.31 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.33 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.35 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.37 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.39 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.41 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.43 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.45 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.47 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.49 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.51 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.53 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.55 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.57 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.59 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.61 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.63 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.65 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.67 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.69 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.71 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.73 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.75 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.77 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.79 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.81 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.83 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.85 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.87 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.89 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.91 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.93 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.95 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.97 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.99 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.101 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.103 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.105 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.107 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.109 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.111 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.113 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.115 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.117 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.119 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.121 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.123 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.125 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.127 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.129 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.131 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.133 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.135 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.137 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.139 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.141 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.143 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.145 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.147 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.149 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.151 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.153 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.155 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.157 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.159 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.161 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.163 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.165 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.167 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.169 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.171 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.173 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.175 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.177 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.179 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.181 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.183 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.185 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.187 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.189 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.191 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.193 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.195 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.197 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.199 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.201 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.203 TBD TBD TBD TBD TBD TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
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