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Created page with "{{WorkInProgress}} {{InfoBoxTop}} {{Applies To Maya}} {{InfoBoxBottom}} == Introduction == Maya memory organization and mapping is relatively simple. About system RAM, DM81..."
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== Introduction ==
Maya memory organization and mapping is relatively simple.
About system RAM, DM8148 provides two controllers. Each one can be interfaced to one SDRAM bank through a physical interface called EMIF (EMIF0 and EMIF1). EMIF0 is connected to 32-bit DDR2 SDRAM bank (up to 512 MByte). EMIF1 is not connected to any device, hence is permanently disabled.
About non-volatile memories, 8-bit NAND flash is conneted to processor through GPMC bus. Associated chip select is CS0n in order to make it work as boot device.
{{InfoBoxTop}}
{{Applies To Maya}}
{{InfoBoxBottom}}
== Introduction ==
Maya memory organization and mapping is relatively simple.
About system RAM, DM8148 provides two controllers. Each one can be interfaced to one SDRAM bank through a physical interface called EMIF (EMIF0 and EMIF1). EMIF0 is connected to 32-bit DDR2 SDRAM bank (up to 512 MByte). EMIF1 is not connected to any device, hence is permanently disabled.
About non-volatile memories, 8-bit NAND flash is conneted to processor through GPMC bus. Associated chip select is CS0n in order to make it work as boot device.