Difference between revisions of "MITO 8M Nano SOM/MITO 8M Nano Hardware/General Information/Processor and memory subsystem"
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! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History | ! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History | ||
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| + | ! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Version | ||
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date | ! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date | ||
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes | ! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes | ||
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| − | | style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" | | + | | style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |1.0.0 |
| − | | style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" | First release | + | | style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Jan 2021 |
| + | | style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release | ||
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|} | |} | ||
<section end="History" /> | <section end="History" /> | ||
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== Processor and memory subsystem == | == Processor and memory subsystem == | ||
| − | The heart of MITO 8M Nano module is composed by the following components: | + | The heart of MITO 8M Mini/Nano module is composed by the following components: |
| − | *i.MX8M | + | *i.MX8M Mini SoC application processor |
* Power supply unit | * Power supply unit | ||
* LPDDR4 memory bank | * LPDDR4 memory bank | ||
| Line 26: | Line 27: | ||
*** partially compatible with [[AXEL Lite SOM]] | *** partially compatible with [[AXEL Lite SOM]] | ||
| − | This chapter shortly describes the main MITO 8M Nano components. | + | This chapter shortly describes the main MITO 8M Mini/Nano components. |
=== Processor Info === | === Processor Info === | ||
| Line 32: | Line 33: | ||
{| class="wikitable" | | {| class="wikitable" | | ||
| align="center" style="background:#f0f0f0;" |'''Processor''' | | align="center" style="background:#f0f0f0;" |'''Processor''' | ||
| − | |||
| align="center" style="background:#f0f0f0;" |'''i.MX8M Nano Dual''' | | align="center" style="background:#f0f0f0;" |'''i.MX8M Nano Dual''' | ||
| align="center" style="background:#f0f0f0;" |'''i.MX8M Nano Quad''' | | align="center" style="background:#f0f0f0;" |'''i.MX8M Nano Quad''' | ||
|- | |- | ||
|# Cores | |# Cores | ||
| − | |||
| − | |||
|2x Arm® Cortex®-A53 | |2x Arm® Cortex®-A53 | ||
1x Arm® Cortex®-M7 | 1x Arm® Cortex®-M7 | ||
| Line 44: | Line 42: | ||
1x Arm® Cortex®-M7 | 1x Arm® Cortex®-M7 | ||
|- | |- | ||
| − | |Clock|| colspan=" | + | |Clock|| colspan="2" |1.4 GHz<br>1.5 GHz |
|- | |- | ||
|L2 | |L2 | ||
Cache | Cache | ||
| − | | colspan=" | + | | colspan="2" |1 MB |
|- | |- | ||
|LPDDR4 | |LPDDR4 | ||
| − | | colspan=" | + | | colspan="2" |16 bit @ 1600 MHz |
(LPDDR4-3200) | (LPDDR4-3200) | ||
|- | |- | ||
|GPU | |GPU | ||
| − | | colspan=" | + | | colspan="2" |Vivante GC 7000UL (2 Shader) |
OpenGL ES 3.1<br>Vulkan<br>Open VG 1.1<br>Open CL 1.2 | OpenGL ES 3.1<br>Vulkan<br>Open VG 1.1<br>Open CL 1.2 | ||
|- | |- | ||
|Display | |Display | ||
Controller | Controller | ||
| − | | colspan=" | + | | colspan="2" |Dual Independent LVDS channel |
Display Support | Display Support | ||
up to 1080p60 | up to 1080p60 | ||
| Line 66: | Line 64: | ||
|Video | |Video | ||
Output | Output | ||
| − | | colspan=" | + | | colspan="2" |1x MIPI-DSI (with MIPI to LVDS bridge) |
|- | |- | ||
|Camera | |Camera | ||
Input | Input | ||
| − | | colspan=" | + | | colspan="2" |1x MIPI CSI (4-lanes) |
|- | |- | ||
|USB | |USB | ||
| − | | colspan=" | + | | colspan="2" |2x USB 2.0 OTG |
|- | |- | ||
|+ align="bottom" style="caption-side: bottom" | Table: i.MX8M Nano models comparison | |+ align="bottom" style="caption-side: bottom" | Table: i.MX8M Nano models comparison | ||
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=== RAM memory bank === | === RAM memory bank === | ||
| − | LPDD4 SDRAM memory bank is composed by 1x | + | LPDD4 SDRAM memory bank is composed by 1x 32-bit width chip. The following table reports the SDRAM specifications: |
{| class="wikitable" | | {| class="wikitable" | | ||
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{| style="color:#000000; border:solid 2px #73B2C7; background-color:#ededed;font-size:95%; vertical-align:middle;" | {| style="color:#000000; border:solid 2px #73B2C7; background-color:#ededed;font-size:95%; vertical-align:middle;" | ||
| [[File:TBD.png|30px]] | | [[File:TBD.png|30px]] | ||
| − | | ''' | + | | '''Section not completed yet''' |
|} | |} | ||
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| '''CPU connection'''||Raw NAND flash controller | | '''CPU connection'''||Raw NAND flash controller | ||
|- | |- | ||
| − | | '''Page size'''|| | + | | '''Page size'''|| TBD |
|- | |- | ||
| − | | '''Size min'''|| | + | | '''Size min'''||TBD |
|- | |- | ||
| − | | '''Size max'''|| | + | | '''Size max'''||TBD |
|- | |- | ||
| '''Width'''||8 bit | | '''Width'''||8 bit | ||
|- | |- | ||
| − | | '''Chip select'''|| | + | | '''Chip select'''||TBD |
|- | |- | ||
| '''Bootable'''||Yes | | '''Bootable'''||Yes | ||
| Line 146: | Line 144: | ||
---- | ---- | ||
| + | [[Category:MITO 8M Mini]] | ||
[[Category:MITO 8M Nano]] | [[Category:MITO 8M Nano]] | ||
Revision as of 14:16, 23 February 2021
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| Version | Issue Date | Notes | |
| 1.0.0 | Jan 2021 | First release | |
Contents
Processor and memory subsystem[edit | edit source]
The heart of MITO 8M Mini/Nano module is composed by the following components:
- i.MX8M Mini SoC application processor
- Power supply unit
- LPDDR4 memory bank
- eMMC or NAND flash banks
- Connectors:
- 1 x 204 pins SO-DIMM edge connector with interfaces signals
- partially compatible with AXEL Lite SOM
- 1 x 204 pins SO-DIMM edge connector with interfaces signals
This chapter shortly describes the main MITO 8M Mini/Nano components.
Processor Info[edit | edit source]
| Processor | i.MX8M Nano Dual | i.MX8M Nano Quad |
| # Cores | 2x Arm® Cortex®-A53
1x Arm® Cortex®-M7 |
4x Arm® Cortex®-A53
1x Arm® Cortex®-M7 |
| Clock | 1.4 GHz 1.5 GHz | |
| L2
Cache |
1 MB | |
| LPDDR4 | 16 bit @ 1600 MHz
(LPDDR4-3200) | |
| GPU | Vivante GC 7000UL (2 Shader)
OpenGL ES 3.1 | |
| Display
Controller |
Dual Independent LVDS channel
Display Support up to 1080p60 | |
| Video
Output |
1x MIPI-DSI (with MIPI to LVDS bridge) | |
| Camera
Input |
1x MIPI CSI (4-lanes) | |
| USB | 2x USB 2.0 OTG | |
RAM memory bank[edit | edit source]
LPDD4 SDRAM memory bank is composed by 1x 32-bit width chip. The following table reports the SDRAM specifications:
| CPU connection | Multi-mode DDR controller (MMDC) |
| Size max | 4 GB |
| Width | 16 bit |
| Speed | 1600 MHz |
eMMC flash bank[edit | edit source]
On board main storage memory eMMC is connected to the SDIO1 interface and it can act as boot peripheral. The following table reports the eMMC flash specifications:
| CPU connection | SDIO1 |
| Size min | 4 GB |
| Size max | 64 GB |
| Bootable | Yes |
NAND flash bank[edit | edit source]
|
Section not completed yet |
Alternative option for main storage memory can be a 8-bit wide NAND flash connected to the CPU's Raw NAND flash controller. It can act as boot peripheral. The following table reports the NAND flash specifications:
| CPU connection | Raw NAND flash controller |
| Page size | TBD |
| Size min | TBD |
| Size max | TBD |
| Width | 8 bit |
| Chip select | TBD |
| Bootable | Yes |
Memory map[edit | edit source]
For detailed information, please refer to chapter 2 “Memory Maps” of the i.MX8M Nano Applications Processor Reference Manual
Power supply unit[edit | edit source]
MITO 8M Nano embeds all the elements required for powering the unit, therefore power sequencing is self-contained and simplified. Nevertheless, power must be provided from carrier board, and therefore users should be aware of the ranges power supply can assume as well as all other parameters.
