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Created page with "<section begin=History/> {| style="border-collapse:collapse; " ! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History |- ! style="borde..."
<section begin=History/>
{| style="border-collapse:collapse; "
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
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! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Version
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
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| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |1.0.0
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Dec 2020
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release
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==Peripheral LVDS ==
The LVDS interface available on MITO 8M Mini/Nano is based on a MIPI® DSI To FLATLINK™ LVDS bridge IC.
It is directly connected to the MIPI® DSI output port of iMX8M Mini/Nano SOC.
This support covers all aspects of these activities:
* Connectivity to relevant devices - Displays with LVDS receivers
* Arranging the data as required by the external display receiver and by LVDS display standards
* Synchronization and control capabilities
=== Description ===
The LVDS port supports the following standards and features:
* Suitable for 60-fps WUXGA 1920 × 1200 Resolution at 18-bpp and 24-bpp Color, 60 fps 1366 × 768 at 18 bpp and 24 bpp
* Output Configurable for Single-Link or Dual-Link LVDS
* LVDS Output Clock Range of 25 MHz to 154 MHz in Dual-Link or Single-Link Modes
===Pin mapping===
The Pin mapping is described in the [[MITO 8M Mini SOM/MITO 8M Mini Hardware/Pinout_Table | Pinout table section]]
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[[Category:MITO 8M Mini]]
{| style="border-collapse:collapse; "
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
|-
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Version
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
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| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |1.0.0
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Dec 2020
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release
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<section end=History/>
__FORCETOC__
<section begin=Body/>
==Peripheral LVDS ==
The LVDS interface available on MITO 8M Mini/Nano is based on a MIPI® DSI To FLATLINK™ LVDS bridge IC.
It is directly connected to the MIPI® DSI output port of iMX8M Mini/Nano SOC.
This support covers all aspects of these activities:
* Connectivity to relevant devices - Displays with LVDS receivers
* Arranging the data as required by the external display receiver and by LVDS display standards
* Synchronization and control capabilities
=== Description ===
The LVDS port supports the following standards and features:
* Suitable for 60-fps WUXGA 1920 × 1200 Resolution at 18-bpp and 24-bpp Color, 60 fps 1366 × 768 at 18 bpp and 24 bpp
* Output Configurable for Single-Link or Dual-Link LVDS
* LVDS Output Clock Range of 25 MHz to 154 MHz in Dual-Link or Single-Link Modes
===Pin mapping===
The Pin mapping is described in the [[MITO 8M Mini SOM/MITO 8M Mini Hardware/Pinout_Table | Pinout table section]]
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[[Category:MITO 8M Mini]]