Difference between revisions of "MITO 8M Mini SOM/MITO 8M Mini Hardware/Pinout Table"

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(→‎Connectors description)
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−
<section begin="History" />
+
<section begin=History/>
 
{| style="border-collapse:collapse; "
 
{| style="border-collapse:collapse; "
 
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
 
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
 
|-  
 
|-  
 +
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Version
 
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
 
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
 
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
 
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
 
|-
 
|-
−
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |{{oldid|14768|2021/10/11}}
+
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |1.0.0
 +
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Dec 2020
 
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release
 
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release
 
|-
 
|-
−
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |2023/10/26
 
−
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |Update pin information
 
 
|-
 
|-
 
|}
 
|}
−
<section end="History" />
+
<section end=History/>
−
<section begin="Body" />
+
<section begin=Body/>
 
==Connectors and Pinout Table description==
 
==Connectors and Pinout Table description==
  
Line 34: Line 34:
 
The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to MITO 8M Mini pinout specifications. See the images below for reference:
 
The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to MITO 8M Mini pinout specifications. See the images below for reference:
  
−
[[File:MITO8M_Mini-conn-top.png|500px|thumb|MITO 8M Mini/Nano TOP view|none]]
+
[[File:MITO_8M_Mini_-_TOP.jpeg|500px|thumb|MITO 8M TOP view|none]]
−
[[File:MITO8M_Mini-conn-bottom.png|500px|thumb|MITO 8M Mini/Nano BOTTOM view|none]]
+
[[File:MITO_8M_Mini_-_BOTTOM.jpeg|500px|thumb|MITO 8M BOTTOM view|none]]
  
 
Below a detailed description of the pinout, grouped in the following tables:
 
Below a detailed description of the pinout, grouped in the following tables:
Line 48: Line 48:
 
|-
 
|-
 
|'''Pin Name'''  
 
|'''Pin Name'''  
−
| Pin (signal) name on the MITO 8M Mini connectors
+
| Pin (signal) name on the MITO 8M connectors
 
|-
 
|-
 
|'''Internal<br>connections'''  
 
|'''Internal<br>connections'''  
 
| Connections to the components
 
| Connections to the components
−
* CPU.<x> : pin connected to CPU pad (NXP iMX8MM)
+
* CPU.<x> : pin connected to CPU pad named <x>
−
* PMIC.<x> : pin connected to the Power Manager IC (NXP PF8121)
+
* PMIC.<x> : pin connected to the Power Manager IC (NXP PF4210)
 
* LAN.<x> : pin connected to the LAN PHY (MICROCHIP KSZ9031RNX)
 
* LAN.<x> : pin connected to the LAN PHY (MICROCHIP KSZ9031RNX)
 
* BRIDGE.<x>  : pin connected to the MIPI-to-LVDS bridge (TI SN65DSI84)
 
* BRIDGE.<x>  : pin connected to the MIPI-to-LVDS bridge (TI SN65DSI84)
Line 286: Line 286:
 
| rowspan="4" |GPIO1_IO00
 
| rowspan="4" |GPIO1_IO00
 
| rowspan="4" |CPU.GPIO1_IO00
 
| rowspan="4" |CPU.GPIO1_IO00
−
| rowspan="4" |AG14
+
| rowspan="4" |T6
 
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |I/O
 
| rowspan="4" |I/O
Line 297: Line 297:
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|CCM_REF_CLK_32K
+
|ANAMIX_REF_CLK_32K
 
|-
 
|-
 
|ALT6
 
|ALT6
Line 305: Line 305:
 
| rowspan="4" |GPIO1_IO01
 
| rowspan="4" |GPIO1_IO01
 
| rowspan="4" |CPU.GPIO1_IO01
 
| rowspan="4" |CPU.GPIO1_IO01
−
| rowspan="4" |AF14
+
| rowspan="4" |T7
 
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |I/O
 
| rowspan="4" |I/O
Line 316: Line 316:
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|CCM_REF_CLK_24M
+
|ANAMIX_REF_CLK_25M
 
|-
 
|-
 
|ALT6
 
|ALT6
Line 324: Line 324:
 
| rowspan="3" |SPDIF_EXT_CLK
 
| rowspan="3" |SPDIF_EXT_CLK
 
| rowspan="3" |CPU.SPDIF_EXT_CLK
 
| rowspan="3" |CPU.SPDIF_EXT_CLK
−
| rowspan="3" |AF8
+
| rowspan="3" |E6
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
Line 340: Line 340:
 
| rowspan="3" |GPIO1_IO13
 
| rowspan="3" |GPIO1_IO13
 
| rowspan="3" |CPU.GPIO1_IO13
 
| rowspan="3" |CPU.GPIO1_IO13
−
| rowspan="3" |AD9
+
| rowspan="3" |K6
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
−
| rowspan="3" |
+
| rowspan="3" |Internally used, do not connect
 
|ALT0
 
|ALT0
 
|GPIO1_IO13
 
|GPIO1_IO13
Line 353: Line 353:
 
|PWM2_OUT
 
|PWM2_OUT
 
|-
 
|-
−
| rowspan="2" |J1.45
+
|J1.45
−
| rowspan="2" |GPIO1_IO11
+
|VDD_PHY_1V8
−
| rowspan="2" |CPU.GPIO1_IO11
+
|
−
| rowspan="2" |AC10
+
|
−
| rowspan="2" |NVCC_3V3
+
|
−
| rowspan="2" |I/O
+
|
−
| rowspan="2" |Internally used for ETH CLK enable, do not connect
+
|
−
|ALT0
+
|
−
|GPIO1_IO11
+
|
−
|-
 
−
|ALT1
 
−
|USB1_OTG_ID
 
 
|-
 
|-
 
| rowspan="3" |J1.47
 
| rowspan="3" |J1.47
 
| rowspan="3" |ECSPI2_SCLK
 
| rowspan="3" |ECSPI2_SCLK
 
| rowspan="3" |CPU.ECSPI2_SCLK
 
| rowspan="3" |CPU.ECSPI2_SCLK
−
| rowspan="3" |E6
+
| rowspan="3" |C5
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
Line 385: Line 382:
 
| rowspan="3" |ECSPI2_MOSI
 
| rowspan="3" |ECSPI2_MOSI
 
| rowspan="3" |CPU.ECSPI2_MOSI
 
| rowspan="3" |CPU.ECSPI2_MOSI
−
| rowspan="3" |B8
+
| rowspan="3" |E5
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
Line 401: Line 398:
 
| rowspan="3" |GPIO1_IO08
 
| rowspan="3" |GPIO1_IO08
 
| rowspan="3" |CPU.GPIO1_IO08
 
| rowspan="3" |CPU.GPIO1_IO08
−
| rowspan="3" |AG10
+
| rowspan="3" |N7
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
Line 414: Line 411:
 
|USDHC2_RESET_B
 
|USDHC2_RESET_B
 
|-
 
|-
−
| rowspan="4" |J1.53
+
| rowspan="3" |J1.53
−
| rowspan="4" |GPIO1_IO09
+
| rowspan="3" |GPIO1_IO09
−
| rowspan="4" |CPU.GPIO1_IO09
+
| rowspan="3" |CPU.GPIO1_IO09
−
| rowspan="4" |AF10
+
| rowspan="3" |M7
−
| rowspan="4" |NVCC_3V3
+
| rowspan="3" |NVCC_3V3
−
| rowspan="4" |I/O
+
| rowspan="3" |I/O
−
| rowspan="4" |
+
| rowspan="3" |
 
|ALT0
 
|ALT0
 
|GPIO1_IO09
 
|GPIO1_IO09
Line 426: Line 423:
 
|ALT1
 
|ALT1
 
|ENET1_1588_EVENT0_OUT
 
|ENET1_1588_EVENT0_OUT
−
|-
 
−
|ALT4
 
−
|USDHC3_RESET_B
 
 
|-
 
|-
 
|ALT5
 
|ALT5
Line 436: Line 430:
 
| rowspan="3" |ECSPI2_MISO
 
| rowspan="3" |ECSPI2_MISO
 
| rowspan="3" |CPU.ECSPI2_MISO
 
| rowspan="3" |CPU.ECSPI2_MISO
−
| rowspan="3" |A8
+
| rowspan="3" |B5
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
Line 462: Line 456:
 
| rowspan="3" |ECSPI2_SS0
 
| rowspan="3" |ECSPI2_SS0
 
| rowspan="3" |CPU.ECSPI2_SS0
 
| rowspan="3" |CPU.ECSPI2_SS0
−
| rowspan="3" |A6
+
| rowspan="3" |A5
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
Line 471: Line 465:
 
|ALT1
 
|ALT1
 
|UART4_RTS_B
 
|UART4_RTS_B
−
(Configure register IOMUXC_UART4_RTS_B_SELECT_INPUT for mode ALT1)
 
 
|-
 
|-
 
|ALT5
 
|ALT5
Line 479: Line 472:
 
| rowspan="3" |GPIO1_IO05
 
| rowspan="3" |GPIO1_IO05
 
| rowspan="3" |CPU.GPIO1_IO05
 
| rowspan="3" |CPU.GPIO1_IO05
−
| rowspan="3" |AF12
+
| rowspan="3" |P7
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
Line 493: Line 486:
 
|CCM_PMIC_READY
 
|CCM_PMIC_READY
 
|-
 
|-
−
| rowspan="4" |J1.63
+
| rowspan="3" |J1.63
−
| rowspan="4" |SAI5_RXD0
+
| rowspan="3" |I2C2_SCL
−
| rowspan="4" |CPU.SAI5_RXD0
+
| rowspan="3" |CPU.I2C2_SCL
−
| rowspan="4" |AD18
+
| rowspan="3" |G7
−
| rowspan="4" |NVCC_3V3
+
| rowspan="3" |NVCC_3V3
−
| rowspan="4" |I/O
+
| rowspan="3" |I/O
−
| rowspan="4" |
+
| rowspan="3" |
 
|ALT0
 
|ALT0
−
|SAI5_RX_DATA0
+
|I2C2_SCL
−
( Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_0 for mode ALT0)
 
 
|-
 
|-
 
|ALT1
 
|ALT1
−
|SAI1_TX_DATA2
+
|ENET1_1588_EVENT1_IN
−
|-
 
−
|ALT4
 
−
|PDM_BIT_STREAM0
 
−
(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_0 for mode ALT4)
 
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|GPIO3_IO21
+
|GPIO5_IO16
 
|-
 
|-
−
| rowspan="6" |J1.65
+
| rowspan="3" |J1.65
−
| rowspan="6" |SAI5_RXD1
+
| rowspan="3" |I2C2_SDA
−
| rowspan="6" |CPU.SAI5_RXD1
+
| rowspan="3" |CPU.I2C2_SDA
−
| rowspan="6" |AC14
+
| rowspan="3" |F7
−
| rowspan="6" |NVCC_3V3
+
| rowspan="3" |NVCC_3V3
−
| rowspan="6" |I/O
+
| rowspan="3" |I/O
−
| rowspan="6" |
+
| rowspan="3" |
 
|ALT0
 
|ALT0
−
|SAI5_RX_DATA1
+
|I2C2_SDA
−
(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_1 for mode ALT0)
 
 
|-
 
|-
 
|ALT1
 
|ALT1
−
|SAI1_TX_DATA3
+
|ENET1_1588_EVENT1_OUT
−
|-
 
−
|ALT2
 
−
|SAI1_TX_SYNC
 
−
(Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT2)
 
−
|-
 
−
|ALT3
 
−
|SAI5_TX_SYNC
 
−
(Configure register IOMUXC_SAI5_TX_SYNC_SELECT_INPUT for mode ALT3)
 
−
|-
 
−
|ALT4
 
−
|PDM_BIT_STREAM1
 
−
(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_1 for mode ALT4)
 
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|GPIO3_IO22
+
|GPIO5_IO17
 
|-
 
|-
 
| rowspan="4" |J1.67
 
| rowspan="4" |J1.67
 
| rowspan="4" |GPIO1_IO06
 
| rowspan="4" |GPIO1_IO06
 
| rowspan="4" |CPU.GPIO1_IO06
 
| rowspan="4" |CPU.GPIO1_IO06
−
| rowspan="4" |AG11
+
| rowspan="4" |N5
 
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |I/O
 
| rowspan="4" |I/O
Line 562: Line 537:
 
|CCM_EXT_CLK3
 
|CCM_EXT_CLK3
 
|-
 
|-
−
| rowspan="4" |J1.69
+
| rowspan="3" |J1.69
−
| rowspan="4" |SAI2_RXC
+
| rowspan="3" |SAI2_RXC
−
| rowspan="4" |CPU.SAI2_RXC
+
| rowspan="3" |CPU.SAI2_RXC
−
| rowspan="4" |AB22
+
| rowspan="3" |H3
−
| rowspan="4" |NVCC_3V3
+
| rowspan="3" |NVCC_3V3
−
| rowspan="4" |I/O
+
| rowspan="3" |I/O
−
| rowspan="4" |
+
| rowspan="3" |
 
|ALT0
 
|ALT0
 
|SAI2_RX_BCLK
 
|SAI2_RX_BCLK
Line 574: Line 549:
 
|ALT1
 
|ALT1
 
|SAI5_TX_BCLK
 
|SAI5_TX_BCLK
−
(Configure register IOMUXC_SAI5_TX_BCLK_SELECT_INPUT for mode ALT1)
 
−
|-
 
−
|ALT4
 
−
|UART1_RX
 
 
|-
 
|-
 
|ALT5
 
|ALT5
 
|GPIO4_IO22
 
|GPIO4_IO22
 
|-
 
|-
−
| rowspan="6" |J1.71
+
| rowspan="3" |J1.71
−
| rowspan="6" |SAI2_RXFS
+
| rowspan="3" |SAI2_RXFS
−
| rowspan="6" |CPU.SAI2_RXFS
+
| rowspan="3" |CPU.SAI2_RXFS
−
| rowspan="6" |AC19
+
| rowspan="3" |J4
−
| rowspan="6" |NVCC_3V3
+
| rowspan="3" |NVCC_3V3
−
| rowspan="6" |I/O
+
| rowspan="3" |I/O
−
| rowspan="6" |
+
| rowspan="3" |
 
|ALT0
 
|ALT0
 
|SAI2_RX_SYNC
 
|SAI2_RX_SYNC
Line 594: Line 565:
 
|ALT1
 
|ALT1
 
|SAI5_TX_SYNC
 
|SAI5_TX_SYNC
−
(Configure register IOMUXC_SAI5_TX_SYNC_SELECT_INPUT for mode ALT1)
 
−
|-
 
−
|ALT2
 
−
|SAI5_TX_DATA1
 
−
|-
 
−
|ALT3
 
−
|SAI2_RX_DATA1
 
−
|-
 
−
|ALT4
 
−
|UART1_TX
 
 
|-
 
|-
 
|ALT5
 
|ALT5
Line 621: Line 582:
 
| rowspan="2" |SD2_DATA0
 
| rowspan="2" |SD2_DATA0
 
| rowspan="2" |CPU.SD2_DATA0
 
| rowspan="2" |CPU.SD2_DATA0
−
| rowspan="2" |AB23
+
| rowspan="2" |N22
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |I/O
 
| rowspan="2" |I/O
Line 634: Line 595:
 
| rowspan="2" |SD2_DATA1
 
| rowspan="2" |SD2_DATA1
 
| rowspan="2" |CPU.SD2_DATA1
 
| rowspan="2" |CPU.SD2_DATA1
−
| rowspan="2" |AB24
+
| rowspan="2" |N21
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |I/O
 
| rowspan="2" |I/O
Line 647: Line 608:
 
| rowspan="2" |SD2_DATA2
 
| rowspan="2" |SD2_DATA2
 
| rowspan="2" |CPU.SD2_DATA2
 
| rowspan="2" |CPU.SD2_DATA2
−
| rowspan="2" |V24
+
| rowspan="2" |P22
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |I/O
 
| rowspan="2" |I/O
Line 660: Line 621:
 
| rowspan="2" |SD2_DATA3
 
| rowspan="2" |SD2_DATA3
 
| rowspan="2" |CPU.SD2_DATA03
 
| rowspan="2" |CPU.SD2_DATA03
−
| rowspan="2" |V23
+
| rowspan="2" |P21
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |I/O
 
| rowspan="2" |I/O
Line 673: Line 634:
 
| rowspan="2" |SD2_CMD
 
| rowspan="2" |SD2_CMD
 
| rowspan="2" |CPU.SD2_CMD
 
| rowspan="2" |CPU.SD2_CMD
−
| rowspan="2" |W24
+
| rowspan="2" |M22
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |I/O
 
| rowspan="2" |I/O
Line 686: Line 647:
 
| rowspan="2" |SD2_CLK
 
| rowspan="2" |SD2_CLK
 
| rowspan="2" |CPU.SD2_CLK
 
| rowspan="2" |CPU.SD2_CLK
−
| rowspan="2" |W23
+
| rowspan="2" |L22
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |I/O
 
| rowspan="2" |I/O
Line 706: Line 667:
 
|
 
|
 
|-
 
|-
−
| rowspan="4" |J1.89
+
| rowspan="3" |J1.89
−
| rowspan="4" |UART3_TXD
+
| rowspan="3" |UART3_TXD
−
| rowspan="4" |CPU.UART3_TXD
+
| rowspan="3" |CPU.UART3_TXD
−
| rowspan="4" |D18
+
| rowspan="3" |B7
−
| rowspan="4" |NVCC_3V3
+
| rowspan="3" |NVCC_3V3
−
| rowspan="4" |I/O
+
| rowspan="3" |I/O
−
| rowspan="4" |Internally pulled-up to NVCC_3V3
+
| rowspan="3" |
 
|ALT0
 
|ALT0
 
|UART3_TX
 
|UART3_TX
Line 718: Line 679:
 
|ALT1
 
|ALT1
 
|UART1_RTS_B
 
|UART1_RTS_B
−
(Configure register IOMUXC_UART1_RTS_B_SELECT_INPUT for mode ALT1)
 
−
|-
 
−
|ALT2
 
−
|USDHC3_VSELECT
 
 
|-
 
|-
 
|ALT5
 
|ALT5
 
|GPIO5_IO27
 
|GPIO5_IO27
 
|-
 
|-
−
| rowspan="4" |J1.91
+
| rowspan="3" |J1.91
−
| rowspan="4" |UART3_RXD
+
| rowspan="3" |UART3_RXD
−
| rowspan="4" |CPU.UART3_RXD
+
| rowspan="3" |CPU.UART3_RXD
−
| rowspan="4" |E18
+
| rowspan="3" |A6
−
| rowspan="4" |NVCC_3V3
+
| rowspan="3" |NVCC_3V3
−
| rowspan="4" |I/O
+
| rowspan="3" |I/O
−
| rowspan="4" |
+
| rowspan="3" |
 
|ALT0
 
|ALT0
 
|UART3_RX
 
|UART3_RX
Line 738: Line 695:
 
|ALT1
 
|ALT1
 
|UART1_CTS_B
 
|UART1_CTS_B
−
|-
 
−
|ALT2
 
−
|USDHC3_RESET_B
 
 
|-
 
|-
 
|ALT5
 
|ALT5
 
|GPIO5_IO26
 
|GPIO5_IO26
 
|-
 
|-
−
| rowspan="3" |J1.93
+
| rowspan="4" |J1.93
−
| rowspan="3" |UART1_TXD
+
| rowspan="4" |UART4_TXD
−
| rowspan="3" |CPU.UART1_TXD
+
| rowspan="4" |CPU.UART4_TXD
−
| rowspan="3" |F13
+
| rowspan="4" |D7
−
| rowspan="3" |NVCC_3V3
+
| rowspan="4" |NVCC_3V3
−
| rowspan="3" |I/O
+
| rowspan="4" |I/O
−
| rowspan="3" |
+
| rowspan="4" |
 
|ALT0
 
|ALT0
−
|UART1_TX
+
|UART4_TX
 
|-
 
|-
 
|ALT1
 
|ALT1
−
|ECSPI3_MOSI
+
|UART2_RTS_B
 +
|-
 +
|ALT2
 +
|PCIE2_CLKREQ_B
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|GPIO5_IO23
+
|GPIO5_IO29
 
|-
 
|-
−
| rowspan="3" |J1.95
+
| rowspan="4" |J1.95
−
| rowspan="3" |UART1_RXD
+
| rowspan="4" |UART4_RXD
−
| rowspan="3" |CPU.UART1_RXD
+
| rowspan="4" |CPU.UART4_RXD
−
| rowspan="3" |E14
+
| rowspan="4" |C6
−
| rowspan="3" |NVCC_3V3
+
| rowspan="4" |NVCC_3V3
−
| rowspan="3" |I/O
+
| rowspan="4" |I/O
−
| rowspan="3" |
+
| rowspan="4" |
 
|ALT0
 
|ALT0
−
|UART1_RX
+
|UART4_RX
 
|-
 
|-
 
|ALT1
 
|ALT1
−
|ECSPI3_SCLK
+
|UART2_CTS_B
 +
|-
 +
|ALT2
 +
|PCIE1_CLKREQ_B
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|GPIO5_IO22
+
|GPIO5_IO28
 
|-
 
|-
 
| rowspan="2" |J1.97
 
| rowspan="2" |J1.97
 
| rowspan="2" |SD2_WP
 
| rowspan="2" |SD2_WP
 
| rowspan="2" |CPU.SD2_WP
 
| rowspan="2" |CPU.SD2_WP
−
| rowspan="2" |AA27
+
| rowspan="2" |M21
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |I/O
 
| rowspan="2" |I/O
Line 793: Line 753:
 
| rowspan="2" |SD2_RST_B
 
| rowspan="2" |SD2_RST_B
 
| rowspan="2" |CPU.SD2_RESET_B
 
| rowspan="2" |CPU.SD2_RESET_B
−
| rowspan="2" |AB26
+
| rowspan="2" |R22
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |I/O
 
| rowspan="2" |I/O
Line 803: Line 763:
 
|GPIO2_IO19
 
|GPIO2_IO19
 
|-
 
|-
−
| rowspan="4" |J1.101
+
|J1.101
−
| rowspan="4" |I2C2_SCL
+
|HDMI_DDC_SCL
−
| rowspan="4" |CPU.I2C2_SCL
+
|CPU.HDMI_DDC_SCL
−
| rowspan="4" |D10
+
|R3
−
| rowspan="4" |NVCC_3V3
+
|VDD_PHY_1V8
−
| rowspan="4" |I/O
+
|I/O
−
| rowspan="4" |
+
|
−
|ALT0
+
|
−
|I2C2_SCL
+
|
 
|-
 
|-
−
|ALT1
+
|J1.103
−
|ENET1_1588_EVENT1_IN
+
|HDMI_DDC_SDA
 +
|CPU.HDMI_DDC_SDA
 +
|P3
 +
|VDD_PHY_1V8
 +
|I/O
 +
|
 +
|
 +
|
 
|-
 
|-
−
|ALT2
+
|J1.105
−
|USDHC3_CD_B
+
|HDMI_AUX_N
−
(Configure register IOMUXC_USDHC3_CD_B_SELECT_INPUT for mode ALT2)
+
|CPU.HDMI_AUX_N
 +
|V2
 +
| -
 +
|D
 +
|connected with capacitor in series
 +
|
 +
|
 
|-
 
|-
−
|ALT5
+
|J1.107
−
|GPIO5_IO16
+
|HDMI_AUX_P
 +
|CPU.HDMI_AUX_P
 +
|V1
 +
| -
 +
|D
 +
|connected with capacitor in series
 +
|
 +
|
 
|-
 
|-
−
| rowspan="4" |J1.103
+
|J1.109
−
| rowspan="4" |I2C2_SDA
+
|DGND
−
| rowspan="4" |CPU.I2C2_SDA
+
|DGND
−
| rowspan="4" |D9
+
| -
−
| rowspan="4" |NVCC_3V3
+
| -
−
| rowspan="4" |I/O
+
|G
−
| rowspan="4" |
+
|
−
|ALT0
+
|
−
|I2C2_SDA
+
|
 
|-
 
|-
−
|ALT1
+
|J1.111
−
|ENET1_1588_EVENT1_OUT
+
|HDMI_TX_M_LN_3
 +
|CPU.HDMI_TX_M_LN_3
 +
|M2
 +
| -
 +
|D
 +
|connected with capacitor in series
 +
|
 +
|
 
|-
 
|-
−
|ALT2
+
|J1.113
−
|USDHC3_WP
+
|HDMI_TX_P_LN_3
−
(Configure register IOMUXC_USDHC3_WP_SELECT_INPUT for mode ALT2)
+
|CPU.HDMI_TX_P_LN_3
 +
|M1
 +
| -
 +
|D
 +
|connected with capacitor in series
 +
|
 +
|
 
|-
 
|-
−
|ALT5
+
|J1.115
−
|GPIO5_IO17
+
|HDMI_TX_M_LN_0
 +
|CPU.HDMI_TX_M_LN_0
 +
|T2
 +
| -
 +
|D
 +
|connected with capacitor in series
 +
|
 +
|
 
|-
 
|-
−
| rowspan="6" |J1.105
+
|J1.117
−
| rowspan="6" |SAI1_RXD3
+
|HDMI_TX_P_LN_0
−
| rowspan="6" |CPU.SAI1_RXD3
+
|CPU.HDMI_TX_P_LN_0
−
| rowspan="6" |AF17
+
|T1
−
| rowspan="6" | NVCC_3V3
+
| -
−
| rowspan="6" |I/O
+
|D
−
| rowspan="6" |Internally used for BOOT mode configuration:
+
|connected with capacitor in series
−
 
+
|
−
can be pulled-up or down depending on
+
|
−
 
 
−
[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
 
−
|ALT0
 
−
|SAI1_RX_DATA3
 
 
|-
 
|-
−
|ALT1
+
|J1.119
−
|SAI5_RX_DATA3
+
|HDMI_TX_M_LN_1
−
(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_3 for mode ALT1)
+
|CPU.HDMI_TX_M_LN_1
 +
|U1
 +
| -
 +
|D
 +
|connected with capacitor in series
 +
|
 +
|
 
|-
 
|-
−
|ALT3
+
|J1.121
−
|PDM_BIT_STREAM3
+
|HDMI_TX_P_LN_1
−
(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_3 for mode ALT3)
+
|CPU.HDMI_TX_P_LN_1
 +
|U2
 +
| -
 +
|D
 +
|connected with capacitor in series
 +
|
 +
|
 
|-
 
|-
−
|ALT4
+
|J1.123
−
|CORESIGHT_TRACE3
+
|HDMI_TX_M_LN_2
 +
|CPU.HDMI_TX_M_LN_2
 +
|N1
 +
| -
 +
|D
 +
|connected with capacitor in series
 +
|
 +
|
 
|-
 
|-
−
|ALT5
+
|J1.125
−
|GPIO4_IO05
+
|HDMI_TX_P_LN_2
 +
|CPU.HDMI_TX_P_LN_2
 +
|N2
 +
| -
 +
|D
 +
|connected with capacitor in series
 +
|
 +
|
 
|-
 
|-
−
|ALT6
+
|J1.127
−
|SRC_BOOT_CFG3
+
|HDMI_CEC
 +
|CPU.HDMI_CEC
 +
|W3
 +
|VDD_PHY_1V8
 +
|I/O
 +
|
 +
|
 +
|
 
|-
 
|-
−
| rowspan="5" |J1.107
+
|J1.129
−
| rowspan="5" |SAI1_TXD3
+
|HDMI_HPD
−
| rowspan="5" |CPU.SAI1_TXD3
+
|CPU.HDMI_HPD
−
| rowspan="5" |AF21
+
|W2
−
| rowspan="5" | NVCC_3V3
+
|VDD_PHY_1V8
−
| rowspan="5" |I/O
+
|I/O
−
| rowspan="5" |Internally used for BOOT mode configuration:
+
|
−
 
+
|
−
can be pulled-up or down depending on
+
|
−
 
 
−
[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
 
−
|ALT0
 
−
|SAI1_TX_DATA3
 
 
|-
 
|-
−
|ALT1
+
|J1.131
−
|SAI5_TX_DATA3
 
−
|-
 
−
|ALT4
 
−
|CORESIGHT_TRACE11
 
−
|-
 
−
|ALT5
 
−
|GPIO4_IO15
 
−
|-
 
−
|ALT6
 
−
|SRC_BOOT_CFG11
 
−
|-
 
−
|J1.109
 
 
|DGND  
 
|DGND  
 
|DGND
 
|DGND
Line 910: Line 923:
 
|
 
|
 
|-
 
|-
−
| rowspan="4" |J1.111
+
|J1.133
−
| rowspan="4" |SAI1_TXFS
+
|LVDS0_CLK_N
−
| rowspan="4" |CPU.SAI1_TXFS
+
|BRIDGE.A_CLKN
−
| rowspan="4" |AB19
+
|F9
−
| rowspan="4" |NVCC_3V3
+
| -
−
| rowspan="4" |I/O
+
|D
−
| rowspan="4" |
+
|
−
|ALT0
+
|
−
|SAI1_TX_SYNC
+
|
−
 
 
−
(Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT0)
 
 
|-
 
|-
−
|ALT1
+
|J1.135
−
|SAI5_TX_SYNC
+
|LVDS0_CLK_P
−
(Configure register IOMUXC_SAI5_TX_SYNC_SELECT_INPUT for mode ALT1)
+
|BRIDGE.A_CLKP
 +
|F8
 +
| -
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
|ALT4
+
|J1.137
−
|CORESIGHT_EVENTO
+
|LVDS0_TX0_N
 +
|BRIDGE.A_Y0N
 +
|C9
 +
| -
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
|ALT5
+
|J1.139
−
|GPIO4_IO10
+
|LVDS0_TX0_P
 +
|BRIDGE.A_Y0P
 +
|C8
 +
| -
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
| rowspan="4" |J1.113
+
|J1.141
−
| rowspan="4" |SAI1_TXC
+
|LVDS0_TX1_N
−
| rowspan="4" |CPU.SAI1_TXC
+
|BRIDGE.A_Y1N
−
| rowspan="4" |AC18
+
|D9
−
| rowspan="4" |NVCC_3V3
+
| -
−
| rowspan="4" |I/O
+
|D
−
| rowspan="4" |
+
|
−
|ALT0
+
|
−
|SAI1_TX_BCLK
+
|
−
 
 
−
(Configure register IOMUXC_SAI1_TX_BCLK_SELECT_INPUT for mode ALT0)
 
 
|-
 
|-
−
|ALT1
+
|J1.143
−
|SAI5_TX_BCLK
+
|LVDS0_TX1_P
−
(Configure register IOMUXC_SAI5_TX_BCLK_SELECT_INPUT for mode ALT1)
+
|BRIDGE.A_Y1P
 +
|D8
 +
| -
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
|ALT4
+
|J1.145
−
|CORESIGHT_EVENTI
+
|LVDS0_TX2_N
 +
|BRIDGE.A_Y2N
 +
|E9
 +
| -
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
|ALT5
+
|J1.147
−
|GPIO4_IO11
+
|LVDS0_TX2_P
−
|-
+
|BRIDGE.A_Y2P
−
| rowspan="5" |J1.115
+
|E8
−
| rowspan="5" |SAI1_TXD0
+
| -
−
| rowspan="5" |CPU.SAI1_TXD0
+
|D
−
| rowspan="5" |AG20
+
|
−
| rowspan="5" |NVCC_3V3
+
|
−
| rowspan="5" |I/O
+
|
−
| rowspan="5" |Internally used for BOOT mode configuration:
 
−
 
 
−
can be pulled-up or down depending on
 
−
 
 
−
[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
 
−
|ALT0
 
−
|SAI1_TX_DATA0
 
 
|-
 
|-
−
|ALT1
+
|J1.149
−
|SAI5_TX_DATA0
+
|LVDS0_TX3_N
 +
|BRIDGE.A_Y3N
 +
|G9
 +
| -
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
|ALT4
+
|J1.151
−
|CORESIGHT_TRACE8
+
|LVDS0_TX3_P
 +
|BRIDGE.A_Y3P
 +
|G8
 +
| -
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
|ALT5
+
|J1.153
−
|GPIO4_IO12
+
|DGND
−
|-
+
|DGND
−
|ALT6
+
| -
−
|SRC_BOOT_CFG8
+
| -
 +
|G
 +
|
 +
|
 +
|
 
|-
 
|-
−
| rowspan="5" |J1.117
+
|J1.155
−
| rowspan="5" |SAI1_TXD1
+
|LVDS1_CLK_N
−
| rowspan="5" |CPU.SAI1_TXD1
+
|BRIDGE.B_CLKN
−
| rowspan="5" |AF20
+
|A6
−
| rowspan="5" |NVCC_3V3
+
| -
−
| rowspan="5" |I/O
+
|D
−
| rowspan="5" |Internally used for BOOT mode configuration:
+
|
−
 
+
|
−
can be pulled-up or down depending on
+
|
−
 
 
−
[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
 
−
|ALT0
 
−
|SAI1_TX_DATA1
 
 
|-
 
|-
−
|ALT1
+
|J1.157
−
|SAI5_TX_DATA1
+
|LVDS1_CLK_P
 +
|BRIDGE.B_CLKP
 +
|B6
 +
| -
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
|ALT4
+
|J1.159
−
|CORESIGHT_TRACE9
+
|LVDS1_TX0_N
−
|-
+
|BRIDGE.B_Y0N
−
|ALT5
+
|A3
−
|GPIO4_IO13
+
| -
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
|ALT6
+
|J1.161
−
|SRC_BOOT_CFG9
+
|LVDS1_TX0_P
 +
|BRIDGE.B_Y0P
 +
|B3
 +
| -
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
| rowspan="5" |J1.119
+
|J1.163
−
| rowspan="5" |SAI1_TXD2
+
|LVDS1_TX1_N
−
| rowspan="5" |CPU.SAI1_TXD2
+
|BRIDGE.B_Y1N
−
| rowspan="5" |AG21
+
|A4
−
| rowspan="5" |NVCC_3V3
+
| -
−
| rowspan="5" |I/O
+
|D
−
| rowspan="5" |Internally used for BOOT mode configuration:
+
|
−
 
+
|
−
can be pulled-up or down depending on
+
|
−
 
 
−
[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
 
−
|ALT0
 
−
|SAI1_TX_DATA2
 
 
|-
 
|-
−
|ALT1
+
|J1.165
−
|SAI5_TX_DATA2
+
|LVDS1_TX1_P
 +
|BRIDGE.B_Y1P
 +
|B4
 +
| -
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
|ALT4
+
|J1.167
−
|CORESIGHT_TRACE10
+
|LVDS1_TX2_N
 +
|BRIDGE.B_Y2N
 +
|A5
 +
| -
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
|ALT5
+
|J1.169
−
|GPIO4_IO14
+
|LVDS1_TX2_P
 +
|BRIDGE.B_Y2P
 +
|B5
 +
| -
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
|ALT6
+
|J1.171
−
|SRC_BOOT_CFG10
+
|LVDS1_TX3_N
−
|-
+
|BRIDGE.B_Y3N
−
| rowspan="4" |J1.121
+
|A7
−
| rowspan="4" |SAI1_RXFS
+
| -
−
| rowspan="4" |CPU.SAI1_RXFS
+
|D
−
| rowspan="4" |AG16
+
|
−
| rowspan="4" |NVCC_3V3
+
|
−
| rowspan="4" |I/O
+
|
−
| rowspan="4" |
 
−
|ALT0
 
−
|SAI1_RX_SYNC
 
−
 
 
−
(Configure register IOMUXC_SAI1_RX_SYNC_SELECT_INPUT for mode ALT0)
 
 
|-
 
|-
−
|ALT1
+
|J1.173
−
|SAI5_RX_SYNC
+
|LVDS1_TX3_P
−
(Configure register IOMUXC_SAI5_RX_SYNC_SELECT_INPUT for mode ALT1)
+
|BRIDGE.B_Y3P
 +
|B7
 +
| -
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
|ALT4
+
|J1.175
−
|CORESIGHT_TRACE_CLK
+
|DGND
 +
|DGND
 +
| -
 +
| -
 +
|G
 +
|
 +
|
 +
|
 
|-
 
|-
−
|ALT5
+
| rowspan="2" |J1.177
−
|GPIO4_IO00
+
| rowspan="2" |SD2_CD_B
−
|-
+
| rowspan="2" |CPU.SD2_CD_B
−
| rowspan="4" |J1.123
+
| rowspan="2" |L21
−
| rowspan="4" |SAI1_RXC
+
| rowspan="2" |NVCC_3V3
−
| rowspan="4" |CPU.SAI1_RXC
+
| rowspan="2" |I/O
−
| rowspan="4" |AF16
+
| rowspan="2" |
−
| rowspan="4" |NVCC_3V3
 
−
| rowspan="4" |I/O
 
−
| rowspan="4" |
 
 
|ALT0
 
|ALT0
−
|SAI1_RX_BCLK
+
|USDHC2_CD_B
−
|-
 
−
|ALT1
 
−
|SAI5_RX_BCLK
 
−
(Configure register IOMUXC_SAI5_RX_BCLK_SELECT_INPUT for mode ALT1)
 
−
|-
 
−
|ALT4
 
−
|CORESIGHT_TRACE_CTL
 
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|GPIO4_IO01
+
|GPIO2_IO12
 
|-
 
|-
−
| rowspan="7" |J1.125
+
| rowspan="3" |J1.179
−
| rowspan="7" |SAI1_RXD0
+
| rowspan="3" |ECSPI1_SS0
−
| rowspan="7" |CPU.SAI1_RXD0
+
| rowspan="3" |CPU.ECSPI1_SS0
−
| rowspan="7" |AG15
+
| rowspan="3" |D4
−
| rowspan="7" |NVCC_3V3
+
| rowspan="3" |NVCC_3V3
−
| rowspan="7" |I/O
+
| rowspan="3" |I/O
−
| rowspan="7" |Internally used for BOOT mode configuration:
+
| rowspan="3" |
−
 
 
−
can be pulled-up or down depending on
 
−
 
 
−
[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
 
 
|ALT0
 
|ALT0
−
|SAI1_RX_DATA0
+
|ECSPI1_SS0
 
|-
 
|-
 
|ALT1
 
|ALT1
−
|SAI5_RX_DATA0
+
|UART3_RTS_B
−
(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_0 for mode ALT1)
 
−
|-
 
−
|ALT2
 
−
|SAI1_TX_DATA1
 
−
|-
 
−
|ALT3
 
−
|PDM_BIT_STREAM0
 
−
(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_0 for mode ALT3)
 
−
|-
 
−
|ALT4
 
−
|CORESIGHT_TRACE0
 
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|GPIO4_IO02
+
|GPIO5_IO09
 
|-
 
|-
−
|ALT6
+
| rowspan="3" |J1.181
−
|SRC_BOOT_CFG0
+
| rowspan="3" |ECSPI1_SCLK
−
|-
+
| rowspan="3" |CPU.ECSPI1_SCLK
−
| rowspan="6" |J1.127
+
| rowspan="3" |D5
−
| rowspan="6" |SAI1_RXD1
+
| rowspan="3" |NVCC_3V3
−
| rowspan="6" |CPU.SAI1_RXD1
+
| rowspan="3" |I/O
−
| rowspan="6" |AF15
+
| rowspan="3" |
−
| rowspan="6" |NVCC_3V3
 
−
| rowspan="6" |I/O
 
−
| rowspan="6" |Internally used for BOOT mode configuration:
 
−
 
 
−
can be pulled-up or down depending on
 
−
 
 
−
[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
 
 
|ALT0
 
|ALT0
−
|SAI1_RX_DATA1
+
|ECSPI1_SCLK
 
|-
 
|-
 
|ALT1
 
|ALT1
−
|SAI5_RX_DATA1
+
|UART3_RX
−
(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_1 for mode ALT1)
 
−
|-
 
−
|ALT3
 
−
|PDM_BIT_STREAM1
 
−
(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_1 for mode ALT3)
 
−
|-
 
−
|ALT4
 
−
|CORESIGHT_TRACE1
 
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|GPIO4_IO03
+
|GPIO5_IO06
 
|-
 
|-
−
|ALT6
+
| rowspan="3" |J1.183
−
|SRC_BOOT_CFG1
+
| rowspan="3" |ECSPI1_MISO
−
|-
+
| rowspan="3" |CPU.ECSPI1_MISO
−
| rowspan="6" |J1.129
+
| rowspan="3" |B4
−
| rowspan="6" |SAI1_RXD2
+
| rowspan="3" |NVCC_3V3
−
| rowspan="6" |CPU.SAI1_RXD2
+
| rowspan="3" |I/O
−
| rowspan="6" |AG17
+
| rowspan="3" |
−
| rowspan="6" |NVCC_3V3
 
−
| rowspan="6" |I/O
 
−
| rowspan="6" |Internally used for BOOT mode configuration:
 
−
 
 
−
can be pulled-up or down depending on
 
−
 
 
−
[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
 
 
|ALT0
 
|ALT0
−
|SAI1_RX_DATA2
+
|ECSPI1_MISO
 
|-
 
|-
 
|ALT1
 
|ALT1
−
|SAI5_RX_DATA2
+
|UART3_CTS_B
−
(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_2 for mode ALT1)
 
−
|-
 
−
|ALT3
 
−
|PDM_BIT_STREAM2
 
−
(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_2 for mode ALT3)
 
−
|-
 
−
|ALT4
 
−
|CORESIGHT_TRACE2
 
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|GPIO4_IO04
+
|GPIO5_IO08
 
|-
 
|-
−
|ALT6
+
| rowspan="3" |J1.185
−
|SRC_BOOT_CFG2
+
| rowspan="3" |GPIO1_IO03
−
|-
+
| rowspan="3" |CPU.GPIO1_IO03
−
|J1.131
+
| rowspan="3" |P4
−
|DGND
+
| rowspan="3" |NVCC_3V3
−
|DGND
+
| rowspan="3" |I/O
−
| -
+
| rowspan="3" |
−
| -
+
|ALT0
−
|G
+
|GPIO1_IO03
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.133
+
|ALT1
−
|LVDS0_CLK_N
+
|USDHC1_VSELECT
−
|BRIDGE.A_CLKN
 
−
|F9
 
−
| -
 
−
|D
 
−
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.133
+
|ALT5
−
|DSI_CLK_N
+
|SDMA1_EXT_EVENT0
−
|CPU.MIPI_DSI_CLK_N
 
−
|A11
 
−
| -
 
−
|D
 
−
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.135
+
| rowspan="3" |J1.187
−
|LVDS0_CLK_P
+
| rowspan="3" |UART2_TXD
−
|BRIDGE.A_CLKP
+
| rowspan="3" |CPU.UART2_TXD
−
|F8
+
| rowspan="3" |D6
−
| -
+
| rowspan="3" |NVCC_3V3
−
|D
+
| rowspan="3" |I/O
−
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
+
| rowspan="3" |used as default Linux console
−
|
+
|ALT0
−
|
+
|UART2_TX
 
|-
 
|-
−
|J1.135
+
|ALT1
−
|DSI_CLK_P
+
|ECSPI3_SS0
−
|CPU.MIPI_
 
−
|B11
 
−
| -
 
−
|D
 
−
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.137
+
|ALT5
−
|LVDS0_TX0_N
+
|GPIO5_IO25
−
|BRIDGE.A_Y0N
 
−
|C9
 
−
| -
 
−
|D
 
−
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.137
+
| rowspan="3" |J1.189
−
|DSI_D0_N
+
| rowspan="3" |UART2_RXD
−
|CPU.MIPI_DSI_D0_N
+
| rowspan="3" |CPU.UART2_RXD
−
|A9
+
| rowspan="3" |B6
−
| -
+
| rowspan="3" |NVCC_3V3
−
|D
+
| rowspan="3" |I/O
−
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
+
| rowspan="3" |used as default Linux console
−
|
+
|ALT0
−
|
+
|UART2_RXD
 
|-
 
|-
−
|J1.139
+
|ALT1
−
|LVDS0_TX0_P
+
|ECSPI3_MISO
−
|BRIDGE.A_Y0P
 
−
|C8
 
−
| -
 
−
|D
 
−
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.139
+
|ALT5
−
|DSI_D0_P
+
|GPIO5_IO24
−
|CPU.MIPI_DSI_D0_P
 
−
|B9
 
−
| -
 
−
|D
 
−
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.141
+
| rowspan="3" |J1.191
−
|LVDS0_TX1_N
+
| rowspan="3" |UART1_TXD
−
|BRIDGE.A_Y1N
+
| rowspan="3" |CPU.UART1_TXD
−
|D9
+
| rowspan="3" |A7
−
| -
+
| rowspan="3" |NVCC_3V3
−
|D
+
| rowspan="3" |I/O
−
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
+
| rowspan="3" |
−
|
+
|ALT0
−
|
+
|UART1_TX
 
|-
 
|-
−
|J1.141
+
|ALT1
−
|DSI_D1_N
+
|ECSPI3_MOSI
−
|CPU.MIPI_DSI_D1_N
 
−
|A10
 
−
| -
 
−
|D
 
−
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.143
+
|ALT5
−
|LVDS0_TX1_P
+
|GPIO5_IO23
−
|BRIDGE.A_Y1P
 
−
|D8
 
−
| -
 
−
|D
 
−
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.143
+
| rowspan="3" |J1.193
−
|DSI_D1_P
+
| rowspan="3" |UART1_RXD
−
|CPU.MIPI_DSI_D1_P
+
| rowspan="3" |CPU.UART1_RXD
−
|B10
+
| rowspan="3" |C7
−
| -
+
| rowspan="3" |NVCC_3V3
−
|D
+
| rowspan="3" |I/O
−
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
+
| rowspan="3" |
−
|
+
|ALT0
−
|
+
|UART1_RXD
 
|-
 
|-
−
|J1.145
+
|ALT1
−
|LVDS0_TX2_N
+
|ECSPI3_SCLK
−
|BRIDGE.A_Y2N
 
−
|E9
 
−
| -
 
−
|D
 
−
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.145
+
|ALT5
−
|DSI_D2_N
+
|GPIO5_IO22
−
|CPU.MIPI_DSI_D2_N
 
−
|A12
 
−
| -
 
−
|D
 
−
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.147
+
| rowspan="3" |J1.195
−
|LVDS0_TX2_P
+
| rowspan="3" |ECSPI1_MOSI
−
|BRIDGE.A_Y2P
+
| rowspan="3" |CPU.ECSPI1_MOSI
−
|E8
+
| rowspan="3" |A4
−
| -
+
| rowspan="3" |NVCC_3V3
−
|D
+
| rowspan="3" |I/O
−
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
+
| rowspan="3" |
−
|
+
|ALT0
−
|
+
|ECSPI1_MOSI
 
|-
 
|-
−
|J1.147
+
|ALT1
−
|DSI_D2_P
+
|UART3_TX
−
|CPU.MIPI_DSI_D2_P
 
−
|B12
 
−
| -
 
−
|D
 
−
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.149
+
|ALT5
−
|LVDS0_TX3_N
+
|GPIO5_IO07
−
|BRIDGE.A_Y3N
 
−
|G9
 
−
| -
 
−
|D
 
−
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.149
+
| rowspan="4" |J1.197
−
|DSI_D3_N
+
| rowspan="4" |GPIO1_IO14
−
|CPU.MIPI_DSI_D3_N
+
| rowspan="4" |CPU.GPIO1_IO14
−
|A13
+
| rowspan="4" |K7
−
| -
+
| rowspan="4" |NVCC_3V3
−
|D
+
| rowspan="4" |I/O
−
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
+
| rowspan="4" |
−
|
+
|ALT0
−
|
+
|GPIO1_IO14
 
|-
 
|-
−
|J1.151
+
|ALT1
−
|LVDS0_TX3_P
+
|USB2_OTG_PWR
−
|BRIDGE.A_Y3P
 
−
|G8
 
−
| -
 
−
|D
 
−
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.151
+
|ALT5
−
|DSI_D3_P
+
|PWM3_OUT
−
|CPU.MIPI_DSI_D3_P
 
−
|B13
 
−
| -
 
−
|D
 
−
|Depending on [[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.153
+
|ALT6
−
|DGND
+
|CCM_CLKO1
−
|DGND
 
−
| -
 
−
| -
 
−
|G
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.155
+
| rowspan="3" |J1.199
−
|LVDS1_CLK_N
+
| rowspan="3" |GPIO1_IO04
−
|BRIDGE.B_CLKN
+
| rowspan="3" |CPU.GPIO1_IO04
−
|A6
+
| rowspan="3" |P5
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 +
|GPIO1_IO04
 +
|-
 +
|ALT1
 +
|USDHC2_VSELECT
 +
|-
 +
|ALT5
 +
|SDMA1_EXT_EVENT1
 +
|-
 +
| rowspan="3" |J1.201
 +
| rowspan="3" |GPIO1_IO12
 +
| rowspan="3" |CPU.GPIO1_IO12
 +
| rowspan="3" |L7
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 +
|GPIO1_IO12
 +
|-
 +
|ALT1
 +
|USB1_OTG_PWR
 +
|-
 +
|ALT5
 +
|SDMA2_EXT_EVENT1
 +
|-
 +
|J1.203
 +
|DGND
 +
|DGND
 +
| -
 
| -
 
| -
−
|D
+
|G
 
|
 
|
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.157
+
|}
−
|LVDS1_CLK_P
+
 
−
|BRIDGE.B_CLKP
+
==SODIMM J1 EVEN  pins declaration ==
−
|B6
+
 
 +
{| class="wikitable"
 +
! latexfontsize="scriptsize" | Pin
 +
! latexfontsize="scriptsize" | Pin Name
 +
! latexfontsize="scriptsize" | Internal Connections
 +
! latexfontsize="scriptsize" | Ball/pin #
 +
! latexfontsize="scriptsize" | Voltage domain
 +
! latexfontsize="scriptsize" | Type
 +
! latexfontsize="scriptsize" | Notes
 +
! colspan="2" latexfontsize="scriptsize" | Alternative Functions
 +
|-
 +
|J1.2
 +
|DGND
 +
|DGND
 
| -
 
| -
−
|D
+
|<nowiki>-</nowiki>
 +
|G
 
|
 
|
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.159
+
|J1.4
−
|LVDS1_TX0_N
+
|3.3VIN
−
|BRIDGE.B_Y0N
+
|INPUT VOLTAGE
−
|A3
 
 
| -
 
| -
−
|D
+
|3.3VIN
 +
|S
 
|
 
|
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.161
+
|J1.6
−
|LVDS1_TX0_P
+
|3.3VIN
−
|BRIDGE.B_Y0P
+
|INPUT VOLTAGE
−
|B3
 
 
| -
 
| -
−
|D
+
|3.3VIN
 +
|S
 
|
 
|
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.163
+
|J1.8
−
|LVDS1_TX1_N
+
|3.3VIN
−
|BRIDGE.B_Y1N
+
|INPUT VOLTAGE
−
|A4
 
 
| -
 
| -
−
|D
+
|3.3VIN
 +
|S
 
|
 
|
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.165
+
|J1.10
−
|LVDS1_TX1_P
+
|3.3VIN
−
|BRIDGE.B_Y1P
+
|INPUT VOLTAGE
−
|B4
 
 
| -
 
| -
−
|D
+
|3.3VIN
 +
|S
 
|
 
|
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.167
+
|J1.12
−
|LVDS1_TX2_N
+
|DGND
−
|BRIDGE.B_Y2N
+
|DGND
−
|A5
 
 
| -
 
| -
−
|D
+
|<nowiki>-</nowiki>
 +
|G
 
|
 
|
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.169
+
|J1.14
−
|LVDS1_TX2_P
+
|PMIC_LICELL
−
|BRIDGE.B_Y2P
+
|PMIC.LICELL
−
|B5
+
|30
 
| -
 
| -
−
|D
+
|S
 
|
 
|
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.171
+
|J1.16
−
|LVDS1_TX3_N
+
|CPU_ONOFF
−
|BRIDGE.B_Y3N
+
|CPU.ONOFF
−
|A7
+
|W21
−
| -
+
|NVCC_SNVS
−
|D
+
|I
−
|
+
|internal pull-up 100k to NVCC_SNVS
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.173
+
|J1.18
−
|LVDS1_TX3_P
+
|BOARD_PGOOD
−
|BRIDGE.B_Y3P
+
| -
−
|B7
 
 
| -
 
| -
−
|D
+
|NVCC_3V3
 +
|O
 
|
 
|
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.175
+
|J1.20
−
|DGND
+
|BOOT_MODE_SEL
−
|DGND
+
|BOOT MODE SELECTION
 +
| -
 +
|NVCC_3V3
 +
|I
 +
|internal pull-up to NVCC_3V3
 +
|
 +
|
 +
|-
 +
|J1.22
 +
|CPU_PORn
 +
|CPU.POR_B
 +
PMIC.RESETMCU
 +
|W20
 +
3
 +
|NVCC_SNVS
 +
|I/O
 +
|internal pull-up 100k to NVCC_SNVS
 +
|
 +
|
 +
|-
 +
|J1.24
 +
|EXT_RESET
 +
|MASTER RESET
 
| -
 
| -
 
| -
 
| -
−
|G
+
|I
−
|
+
|internal pull-up to NVCC_SNVS
 
|
 
|
 
|
 
|
 
|-
 
|-
−
| rowspan="2" |J1.177
+
| rowspan="4" |J1.26
−
| rowspan="2" |SD2_CD_B
+
| rowspan="4" |SAI3_RXC
−
| rowspan="2" |CPU.SD2_CD_B
+
| rowspan="4" |CPU.SAI3_RXC
−
| rowspan="2" |AA26
+
| rowspan="4" |F4
−
| rowspan="2" |NVCC_3V3
+
| rowspan="4" |NVCC_3V3
−
| rowspan="2" |I/O
+
| rowspan="4" |I/O
−
| rowspan="2" |
+
| rowspan="4" |
 
|ALT0
 
|ALT0
−
|USDHC2_CD_B
+
|SAI3_RX_BCLK
 
|-
 
|-
−
|ALT5
+
|ALT1
−
|GPIO2_IO12
+
|GPT1_CAPTURE2
 
|-
 
|-
−
| rowspan="3" |J1.179
+
|ALT2
−
| rowspan="3" |ECSPI1_SS0
+
|SAI5_RX_BCLK
−
| rowspan="3" |CPU.ECSPI1_SS0
 
−
| rowspan="3" |B6
 
−
| rowspan="3" |NVCC_3V3
 
−
| rowspan="3" |I/O
 
−
| rowspan="3" |
 
−
|ALT0
 
−
|ECSPI1_SS0
 
−
|-
 
−
|ALT1
 
−
|UART3_RTS_B
 
−
(Configure register IOMUXC_UART3_RTS_B_SELECT_INPUT for mode ALT1)
 
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|GPIO5_IO09
+
|GPIO4_IO29
 
|-
 
|-
−
| rowspan="3" |J1.181
+
| rowspan="4" |J1.28
−
| rowspan="3" |ECSPI1_SCLK
+
| rowspan="4" |GPIO1_IO02
−
| rowspan="3" |CPU.ECSPI1_SCLK
+
| rowspan="4" |CPU.GPIO1_IO02
−
| rowspan="3" |D6
+
| rowspan="4" |R4
−
| rowspan="3" |NVCC_3V3
+
| rowspan="4" |NVCC_3V3
−
| rowspan="3" |I/O
+
| rowspan="4" |I/O
−
| rowspan="3" |
+
| rowspan="4" |Internally used for SW reset, do not connect
 
|ALT0
 
|ALT0
−
|ECSPI1_SCLK
+
|GPIO1_IO02
 
|-
 
|-
 
|ALT1
 
|ALT1
−
|UART3_RX
+
|WDOG1_WDOG_B
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|GPIO5_IO06
+
|WDOG1_WDOG_ANY
 
|-
 
|-
−
| rowspan="3" |J1.183
+
|ALT7
−
| rowspan="3" |ECSPI1_MISO
+
|SJC_DE_B
−
| rowspan="3" |CPU.ECSPI1_MISO
+
|-
−
| rowspan="3" |A7
+
|J1.30
−
| rowspan="3" |NVCC_3V3
+
|DGND
−
| rowspan="3" |I/O
+
|DGND
−
| rowspan="3" |
+
| -
 +
|<nowiki>-</nowiki>
 +
|G
 +
|
 +
|
 +
|
 +
|-
 +
| rowspan="4" |J1.32
 +
| rowspan="4" |SAI3_RXD
 +
| rowspan="4" |CPU.SAI3_RXD
 +
| rowspan="4" |F3
 +
| rowspan="4" |NVCC_3V3
 +
| rowspan="4" |I/O
 +
| rowspan="4" |
 
|ALT0
 
|ALT0
−
|ECSPI1_MISO
+
|SAI3_RX_DATA0
 
|-
 
|-
 
|ALT1
 
|ALT1
−
|UART3_CTS_B
+
|GPT1_COMPARE1
 +
|-
 +
|ALT2
 +
|SAI5_RX_DATA0
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|GPIO5_IO08
+
|GPIO4_IO30
 
|-
 
|-
−
| rowspan="3" |J1.185
+
| rowspan="3" |J1.34
−
| rowspan="3" |GPIO1_IO03
+
| rowspan="3" |SAI2_MCLK
−
| rowspan="3" |CPU.GPIO1_IO03
+
| rowspan="3" |CPU.SAI2_MCLK
−
| rowspan="3" |AF13
+
| rowspan="3" |H5
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
−
| rowspan="3" |Internally used for PMIC interrupt, do not connect
+
| rowspan="3" |
−
 
 
−
Pulled-up to NVCC_3V3
 
 
|ALT0
 
|ALT0
−
|GPIO1_IO03
+
|SAI2_MCLK
 
|-
 
|-
 
|ALT1
 
|ALT1
−
|USDHC1_VSELECT
+
|SAI5_MCLK
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|SDMA1_EXT_EVENT0
+
|GPIO4_IO27
 
|-
 
|-
−
| rowspan="3" |J1.187
+
| rowspan="4" |J1.36
−
| rowspan="3" |UART2_TXD
+
| rowspan="4" |SAI3_RXFS
−
| rowspan="3" |CPU.UART2_TXD
+
| rowspan="4" |CPU.SAI3_RXFS
−
| rowspan="3" |E15
+
| rowspan="4" |G4
−
| rowspan="3" |NVCC_3V3
+
| rowspan="4" |NVCC_3V3
−
| rowspan="3" |I/O
+
| rowspan="4" |I/O
−
| rowspan="3" |used as default Linux console
+
| rowspan="4" |
 
|ALT0
 
|ALT0
−
|UART2_TX
+
|SAI3_RX_SYNC
 
|-
 
|-
 
|ALT1
 
|ALT1
−
|ECSPI3_SS0
+
|GPT1_CAPTURE1
 +
|-
 +
|ALT2
 +
|SAI5_RX_SYNC
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|GPIO5_IO25
+
|GPIO4_IO28
 
|-
 
|-
−
| rowspan="3" |J1.189
+
| rowspan="4" |J1.38
−
| rowspan="3" |UART2_RXD
+
| rowspan="4" |I2C3_SCL
−
| rowspan="3" |CPU.UART2_RXD
+
| rowspan="4" |CPU.I2C3_SCL
−
| rowspan="3" |F15
+
| rowspan="4" |G8
−
| rowspan="3" |NVCC_3V3
+
| rowspan="4" |NVCC_3V3
−
| rowspan="3" |I/O
+
| rowspan="4" |I/O
−
| rowspan="3" |used as default Linux console
+
| rowspan="4" |
 
|ALT0
 
|ALT0
−
|UART2_RXD
+
|I2C3_SCL
 
|-
 
|-
 
|ALT1
 
|ALT1
−
|ECSPI3_MISO
+
|PWM4_OUT
 
|-
 
|-
−
|ALT5
+
|ALT2
−
|GPIO5_IO24
+
|GPT2_CLK
−
|-
 
−
| rowspan="3" |J1.191
 
−
| rowspan="3" |UART4_TXD
 
−
| rowspan="3" |CPU.UART4_TXD
 
−
| rowspan="3" |F18
 
−
| rowspan="3" |NVCC_3V3
 
−
| rowspan="3" |I/O
 
−
| rowspan="3" |
 
−
|ALT0
 
−
|UART4_TX
 
−
|-
 
−
|ALT1
 
−
|UART2_RTS_B
 
−
(Configure register IOMUXC_UART2_RTS_B_SELECT_INPUT for mode ALT1)
 
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|GPIO5_IO29
+
|GPIO5_IO18
 
|-
 
|-
−
| rowspan="4" |J1.193
+
| rowspan="4" |J1.40
−
| rowspan="4" |UART4_RXD
+
| rowspan="4" |SAI3_TXFS
−
| rowspan="4" |CPU.UART4_RXD
+
| rowspan="4" |CPU.SAI3_TXFS
−
| rowspan="4" |F19
+
| rowspan="4" |G3
 
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |NVCC_3V3
 
| rowspan="4" |I/O
 
| rowspan="4" |I/O
 
| rowspan="4" |
 
| rowspan="4" |
 
|ALT0
 
|ALT0
−
|UART4_RX
+
|SAI3_TX_SYNC
 
|-
 
|-
 
|ALT1
 
|ALT1
−
|UART2_CTS_B
+
|GPT1_CLK
 
|-
 
|-
 
|ALT2
 
|ALT2
−
|PCIE1_CLKREQ_B
+
|SAI5_RX_DATA1
−
(Configure register IOMUXC_PCIE1_CLKREQ_B_SELECT_INPUT for mode ALT2)
 
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|GPIO5_IO28
+
|GPIO4_IO31
 
|-
 
|-
−
| rowspan="3" |J1.195
+
| rowspan="3" |J1.42
−
| rowspan="3" |ECSPI1_MOSI
+
| rowspan="3" |SPDIF_RX
−
| rowspan="3" |CPU.ECSPI1_MOSI
+
| rowspan="3" |CPU.SPDIF_RX
−
| rowspan="3" |B7
+
| rowspan="3" |G6
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
 
| rowspan="3" |
 
| rowspan="3" |
 
|ALT0
 
|ALT0
−
|ECSPI1_MOSI
+
|SPDIF1_IN
 
|-
 
|-
 
|ALT1
 
|ALT1
−
|UART3_TX
+
|PWM2_OUT
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|GPIO5_IO07
+
|GPIO5_IO04
 
|-
 
|-
−
| rowspan="5" |J1.197
+
| rowspan="3" |J1.44
−
| rowspan="5" |GPIO1_IO14
+
| rowspan="3" |SPDIF_TX
−
| rowspan="5" |CPU.GPIO1_IO14
+
| rowspan="3" |CPU.SPDIF_TX
−
| rowspan="5" |AC9
+
| rowspan="3" |F6
−
| rowspan="5" |NVCC_3V3
+
| rowspan="3" |NVCC_3V3
−
| rowspan="5" |I/O
+
| rowspan="3" |I/O
−
| rowspan="5" |
+
| rowspan="3" |
 
|ALT0
 
|ALT0
−
|GPIO1_IO14
+
|SPDIF1_OUT
 
|-
 
|-
 
|ALT1
 
|ALT1
−
|USB2_OTG_PWR
+
|PWM3_OUT
−
|-
 
−
|ALT4
 
−
|USDHC3_CD_B
 
−
(Configure register IOMUXC_USDHC3_CD_B_SELECT_INPUT for mode ALT4)
 
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|PWM3_OUT
+
|GPIO5_IO03
 
|-
 
|-
−
|ALT6
+
| rowspan="4" |J1.46
−
|CCM_CLKO1
+
| rowspan="4" |SAI3_MCLK
−
|-
+
| rowspan="4" |CPU.SAI3_MCLK
−
| rowspan="3" |J1.199
+
| rowspan="4" |D3
−
| rowspan="3" |GPIO1_IO04
+
| rowspan="4" |NVCC_3V3
−
| rowspan="3" |CPU.GPIO1_IO04
+
| rowspan="4" |I/O
−
| rowspan="3" |AG12
+
| rowspan="4" |
−
| rowspan="3" |NVCC_3V3
 
−
| rowspan="3" |I/O
 
−
| rowspan="3" |
 
 
|ALT0
 
|ALT0
−
|GPIO1_IO04
+
|SAI3_MCLK
 
|-
 
|-
 
|ALT1
 
|ALT1
−
|USDHC2_VSELECT
+
|PWM4_OUT
 +
|-
 +
|ALT2
 +
|SAI5_MCLK
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|SDMA1_EXT_EVENT1
+
|GPIO5_IO02
 
|-
 
|-
−
| rowspan="3" |J1.201
+
| rowspan="4" |J1.48
−
| rowspan="3" |GPIO1_IO12
+
| rowspan="4" |I2C3_SDA
−
| rowspan="3" |CPU.GPIO1_IO12
+
| rowspan="4" |CPU.I2C3_SDA
−
| rowspan="3" |AB10
+
| rowspan="4" |E9
−
| rowspan="3" |NVCC_3V3
+
| rowspan="4" |NVCC_3V3
−
| rowspan="3" |I/O
+
| rowspan="4" |I/O
−
| rowspan="3" |
+
| rowspan="4" |
 
|ALT0
 
|ALT0
−
|GPIO1_IO12
+
|I2C3_SDA
 
|-
 
|-
 
|ALT1
 
|ALT1
−
|USB1_OTG_PWR
+
|PWM3_OUT
 +
|-
 +
|ALT2
 +
|GPT3_CLK
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|SDMA2_EXT_EVENT1
+
|GPIO5_IO19
 
|-
 
|-
−
|J1.203
+
| rowspan="4" |J1.50
−
|DGND
+
| rowspan="4" |SAI3_TXC
−
|DGND
+
| rowspan="4" |CPU.SAI3_TXC
−
| -
+
| rowspan="4" |C4
−
| -
+
| rowspan="4" |NVCC_3V3
−
|G
+
| rowspan="4" |I/O
−
|
+
| rowspan="4" |
−
|
+
|ALT0
−
|
+
|SAI3_TX_BCLK
 
|-
 
|-
−
|}
+
|ALT1
−
 
+
|GPT1_COMPARE2
−
==SODIMM J1 EVEN  pins declaration ==
 
−
 
 
−
{| class="wikitable"
 
−
! latexfontsize="scriptsize" | Pin
 
−
! latexfontsize="scriptsize" | Pin Name
 
−
! latexfontsize="scriptsize" | Internal Connections
 
−
! latexfontsize="scriptsize" | Ball/pin #
 
−
! latexfontsize="scriptsize" | Voltage domain
 
−
! latexfontsize="scriptsize" | Type
 
−
! latexfontsize="scriptsize" | Notes
 
−
! colspan="2" latexfontsize="scriptsize" | Alternative Functions
 
 
|-
 
|-
−
|J1.2
+
|ALT2
 +
|SAI5_RX_DATA2
 +
|-
 +
|ALT5
 +
|GPIO5_IO00
 +
|-
 +
| rowspan="4" |J1.52
 +
| rowspan="4" |SAI3_TXD
 +
| rowspan="4" |CPU.SAI3_TXD
 +
| rowspan="4" |C3
 +
| rowspan="4" |NVCC_3V3
 +
| rowspan="4" |I/O
 +
| rowspan="4" |
 +
|ALT0
 +
|SAI3_TX_DATA0
 +
|-
 +
|ALT1
 +
|GPT1_COMPARE3
 +
|-
 +
|ALT2
 +
|SAI5_RX_DATA3
 +
|-
 +
|ALT5
 +
|GPIO5_IO01
 +
|-
 +
| rowspan="2" |J1.54
 +
| rowspan="2" |GPIO1_IO10
 +
| rowspan="2" |CPU.GPIO1_IO10
 +
| rowspan="2" |M7
 +
| rowspan="2" |NVCC_3V3
 +
| rowspan="2" |I/O
 +
| rowspan="2" |Internally used for ETH PHY interrupt, do not connect
 +
|ALT0
 +
|GPIO1_IO10
 +
|-
 +
|ALT1
 +
|USB1_OTG_ID
 +
|-
 +
|J1.56
 
|DGND
 
|DGND
 
|DGND
 
|DGND
Line 1,754: Line 1,768:
 
|
 
|
 
|-
 
|-
−
|J1.4
+
| rowspan="4" |J1.58
−
|3.3VIN
+
| rowspan="4" |SAI5_MCLK
−
|INPUT VOLTAGE
+
| rowspan="4" |CPU.SAI5_MCLK
−
| -
+
| rowspan="4" |K4
−
|3.3VIN
+
| rowspan="4" |NVCC_3V3
−
|S
+
| rowspan="4" |I/O
−
|
+
| rowspan="4" |
−
|
+
|ALT0
−
|
+
|SAI5_MCLK
 
|-
 
|-
−
|J1.6
+
|ALT1
−
|3.3VIN
+
|SAI1_TX_BCLK
−
|INPUT VOLTAGE
 
−
| -
 
−
|3.3VIN
 
−
|S
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.8
+
|ALT2
−
|3.3VIN
+
|SAI4_MCLK
−
|INPUT VOLTAGE
 
−
| -
 
−
|3.3VIN
 
−
|S
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.10
+
|ALT5
−
|3.3VIN
+
|GPIO3_IO25
−
|INPUT VOLTAGE
 
−
| -
 
−
|3.3VIN
 
−
|S
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.12
+
| rowspan="4" |J1.60
−
|DGND
+
| rowspan="4" |GPIO1_IO15
−
|DGND
+
| rowspan="4" |CPU.GPIO1_IO15
−
| -
+
| rowspan="4" |J6
−
|<nowiki>-</nowiki>
+
| rowspan="4" |NVCC_3V3
−
|G
+
| rowspan="4" |I/O
−
|
+
| rowspan="4" |
−
|
+
|ALT0
−
|
+
|GPIO1_IO15
 
|-
 
|-
−
|J1.14
+
|ALT1
−
|PMIC_LICELL
+
|USB2_OTG_OC
−
|PMIC.LICELL
 
−
|46
 
−
| -
 
−
|S
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.16
+
|ALT5
−
|CPU_ONOFF
+
|PWM4_OUT
−
|CPU.ONOFF
 
−
|A25
 
−
|NVCC_SNVS_1V8
 
−
|I
 
−
|internal pull-up 100k to NVCC_SNVS_1V8
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.18
+
|ALT6
−
|BOARD_PGOOD
+
|CCM_CLKO2
−
| -
 
−
| -
 
−
|NVCC_3V3
 
−
|O
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.20
+
| rowspan="3" |J1.62
−
|BOOT_MODE_SEL
+
| rowspan="3" |SAI5_RXFS
−
|BOOT MODE SELECTION
+
| rowspan="3" |CPU.SAI5_RXFS
−
| -
+
| rowspan="3" |N4
−
|NVCC_3V3
+
| rowspan="3" |NVCC_3V3
−
|I
+
| rowspan="3" |I/O
−
|internal pull-up to NVCC_3V3
+
| rowspan="3" |
−
|
+
|ALT0
−
|
+
|SAI5_RX_SYNC
 
|-
 
|-
−
|J1.22
+
|ALT1
−
|CPU_PORn
+
|SAI1_TX_DATA0
−
|CPU.POR_B
 
−
PMIC.RESET_MCU
 
−
|B24
 
−
21
 
−
|NVCC_SNVS_1V8
 
−
|I/O
 
−
|internal pull-up 100k to NVCC_SNVS_1V8
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.24
+
|ALT5
−
|PMIC_PWRON
+
|GPIO3_IO19
−
|PMIC.PWRON
 
−
| 22
 
−
| '''(*)''' 3.3VIN
 
−
|I
 
−
|internal pull-up 100k to VIN
 
−
'''(*)''' default as ''Embedded'' power mode
 
−
|
 
−
|
 
 
|-
 
|-
−
| rowspan="5" |J1.26
+
| rowspan="3" |J1.64
−
| rowspan="5" |SAI3_RXC
+
| rowspan="3" |SAI5_RXC
−
| rowspan="5" |CPU.SAI3_RXC
+
| rowspan="3" |CPU.SAI5_RXC
−
| rowspan="5" |AG7
+
| rowspan="3" |L5
−
| rowspan="5" |NVCC_3V3
+
| rowspan="3" |NVCC_3V3
−
| rowspan="5" |I/O
+
| rowspan="3" |I/O
−
| rowspan="5" |
+
| rowspan="3" |
 
|ALT0
 
|ALT0
−
|SAI3_RX_BCLK
+
|SAI5_RX_BCLK
 
|-
 
|-
 
|ALT1
 
|ALT1
−
|GPT1_CLK
+
|SAI1_TX_DATA1
−
|-
 
−
|ALT2
 
−
|SAI5_RX_BCLK
 
−
(Configure register IOMUXC_SAI5_RX_BCLK_SELECT_INPUT for mode ALT2)
 
−
|-
 
−
|ALT4
 
−
|UART2_CTS_B
 
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|GPIO4_IO29
+
|GPIO3_IO20
 
|-
 
|-
−
| rowspan="4" |J1.28
+
| rowspan="3" |J1.66
−
| rowspan="4" |GPIO1_IO02
+
| rowspan="3" |SAI2_TXC
−
| rowspan="4" |CPU.GPIO1_IO02
+
| rowspan="3" |CPU.SAI2_TXC
−
| rowspan="4" |AG13
+
| rowspan="3" |J5
−
| rowspan="4" |NVCC_3V3
+
| rowspan="3" |NVCC_3V3
−
| rowspan="4" |I/O
+
| rowspan="3" |I/O
−
| rowspan="4" |Internally used for PMIC WDI, do not connect
+
| rowspan="3" |
 
|ALT0
 
|ALT0
−
|GPIO1_IO02
+
|SAI2_TX_BCLK
 
|-
 
|-
 
|ALT1
 
|ALT1
−
|WDOG1_WDOG_B
+
|SAI5_TX_DATA2
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|WDOG1_WDOG_ANY
+
|GPIO4_IO25
 +
|-
 +
| rowspan="3" |J1.68
 +
| rowspan="3" |SAI2_TXD0
 +
| rowspan="3" |CPU.SAI2_TXD0
 +
| rowspan="3" |G5
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 +
|SAI2_TX_DATA0
 
|-
 
|-
−
|ALT7
+
|ALT1
−
|SJC_DE_B
+
|SAI5_TX_DATA3
 
|-
 
|-
−
|J1.30
+
|ALT5
−
|DGND
+
|GPIO4_IO26
−
|DGND
 
−
| -
 
−
|<nowiki>-</nowiki>
 
−
|G
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
| rowspan="5" |J1.32
+
| rowspan="3" |J1.70
−
| rowspan="5" |SAI3_RXD
+
| rowspan="3" |SAI2_TXFS
−
| rowspan="5" |CPU.SAI3_RXD
+
| rowspan="3" |CPU.SAI2_TXFS
−
| rowspan="5" |AF7
+
| rowspan="3" |H4
−
| rowspan="5" |NVCC_3V3
+
| rowspan="3" |NVCC_3V3
−
| rowspan="5" |I/O
+
| rowspan="3" |I/O
−
| rowspan="5" |
+
| rowspan="3" |
 
|ALT0
 
|ALT0
−
|SAI3_RX_DATA0
+
|SAI2_TX_SYNC
 
|-
 
|-
 
|ALT1
 
|ALT1
−
|GPT1_COMPARE1
+
|SAI5_TX_DATA1
−
|-
 
−
|ALT2
 
−
|SAI5_RX_DATA0
 
−
(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_0 for mode ALT2)
 
−
|-
 
−
|ALT4
 
−
|UART2_RTS_B
 
−
(Configure register IOMUXC_UART2_RTS_B_SELECT_INPUT for mode ALT4)
 
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|GPIO4_IO30
+
|GPIO4_IO24
 
|-
 
|-
−
| rowspan="3" |J1.34
+
| rowspan="3" |J1.72
−
| rowspan="3" |SAI2_MCLK
+
| rowspan="3" |SAI2_RXD0
−
| rowspan="3" |CPU.SAI2_MCLK
+
| rowspan="3" |CPU.SAI2_RXD0
−
| rowspan="3" |AD19
+
| rowspan="3" |H6
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
 
| rowspan="3" |
 
| rowspan="3" |
 
|ALT0
 
|ALT0
−
|SAI2_MCLK
+
|SAI2_RX_DATA0
 
|-
 
|-
 
|ALT1
 
|ALT1
−
|SAI5_MCLK
+
|SAI5_TX_DATA0
−
(Configure register IOMUXC_SAI5_MCLK_SELECT_INPUT for mode ALT1)
 
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|GPIO4_IO27
+
|GPIO4_IO23
 
|-
 
|-
−
| rowspan="5" |J1.36
+
| rowspan="3" |J1.74
−
| rowspan="5" |SAI3_RXFS
+
| rowspan="3" |SAI5_RXD0
−
| rowspan="5" |CPU.SAI3_RXFS
+
| rowspan="3" |CPU.SAI5_RXD0
−
| rowspan="5" |AG8
+
| rowspan="3" |M5
−
| rowspan="5" |NVCC_3V3
+
| rowspan="3" |NVCC_3V3
−
| rowspan="5" |I/O
+
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 +
|SAI5_RX_DATA0
 +
|-
 +
|ALT1
 +
|SAI1_TX_DATA2
 +
|-
 +
|ALT5
 +
|GPIO3_IO21
 +
|-
 +
| rowspan="5" |J1.76
 +
| rowspan="5" |SAI5_RXD1
 +
| rowspan="5" |CPU.SAI5_RXD1
 +
| rowspan="5" |L4
 +
| rowspan="5" |NVCC_3V3
 +
| rowspan="5" |I/O
 
| rowspan="5" |
 
| rowspan="5" |
 
|ALT0
 
|ALT0
−
|SAI3_RX_SYNC
+
|SAI5_RX_DATA1
 
|-
 
|-
 
|ALT1
 
|ALT1
−
|GPT1_CAPTURE1
+
|SAI1_TX_DATA3
 
|-
 
|-
 
|ALT2
 
|ALT2
−
|SAI5_RX_SYNC
+
|SAI1_TX_SYNC
−
(Configure register IOMUXC_SAI5_RX_SYNC_SELECT_INPUT for mode ALT2)
 
 
|-
 
|-
 
|ALT3
 
|ALT3
−
|SAI3_RX_DATA1
+
|SAI5_TX_SYNC
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|GPIO4_IO28
+
|GPIO3_IO212
 
|-
 
|-
−
| rowspan="4" |J1.38
+
| rowspan="5" |J1.78
−
| rowspan="4" |I2C3_SCL
+
| rowspan="5" |SAI5_RXD2
−
| rowspan="4" |CPU.I2C3_SCL
+
| rowspan="5" |CPU.SAI5_RXD2
−
| rowspan="4" |E10
+
| rowspan="5" |M4
−
| rowspan="4" |NVCC_3V3
+
| rowspan="5" |NVCC_3V3
−
| rowspan="4" |I/O
+
| rowspan="5" |I/O
−
| rowspan="4" |
+
| rowspan="5" |
 
|ALT0
 
|ALT0
−
|I2C3_SCL
+
|SAI5_RX_DATA2
 
|-
 
|-
 
|ALT1
 
|ALT1
−
|PWM4_OUT
+
|SAI1_TX_DATA4
 
|-
 
|-
 
|ALT2
 
|ALT2
−
|GPT2_CLK
+
|SAI1_TX_SYNC
 +
|-
 +
|ALT3
 +
|SAI5_TX_BCLK
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|GPIO5_IO18
+
|GPIO3_IO23
 
|-
 
|-
−
| rowspan="6" |J1.40
+
| rowspan="5" |J1.80
−
| rowspan="6" |SAI3_TXFS
+
| rowspan="5" |SAI5_RXD3
−
| rowspan="6" |CPU.SAI3_TXFS
+
| rowspan="5" |CPU.SAI5_RXD3
−
| rowspan="6" |AC6
+
| rowspan="5" |K5
−
| rowspan="6" |NVCC_3V3
+
| rowspan="5" |NVCC_3V3
−
| rowspan="6" |I/O
+
| rowspan="5" |I/O
−
| rowspan="6" |
+
| rowspan="5" |
 
|ALT0
 
|ALT0
−
|SAI3_TX_SYNC
+
|SAI5_RX_DATA3
 
|-
 
|-
 
|ALT1
 
|ALT1
−
|GPT1_CAPTURE2
+
|SAI1_TX_DATA5
 
|-
 
|-
 
|ALT2
 
|ALT2
−
|SAI5_RX_DATA1
+
|SAI1_TX_SYNC
−
(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_1 for mode ALT2)
 
 
|-
 
|-
 
|ALT3
 
|ALT3
−
|SAI3_TX_DATA1
+
|SAI5_TX_DATA0
−
|-
 
−
|ALT4
 
−
|UART2_RX
 
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|GPIO4_IO31
+
|GPIO3_IO24
 
|-
 
|-
−
| rowspan="3" |J1.42
+
|J1.82
−
| rowspan="3" |SPDIF_RX
+
|DGND
−
| rowspan="3" |CPU.SPDIF_RX
+
|DGND
−
| rowspan="3" |AG9
+
| -
−
| rowspan="3" |NVCC_3V3
+
|<nowiki>-</nowiki>
−
| rowspan="3" |I/O
+
|G
−
| rowspan="3" |
+
|
−
|ALT0
+
|
−
|SPDIF1_IN
+
|
 
|-
 
|-
−
|ALT1
+
|J1.84
−
|PWM2_OUT
+
|CLK2_N
 +
|CPU.CLK2_N
 +
|T22
 +
|VDDA_1V8
 +
|D
 +
|Internally used for PCIe CLK, do not connect
 +
|
 +
|
 
|-
 
|-
−
|ALT5
+
|J1.86
−
|GPIO5_IO04
+
|CLK2_P
 +
|CPU.CLK2_P
 +
|U22
 +
|VDDA_1V8
 +
|D
 +
|Internally used for PCIe CLK, do not connect
 +
|
 +
|
 
|-
 
|-
−
| rowspan="3" |J1.44
+
|J1.88
−
| rowspan="3" |SPDIF_TX
+
|PCIE1_REF_CLKN
−
| rowspan="3" |CPU.SPDIF_TX
+
|CPU.PCIE1_REF_PAD_CLK_N
−
| rowspan="3" |AF9
+
|K24
−
| rowspan="3" |NVCC_3V3
+
|VDD_PHY_3V3
−
| rowspan="3" |I/O
+
|D
−
| rowspan="3" |
+
|
−
|ALT0
+
|
−
|SPDIF1_OUT
+
|
 
|-
 
|-
−
|ALT1
+
|J1.90
−
|PWM3_OUT
+
|PCIE1_REF_CLKP
 +
|CPU.PCIE1_REF_PAD_CLK_P
 +
|K25
 +
|VDD_PHY_3V3
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
|ALT5
+
|J1.92
−
|GPIO5_IO03
+
|PCIE1_RXN
 +
|CPU.PCIE1_RXN_N
 +
|H24
 +
|VDD_PHY_3V3
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
| rowspan="4" |J1.46
+
|J1.94
−
| rowspan="4" |SAI3_MCLK
+
|PCIE1_RXP
−
| rowspan="4" |CPU.SAI3_MCLK
+
|CPU.PCIE1_RXN_P
−
| rowspan="4" |AD6
+
|H25
−
| rowspan="4" |NVCC_3V3
+
|VDD_PHY_3V3
−
| rowspan="4" |I/O
+
|D
−
| rowspan="4" |
+
|
−
|ALT0
+
|
−
|SAI3_MCLK
+
|
 
|-
 
|-
−
|ALT1
+
|J1.96
−
|PWM4_OUT
+
|PCIE1_TXN
 +
|CPU.PCIE1_TXN_N
 +
|J24
 +
|VDD_PHY_3V3
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
|ALT2
+
|J1.98
−
|SAI5_MCLK
+
|PCIE1_TXP
−
(Configure register IOMUXC_SAI5_MCLK_SELECT_INPUT for mode ALT2)
+
|CPU.PCIE1_TXN_P
 +
|J25
 +
|VDD_PHY_3V3
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
|ALT5
+
|J1.100
−
|GPIO5_IO02
+
|DGND
 +
|DGND
 +
| -
 +
|<nowiki>-</nowiki>
 +
|G
 +
|
 +
|
 +
|
 
|-
 
|-
−
| rowspan="4" |J1.48
+
|J1.102
−
| rowspan="4" |I2C3_SDA
+
|CSI1_CLK_N
−
| rowspan="4" |CPU.I2C3_SDA
+
|CPU.MIPI_CSI1_CLK_N
−
| rowspan="4" |F10
+
|A22
−
| rowspan="4" |NVCC_3V3
+
| -
−
| rowspan="4" |I/O
+
|D
−
| rowspan="4" |
+
|
−
|ALT0
+
|
−
|I2C3_SDA
+
|
 
|-
 
|-
−
|ALT1
+
|J1.104
−
|PWM3_OUT
+
|CSI1_CLK_P
−
|-
+
|CPU.MIPI_CSI1_CLK_P
−
|ALT2
+
|B22
−
|GPT3_CLK
+
| -
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
|ALT5
+
|J1.106
−
|GPIO5_IO19
+
|CSI1_D0_N
 +
|CPU.MIPI_CSI1_D0_N
 +
|A23
 +
| -
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
| rowspan="5" |J1.50
+
|J1.108
−
| rowspan="5" |SAI3_TXC
+
|CSI1_D0_P
−
| rowspan="5" |CPU.SAI3_TXC
+
|CPU.MIPI_CSI1_D0_P
−
| rowspan="5" |AG6
+
|B23
−
| rowspan="5" |NVCC_3V3
+
| -
−
| rowspan="5" |I/O
+
|D
−
| rowspan="5" |
+
|
−
|ALT0
+
|
−
|SAI3_TX_BCLK
+
|
 
|-
 
|-
−
|ALT1
+
|J1.110
−
|GPT1_COMPARE2
+
|CSI1_D1_N
 +
|CPU.MIPI_CSI1_D1_N
 +
|C22
 +
| -
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
|ALT2
+
|J1.112
−
|SAI5_RX_DATA2
+
|CSI1_D1_P
−
(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_2 for mode ALT2)
+
|CPU.MIPI_CSI1_D1_P
 +
|D22
 +
| -
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
|ALT4
+
|J1.114
−
|UART2_TX
+
|CSI1_D2_N
 +
|CPU.MIPI_CSI1_D2_N
 +
|B24
 +
| -
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
|ALT5
+
|J1.116
−
|GPIO5_IO00
+
|CSI1_D2_P
 +
|CPU.MIPI_CSI1_D2_P
 +
|C23
 +
| -
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
| rowspan="4" |J1.52
+
|J1.118
−
| rowspan="4" |SAI3_TXD
+
|CSI1_D3_N
−
| rowspan="4" |CPU.SAI3_TXD
+
|CPU.MIPI_CSI1_D3_N
−
| rowspan="4" |AF6
+
|C21
−
| rowspan="4" |NVCC_3V3
+
| -
−
| rowspan="4" |I/O
+
|D
−
| rowspan="4" |
+
|
−
|ALT0
+
|
−
|SAI3_TX_DATA0
+
|
 
|-
 
|-
−
|ALT1
+
|J1.120
−
|GPT1_COMPARE3
+
|CSI1_D3_P
 +
|CPU.MIPI_CSI1_D3_P
 +
|D21
 +
| -
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
|ALT2
+
|J1.122
−
|SAI5_RX_DATA3
 
−
(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_3 for mode ALT2)
 
−
|-
 
−
|ALT5
 
−
|GPIO5_IO01
 
−
|-
 
−
| rowspan="5" |J1.54
 
−
| rowspan="5" |SAI1_MCLK
 
−
| rowspan="5" |CPU.SAI1_MCLK
 
−
| rowspan="5" |AB18
 
−
| rowspan="5" |NVCC_3V3
 
−
| rowspan="5" |I/O
 
−
| rowspan="5" |
 
−
|ALT0
 
−
|SAI1_MCLK
 
−
|-
 
−
|ALT1
 
−
|SAI5_MCLK
 
−
(Configure register IOMUXC_SAI5_MCLK_SELECT_INPUT for mode ALT1)
 
−
|-
 
−
|ALT2
 
−
|SAI1_TX_BCLK
 
−
(Configure register IOMUXC_SAI1_TX_BCLK_SELECT_INPUT for mode ALT2)
 
−
|-
 
−
|ALT3
 
−
|PDM_CLK
 
−
|-
 
−
|ALT5
 
−
|GPIO4_IO20
 
−
|-
 
−
|J1.56
 
 
|DGND
 
|DGND
 
|DGND
 
|DGND
Line 2,176: Line 2,194:
 
|
 
|
 
|-
 
|-
−
| rowspan="3" |J1.58
+
|J1.124
−
| rowspan="3" |SAI5_MCLK
+
(NAND on board)
−
| rowspan="3" |CPU.SAI5_MCLK
+
|NAND_DQS
−
| rowspan="3" |AD15
+
|CPU.NAND_DQS
 +
|M20
 +
|NVCC_3V3
 +
|I/O
 +
|Internally used for NAND, do not connect
 +
|
 +
|
 +
|-
 +
| rowspan="3" |J1.124
 +
(eMMC on board)
 +
| rowspan="3" |NAND_DQS
 +
| rowspan="3" |CPU.NAND_DQS
 +
| rowspan="3" |M20
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
 
| rowspan="3" |
 
| rowspan="3" |
 
|ALT0
 
|ALT0
−
|SAI5_MCLK
+
|RAWNAND_DQS
−
(Configure register IOMUXC_SAI5_MCLK_SELECT_INPUT for mode ALT0)
 
 
|-
 
|-
 
|ALT1
 
|ALT1
−
|SAI1_TX_BCLK
+
|QSPI_A_DQS
−
(Configure register IOMUXC_SAI1_TX_BCLK_SELECT_INPUT for mode ALT1)
 
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|GPIO3_IO25
+
|GPIO3_IO14
 
|-
 
|-
−
| rowspan="2" |J1.60
+
|J1.126
−
| rowspan="2" |GPIO1_IO10
+
(NAND on board)
−
| rowspan="2" |CPU.GPIO1_IO10
+
|NAND_ALE
−
| rowspan="2" |AD10
+
|CPU.NAND_ALE
−
| rowspan="2" |NVCC_3V3
+
|G19
−
| rowspan="2" |I/O
+
|NVCC_3V3
−
| rowspan="2" |Internally used for ETH PHY interrupt, do not connect
+
|I/O
−
|ALT0
+
|Internally used for NAND, do not connect
−
|GPIO1_IO10
+
|
 +
|
 
|-
 
|-
−
|ALT1
+
| rowspan="3" |J1.126
−
|USB1_OTG_ID
+
(eMMC on board)
−
|-
+
| rowspan="3" |NAND_ALE
−
| rowspan="3" |J1.62
+
| rowspan="3" |CPU.NAND_ALE
−
| rowspan="3" |SAI5_RXFS
+
| rowspan="3" |G19
−
| rowspan="3" |CPU.SAI5_RXFS
 
−
| rowspan="3" |AB15
 
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
 
| rowspan="3" |
 
| rowspan="3" |
 
|ALT0
 
|ALT0
−
|SAI5_RX_SYNC
+
|RAWNAND_ALE
−
(Configure register IOMUXC_SAI5_RX_SYNC_SELECT_INPUT for mode ALT0)
 
 
|-
 
|-
 
|ALT1
 
|ALT1
−
|SAI1_TX_DATA0
+
|QSPI_A_SCLK
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|GPIO3_IO19
+
|GPIO3_IO00
 
|-
 
|-
−
| rowspan="4" |J1.64
+
| rowspan="2" |J1.128
−
| rowspan="4" |SAI5_RXC
+
(NAND on board)
−
| rowspan="4" |CPU.SAI5_RXC
+
| rowspan="2" |SD1_CLK
−
| rowspan="4" |AC15
+
| rowspan="2" |CPU.SD1_CLK
−
| rowspan="4" |NVCC_3V3
+
| rowspan="2" |L25
−
| rowspan="4" |I/O
+
| rowspan="2" |NVCC_3V3
−
| rowspan="4" |
+
(NVCC_1V8 on request)
 +
| rowspan="2" |I/O
 +
| rowspan="2" |
 
|ALT0
 
|ALT0
−
|SAI5_RX_BCLK
+
|USDHC1_CLK
−
(Configure register IOMUXC_SAI5_RX_BCLK_SELECT_INPUT for mode ALT0)
 
 
|-
 
|-
−
|ALT1
+
|ALT5
−
|SAI1_TX_DATA1
+
|GPIO2_IO00
 
|-
 
|-
−
|ALT4
+
| rowspan="3" |J1.128
−
|PDM_CLK
+
(eMMC on board)
−
|-
+
| rowspan="3" |NAND_CE0_B
−
|ALT5
+
| rowspan="3" |CPU.NAND_CE0_B
−
|GPIO3_IO20
+
| rowspan="3" |H19
−
|-
 
−
| rowspan="3" |J1.66
 
−
| rowspan="3" |SAI2_TXC
 
−
| rowspan="3" |CPU.SAI2_TXC
 
−
| rowspan="3" |AD22
 
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
 
| rowspan="3" |
 
| rowspan="3" |
 
|ALT0
 
|ALT0
−
|SAI2_TX_BCLK
+
|RAWNAND_CE0_B
 
|-
 
|-
 
|ALT1
 
|ALT1
−
|SAI5_TX_DATA2
+
|QSPI_A_SS0_B
 +
|-
 +
|ALT5
 +
|GPIO3_IO01
 +
|-
 +
| rowspan="2" |J1.130
 +
(NAND on board)
 +
| rowspan="2" |SD1_CMD
 +
| rowspan="2" |CPU.SD1_CMD
 +
| rowspan="2" |L24
 +
| rowspan="2" |NVCC_3V3
 +
(NVCC_1V8 on request)
 +
| rowspan="2" |I/O
 +
| rowspan="2" |
 +
|ALT0
 +
|USDHC1_CMD
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|GPIO4_IO25
+
|GPIO2_IO01
 
|-
 
|-
−
| rowspan="3" |J1.68
+
| rowspan="3" |J1.130
−
| rowspan="3" |SAI2_TXD0
+
(eMMC on board)
−
| rowspan="3" |CPU.SAI2_TXD0
+
| rowspan="3" |NAND_CE1_B
−
| rowspan="3" |AC22
+
| rowspan="3" |CPU.NAND_CE1_B
 +
| rowspan="3" |G21
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
 
| rowspan="3" |
 
| rowspan="3" |
 
|ALT0
 
|ALT0
−
|SAI2_TX_DATA0
+
|RAWNAND_CE1_B
 
|-
 
|-
 
|ALT1
 
|ALT1
−
|SAI5_TX_DATA3
+
|QSPI_A_SS1_B
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|GPIO4_IO26
+
|GPIO3_IO02
 
|-
 
|-
−
| rowspan="5" |J1.70
+
| rowspan="2" |J1.132
−
| rowspan="5" |SAI2_TXFS
+
(NAND on board)
−
| rowspan="5" |CPU.SAI2_TXFS
+
| rowspan="2" |SD1_RST_B
−
| rowspan="5" |AD23
+
| rowspan="2" |CPU.SD1_RST_B
−
| rowspan="5" |NVCC_3V3
+
| rowspan="2" |R24
−
| rowspan="5" |I/O
+
| rowspan="2" |NVCC_3V3
−
| rowspan="5" |
+
(NVCC_1V8 on request)
 +
| rowspan="2" |I/O
 +
| rowspan="2" |
 
|ALT0
 
|ALT0
−
|SAI2_TX_SYNC
+
|USDHC1_RESET_B
 
|-
 
|-
−
|ALT1
+
|ALT5
−
|SAI5_TX_DATA1
+
|GPIO2_IO10
 
|-
 
|-
−
|ALT3
+
| rowspan="3" |J1.132
−
|SAI2_TX_DATA1
+
(eMMC on board)
 +
| rowspan="3" |NAND_CE2_B
 +
| rowspan="3" |CPU.NAND_CE2_B
 +
| rowspan="3" |F21
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 +
|RAWNAND_CE2_B
 
|-
 
|-
−
|ALT4
+
|ALT1
−
|UART1_CTS_B
+
|QSPI_B_SS0_B
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|GPIO4_IO24
+
|GPIO3_IO03
 
|-
 
|-
−
| rowspan="4" |J1.72
+
| rowspan="2" |J1.134
−
| rowspan="4" |SAI2_RXD0
+
(NAND on board)
−
| rowspan="4" |CPU.SAI2_RXD0
+
| rowspan="2" |SD1_STROBE
−
| rowspan="4" |AC24
+
| rowspan="2" |CPU.SD1_STROBE
−
| rowspan="4" |NVCC_3V3
+
| rowspan="2" |T24
−
| rowspan="4" |I/O
+
| rowspan="2" |NVCC_3V3
−
| rowspan="4" |
+
(NVCC_1V8 on request)
 +
| rowspan="2" |I/O
 +
| rowspan="2" |
 
|ALT0
 
|ALT0
−
|SAI2_RX_DATA0
+
|USDHC1_STROBE
−
|-
 
−
|ALT1
 
−
|SAI5_TX_DATA0
 
−
|-
 
−
|ALT4
 
−
|UART1_RTS_B
 
−
(Configure register IOMUXC_UART1_RTS_B_SELECT_INPUT for mode ALT4)
 
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|GPIO4_IO23
+
|GPIO2_IO11
 
|-
 
|-
−
| rowspan="3" |J1.74
+
| rowspan="3" |J1.134
−
| rowspan="3" |I2C4_SDA
+
(eMMC on board)
−
| rowspan="3" |CPU.I2C4_SDA
+
| rowspan="3" |NAND_CE3_B
−
| rowspan="3" |E13
+
| rowspan="3" |CPU.NAND_CE3_B
 +
| rowspan="3" |H20
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |NVCC_3V3
 
| rowspan="3" |I/O
 
| rowspan="3" |I/O
 
| rowspan="3" |
 
| rowspan="3" |
 
|ALT0
 
|ALT0
−
|I2C4_SDA
+
|RAWNAND_CE3_B
 
|-
 
|-
 
|ALT1
 
|ALT1
−
|PWM1_OUT
+
|QSPI_B_SS1_B
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|GPIO5_IO21
+
|GPIO3_IO034
 
|-
 
|-
−
| rowspan="4" |J1.76
+
|J1.136
−
| rowspan="4" |I2C4_SCL
+
(NAND on board)
−
| rowspan="4" |CPU.I2C4_SCL
+
|NAND_CLE
−
| rowspan="4" |D13
+
|CPU.NAND_CLE
−
| rowspan="4" |NVCC_3V3
+
|H21
−
| rowspan="4" |I/O
+
|NVCC_3V3
−
| rowspan="4" |
+
|I/O
−
|ALT0
+
|Internally used for NAND, do not connect
−
|I2C4_SCL
+
|
 +
|
 +
|-
 +
| rowspan="3" |J1.136
 +
(eMMC on board)
 +
| rowspan="3" |NAND_CLE
 +
| rowspan="3" |CPU.NAND_CLE
 +
| rowspan="3" |H21
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 +
|RAWNAND_CLE
 
|-
 
|-
 
|ALT1
 
|ALT1
−
|PWM2_OUT
+
|QSPI_B_SCLK
−
|-
 
−
|ALT2
 
−
|PCIE1_CLKREQ_B
 
−
(Configure register IOMUXC_PCIE1_CLKREQ_B_SELECT_INPUT for mode ALT2)
 
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|GPIO5_IO20
+
|GPIO3_IO05
 
|-
 
|-
−
| rowspan="6" |J1.78
+
| rowspan="2" |J1.138
−
| rowspan="6" |SAI5_RXD2
+
(NAND on board)
−
| rowspan="6" |CPU.SAI5_RXD2
+
| rowspan="2" |SD1_DATA0
−
| rowspan="6" |AD13
+
| rowspan="2" |CPU.SD1_DATA0
−
| rowspan="6" |NVCC_3V3
+
| rowspan="2" |M25
−
| rowspan="6" |I/O
+
| rowspan="2" |NVCC_3V3
−
| rowspan="6" |
+
(NVCC_1V8 on request)
 +
| rowspan="2" |I/O
 +
| rowspan="2" |
 
|ALT0
 
|ALT0
−
|SAI5_RX_DATA2
+
|USDHC1_DATA0
−
(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_2 for mode ALT0)
 
 
|-
 
|-
−
|ALT1
+
|ALT5
−
|SAI1_TX_DATA4
+
|GPIO2_IO02
 
|-
 
|-
−
|ALT2
+
| rowspan="3" |J1.138
−
|SAI1_TX_SYNC
+
(eMMC on board)
−
(Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT2)
+
| rowspan="3" |NAND_DATA00
 +
| rowspan="3" |CPU.NAND_DATA00
 +
| rowspan="3" |G20
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 +
|RAWNAND_DATA00
 
|-
 
|-
−
|ALT3
+
|ALT1
−
|SAI5_TX_BCLK
+
|QSPI_A_DATA0
−
(Configure register IOMUXC_SAI5_TX_BCLK_SELECT_INPUT for mode ALT3)
 
 
|-
 
|-
−
|ALT4
+
|ALT5
−
|PDM_BIT_STREAM2
+
|GPIO3_IO06
−
(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_2 for mode ALT4)
+
|-
 +
| rowspan="2" |J1.140
 +
(NAND on board)
 +
| rowspan="2" |SD1_DATA1
 +
| rowspan="2" |CPU.SD1_DATA1
 +
| rowspan="2" |M24
 +
| rowspan="2" |NVCC_3V3
 +
(NVCC_1V8 on request)
 +
| rowspan="2" |I/O
 +
| rowspan="2" |
 +
|ALT0
 +
|USDHC1_DATA1
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|GPIO3_IO23
+
|GPIO2_IO0
 
|-
 
|-
−
| rowspan="6" |J1.80
+
| rowspan="3" |J1.140
−
| rowspan="6" |SAI5_RXD3
+
(eMMC on board)
−
| rowspan="6" |CPU.SAI5_RXD3
+
| rowspan="3" |NAND_DATA01
−
| rowspan="6" |AC13
+
| rowspan="3" |CPU.NAND_DATA01
−
| rowspan="6" |NVCC_3V3
+
| rowspan="3" |J20
−
| rowspan="6" |I/O
+
| rowspan="3" |NVCC_3V3
−
| rowspan="6" |
+
| rowspan="3" |I/O
 +
| rowspan="3" |
 
|ALT0
 
|ALT0
−
|SAI5_RX_DATA3
+
|RAWNAND_DATA01
−
(Configure register IOMUXC_SAI5_RX_DATA_SELECT_INPUT_3 for mode ALT0)
 
 
|-
 
|-
 
|ALT1
 
|ALT1
−
|SAI1_TX_DATA5
+
|QSPI_A_DATA1
 +
|-
 +
|ALT5
 +
|GPIO3_IO07
 +
|-
 +
| rowspan="2" |J1.142
 +
(NAND on board)
 +
| rowspan="2" |SD1_DATA2
 +
| rowspan="2" |CPU.SD1_DATA2
 +
| rowspan="2" |N25
 +
| rowspan="2" |NVCC_3V3
 +
(NVCC_1V8 on request)
 +
| rowspan="2" |I/O
 +
| rowspan="2" |
 +
|ALT0
 +
|USDHC1_DATA2
 
|-
 
|-
−
|ALT2
+
|ALT5
−
|SAI1_TX_SYNC
+
|GPIO2_IO04
−
(Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT2)
 
 
|-
 
|-
−
|ALT3
+
| rowspan="3" |J1.142
−
|SAI5_TX_DATA0
+
(eMMC on board)
 +
| rowspan="3" |NAND_DATA02
 +
| rowspan="3" |CPU.NAND_DATA02
 +
| rowspan="3" |H22
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 +
|RAWNAND_DATA02
 
|-
 
|-
−
|ALT4
+
|ALT1
−
|PDM_BIT_STREAM3
+
|QSPI_A_DATA2
−
(Configure register IOMUXC_PDM_BIT_STREAM_SELECT_INPUT_3 for mode ALT4)
 
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|GPIO3_IO24
+
|GPIO3_IO08
 
|-
 
|-
−
|J1.82
+
| rowspan="2" |J1.144
 +
(NAND on board)
 +
| rowspan="2" |SD1_DATA3
 +
| rowspan="2" |CPU.SD1_DATA3
 +
| rowspan="2" |P25
 +
| rowspan="2" |NVCC_3V3
 +
(NVCC_1V8 on request)
 +
| rowspan="2" |I/O
 +
| rowspan="2" |
 +
|ALT0
 +
|USDHC1_DATA3
 +
|-
 +
|ALT5
 +
|GPIO2_IO05
 +
|-
 +
| rowspan="3" |J1.144
 +
(eMMC on board)
 +
| rowspan="3" |NAND_DATA03
 +
| rowspan="3" |CPU.NAND_DATA03
 +
| rowspan="3" |J21
 +
| rowspan="3" |NVCC_3V3
 +
| rowspan="3" |I/O
 +
| rowspan="3" |
 +
|ALT0
 +
|RAWNAND_DATA03
 +
|-
 +
|ALT1
 +
|QSPI_A_DATA3
 +
|-
 +
|ALT5
 +
|GPIO3_IO09
 +
|-
 +
|J1.146
 
|DGND
 
|DGND
 
|DGND
 
|DGND
Line 2,421: Line 2,544:
 
|
 
|
 
|-
 
|-
−
|J1.84
+
| rowspan="2" |J1.148
−
|PCIE1_REF_CLKN
+
(NAND on board)
−
|CPU.PCIE_REF_CLK_N
+
| rowspan="2" |SD1_DATA4
−
|A21
+
| rowspan="2" |CPU.SD1_DATA4
−
|VDDA_1V8
+
| rowspan="2" |N24
−
|D
+
| rowspan="2" |NVCC_3V3
−
|
+
(NVCC_1V8 on request)
−
|
+
| rowspan="2" |I/O
−
|
+
| rowspan="2" |
 +
|ALT0
 +
|USDHC1_DATA4
 +
|-
 +
|ALT5
 +
|GPIO2_IO06
 
|-
 
|-
−
|J1.86
+
| rowspan="3" |J1.148
−
|PCIE1_REF_CLKP
+
(eMMC on board)
−
|CPU.PCIE_REF_CLK_P
+
| rowspan="3" |NAND_DATA04
−
|B21
+
| rowspan="3" |CPU.NAND_DATA04
−
|VDDA_1V8
+
| rowspan="3" |L20
−
|D
+
| rowspan="3" |NVCC_3V3
−
|
+
| rowspan="3" |I/O
−
|
+
| rowspan="3" |
−
|
+
|ALT0
 +
|RAWNAND_DATA04
 
|-
 
|-
−
|J1.88
+
|ALT1
−
|CLKIN1
+
|QSPI_B_DATA0
−
|CPU.CLKIN1
 
−
|H27
 
−
|NVCC_3V3
 
−
|I
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.90
+
|ALT5
−
|CLKIN2
+
|GPIO3_IO10
−
|CPU.CLKIN2
 
−
|J27
 
−
|NVCC_3V3
 
−
|I
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.92
+
| rowspan="2" |J1.150
−
|PCIE1_RXN
+
(NAND on board)
−
|CPU.PCIE_RXN_N
+
| rowspan="2" |SD1_DATA5
−
|A19
+
| rowspan="2" |CPU.SD1_DATA5
−
|VDDA_1V8
+
| rowspan="2" |P24
−
|D
+
| rowspan="2" |NVCC_3V3
−
|
+
(NVCC_1V8 on request)
−
|
+
| rowspan="2" |I/O
−
|
+
| rowspan="2" |
 +
|ALT0
 +
|USDHC1_DATA5
 
|-
 
|-
−
|J1.94
+
|ALT5
−
|PCIE1_RXP
+
|GPIO2_IO07
−
|CPU.PCIE_RXN_P
 
−
|B19
 
−
|VDDA_1V8
 
−
|D
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.96
+
| rowspan="3" |J1.150
−
|PCIE1_TXN
+
(eMMC on board)
−
|CPU.PCIE_TXN_N
+
| rowspan="3" |NAND_DATA05
−
|A20
+
| rowspan="3" |CPU.NAND_DATA05
−
|VDDA_1V8
+
| rowspan="3" |J22
−
|D
+
| rowspan="3" |NVCC_3V3
−
|
+
| rowspan="3" |I/O
−
|
+
| rowspan="3" |
−
|
+
|ALT0
 +
|RAWNAND_DATA05
 
|-
 
|-
−
|J1.98
+
|ALT1
−
|PCIE1_TXP
+
|QSPI_B_DATA1
−
|CPU.PCIE_TXN_P
 
−
|B20
 
−
|VDDA_1V8
 
−
|D
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.100
+
|ALT5
−
|DGND
+
|GPIO3_IO11
−
|DGND
 
−
| -
 
−
|<nowiki>-</nowiki>
 
−
|G
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.102
+
| rowspan="2" |J1.152
−
|CSI_P1_CKN
+
(NAND on board)
−
|CPU.MIPI_CSI_CLK_N
+
| rowspan="2" |SD1_DATA6
−
|A16
+
| rowspan="2" |CPU.SD1_DATA6
−
| -
+
| rowspan="2" |R25
−
|D
+
| rowspan="2" |NVCC_3V3
−
|
+
(NVCC_1V8 on request)
−
|
+
| rowspan="2" |I/O
−
|
+
| rowspan="2" |
 +
|ALT0
 +
|USDHC1_DATA6
 
|-
 
|-
−
|J1.104
+
|ALT5
−
|CSI_P1_CKP
+
|GPIO2_IO08
−
|CPU.MIPI_CSI_CLK_P
 
−
|B16
 
−
| -
 
−
|D
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.106
+
| rowspan="3" |J1.152
−
|CSI_P1_DN0
+
(eMMC on board)
−
|CPU.MIPI_CSI_D0_N
+
| rowspan="3" |NAND_DATA06
−
|A14
+
| rowspan="3" |CPU.NAND_DATA06
−
| -
+
| rowspan="3" |L19
−
|D
+
| rowspan="3" |NVCC_3V3
−
|
+
| rowspan="3" |I/O
−
|
+
| rowspan="3" |
−
|
+
|ALT0
 +
|RAWNAND_DATA06
 
|-
 
|-
−
|J1.108
+
|ALT1
−
|CSI_P1_DP0
+
|QSPI_B_DATA2
−
|CPU.MIPI_CSI_D0_P
+
|-
−
|B14
+
|ALT5
−
| -
+
|GPIO3_IO12
−
|D
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.110
+
| rowspan="2" |J1.154
−
|CSI_P1_DN1
+
(NAND on board)
−
|CPU.MIPI_CSI_D1_N
+
| rowspan="2" |SD1_DATA7
−
|A15
+
| rowspan="2" |CPU.SD1_DATA7
−
| -
+
| rowspan="2" |T25
−
|D
+
| rowspan="2" |NVCC_3V3
−
|
+
(NVCC_1V8 on request)
−
|
+
| rowspan="2" |I/O
−
|
+
| rowspan="2" |
 +
|ALT0
 +
|USDHC1_DATA7
 
|-
 
|-
−
|J1.112
+
|ALT5
−
|CSI_P1_DP1
+
|GPIO2_IO09
−
|CPU.MIPI_CSI_D1_P
 
−
|B15
 
−
| -
 
−
|D
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.114
+
| rowspan="3" |J1.154
−
|CSI_P1_DN2
+
(eMMC on board)
−
|CPU.MIPI_CSI_D2_N
+
| rowspan="3" |NAND_DATA07
−
|A17
+
| rowspan="3" |CPU.NAND_DATA07
−
| -
+
| rowspan="3" |M19
−
|D
+
| rowspan="3" |NVCC_3V3
−
|
+
| rowspan="3" |I/O
−
|
+
| rowspan="3" |
−
|
+
|ALT0
 +
|RAWNAND_DATA07
 +
|-
 +
|ALT1
 +
|QSPI_B_DATA3
 
|-
 
|-
−
|J1.116
+
|ALT5
−
|CSI_P1_DP2
+
|GPIO3_IO13
−
|CPU.MIPI_CSI_D2_P
 
−
|B17
 
−
| -
 
−
|D
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.118
+
|J1.156
−
|CSI_P1_DN3
+
(NAND on board)
−
|CPU.MIPI_CSI_D3_N
+
|NAND_RE_B
−
|A18
+
|CPU.NAND_RE_B
−
| -
+
|K19
−
|D
+
|NVCC_3V3
−
|
+
|I/O
 +
|Internally used for NAND, do not connect
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.120
+
| rowspan="3" |J1.156
−
|CSI_P1_DP3
+
(eMMC on board)
−
|CPU.MIPI_CSI_D3_P
+
| rowspan="3" |NAND_RE_B
−
|B18
+
| rowspan="3" |CPU.NAND_RE_B
−
| -
+
| rowspan="3" |K19
−
|D
+
| rowspan="3" |NVCC_3V3
−
|
+
| rowspan="3" |I/O
−
|
+
| rowspan="3" |
−
|
+
|ALT0
 +
|RAWNAND_RE_B
 +
|-
 +
|ALT1
 +
|QSPI_B_DQS
 
|-
 
|-
−
|J1.122
+
|ALT5
−
|DGND
+
|GPIO3_IO15
−
|DGND
 
−
| -
 
−
|<nowiki>-</nowiki>
 
−
|G
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.124
+
|J1.158
 
(NAND on board)
 
(NAND on board)
−
|NAND_DQS
+
|NAND_READY_B
−
|CPU.NAND_DQS
+
|CPU.NAND_READY_B
−
|R22
+
|K20
 
|NVCC_3V3
 
|NVCC_3V3
 
|I/O
 
|I/O
Line 2,632: Line 2,711:
 
|
 
|
 
|-
 
|-
−
| rowspan="3" |J1.124
+
| rowspan="2" |J1.158
 
(eMMC on board)
 
(eMMC on board)
−
| rowspan="3" |NAND_DQS
+
| rowspan="2" |NAND_READY_B
−
| rowspan="3" |CPU.NAND_DQS
+
| rowspan="2" |CPU.NAND_READY_B
−
| rowspan="3" |R22
+
| rowspan="2" |K20
−
| rowspan="3" |NVCC_3V3
+
| rowspan="2" |NVCC_3V3
−
| rowspan="3" |I/O
+
| rowspan="2" |I/O
−
| rowspan="3" |
+
| rowspan="2" |
 
|ALT0
 
|ALT0
−
|RAWNAND_DQS
+
|RAWNAND_READY_B
−
|-
 
−
|ALT1
 
−
|QSPI_A_DQS
 
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|GPIO3_IO14
+
|GPIO3_IO16
 
|-
 
|-
−
|J1.126
+
|J1.160
 
(NAND on board)
 
(NAND on board)
−
|NAND_ALE
+
|NAND_WE_B
−
|CPU.NAND_ALE
+
|CPU.NAND_WE_B
−
|N22
+
|K22
 
|NVCC_3V3
 
|NVCC_3V3
 
|I/O
 
|I/O
Line 2,660: Line 2,736:
 
|
 
|
 
|-
 
|-
−
| rowspan="3" |J1.126
+
| rowspan="2" |J1.160
 
(eMMC on board)
 
(eMMC on board)
−
| rowspan="3" |NAND_ALE
+
| rowspan="2" |NAND_WE_B
−
| rowspan="3" |CPU.NAND_ALE
+
| rowspan="2" |CPU.NAND_WE_B
−
| rowspan="3" |N22
+
| rowspan="2" |K22
−
| rowspan="3" |NVCC_3V3
+
| rowspan="2" |NVCC_3V3
−
| rowspan="3" |I/O
+
| rowspan="2" |I/O
−
| rowspan="3" |
+
| rowspan="2" |
 
|ALT0
 
|ALT0
−
|RAWNAND_ALE
+
|RAWNAND_WE_B
−
|-
 
−
|ALT1
 
−
|QSPI_A_SCLK
 
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|GPIO3_IO00
+
|GPIO3_IO17
 
|-
 
|-
−
| rowspan="2" |J1.128
+
|J1.162
 
(NAND on board)
 
(NAND on board)
−
| rowspan="2" |SD1_CLK
+
|NAND_WP_B
−
| rowspan="2" |CPU.SD1_CLK
+
|CPU.NAND_WP_B
−
| rowspan="2" |V26
+
|K21
 +
|NVCC_3V3
 +
|I/O
 +
|Internally used for NAND, do not connect
 +
|
 +
|
 +
|-
 +
| rowspan="2" |J1.162
 +
(eMMC on board)
 +
| rowspan="2" |NAND_WP_B
 +
| rowspan="2" |CPU.NAND_WP_B
 +
| rowspan="2" |K21
 
| rowspan="2" |NVCC_3V3
 
| rowspan="2" |NVCC_3V3
−
(NVCC_1V8 on request)
 
 
| rowspan="2" |I/O
 
| rowspan="2" |I/O
 
| rowspan="2" |
 
| rowspan="2" |
 
|ALT0
 
|ALT0
−
|USDHC1_CLK
+
|RAWNAND_WP_B
 
|-
 
|-
 
|ALT5
 
|ALT5
−
|GPIO2_IO00
+
|GPIO3_IO18
 
|-
 
|-
−
| rowspan="3" |J1.128
+
|J1.164
−
(eMMC on board)
+
|DGND
−
| rowspan="3" |NAND_CE0_B
+
|DGND
−
| rowspan="3" |CPU.NAND_CE0_B
+
| -
−
| rowspan="3" |N24
+
|<nowiki>-</nowiki>
−
| rowspan="3" |NVCC_3V3
+
|G
−
| rowspan="3" |I/O
+
|
−
| rowspan="3" |
+
|
−
|ALT0
+
|
−
|RAWNAND_CE0_B
 
 
|-
 
|-
−
|ALT1
+
|J1.166
−
|QSPI_A_SS0_B
+
|CLK1_N
 +
|CPU.CLK1_N
 +
|T23
 +
|
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
|ALT5
+
|J1.168
−
|GPIO3_IO01
+
|CLK1_P
 +
|CPU.CLK1_P
 +
|R23
 +
|
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
| rowspan="2" |J1.130
+
|J1.170
−
(NAND on board)
+
|USB2_RXN
−
| rowspan="2" |SD1_CMD
+
|CPU.USB2_RX_N
−
| rowspan="2" |CPU.SD1_CMD
+
|B8
−
| rowspan="2" |V27
+
|
−
| rowspan="2" |NVCC_3V3
+
|D
−
(NVCC_1V8 on request)
+
|
−
| rowspan="2" |I/O
+
|
−
| rowspan="2" |
+
|
−
|ALT0
 
−
|USDHC1_CMD
 
 
|-
 
|-
−
|ALT5
+
|J1.172
−
|GPIO2_IO01
+
|USB2_RXP
 +
|CPU.USB2_RX_P
 +
|A8
 +
|
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
| rowspan="4" |J1.130
+
|J1.174
−
(eMMC on board)
+
|USB2_TXN
−
| rowspan="4" |NAND_CE1_B
+
|CPU.USB2_TX_N
−
| rowspan="4" |CPU.NAND_CE1_B
+
|B9
−
| rowspan="4" |P27
+
|
−
| rowspan="4" |NVCC_3V3
+
|D
−
| rowspan="4" |I/O
+
|
−
| rowspan="4" |
+
|
−
|ALT0
+
|
−
|RAWNAND_CE1_B
 
 
|-
 
|-
−
|ALT1
+
|J1.176
−
|QSPI_A_SS1_B
+
|USB2_TXP
 +
|CPU.USB2_TX_P
 +
|A9
 +
|
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
|ALT2
+
|J1.178
−
|USDHC3_STROBE
+
|USB1_RXN
 +
|CPU.USB1_RX_N
 +
|B12
 +
|
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
|ALT5
+
|J1.180
−
|GPIO3_IO02
+
|USB1_RXP
 +
|CPU.USB1_RX_P
 +
|A12
 +
|
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
| rowspan="2" |J1.132
+
|J1.182
−
(NAND on board)
+
|USB1_TXN
−
| rowspan="2" |SD1_RST_B
+
|CPU.USB1_TX_N
−
| rowspan="2" |CPU.SD1_RST_B
+
|B13
−
| rowspan="2" |R23
+
|
−
| rowspan="2" |NVCC_3V3
+
|D
−
(NVCC_1V8 on request)
+
|
−
| rowspan="2" |I/O
+
|
−
| rowspan="2" |
+
|
−
|ALT0
 
−
|USDHC1_RESET_B
 
 
|-
 
|-
−
|ALT5
+
|J1.184
−
|GPIO2_IO10
+
|USB1_TXP
 +
|CPU.USB1_TX_P
 +
|A13
 +
|
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
| rowspan="4" |J1.132
+
|J1.186
−
(eMMC on board)
+
|USB1_VBUS
−
| rowspan="4" |NAND_CE2_B
+
|CPU.USB1_VBUS
−
| rowspan="4" |CPU.NAND_CE2_B
+
|D14
−
| rowspan="4" |M27
+
| -
−
| rowspan="4" |NVCC_3V3
+
|S
−
| rowspan="4" |I/O
+
|
−
| rowspan="4" |
+
|
−
|ALT0
+
|
−
|RAWNAND_CE2_B
 
 
|-
 
|-
−
|ALT1
+
|J1.188
−
|QSPI_B_SS0_B
+
|USB2_VBUS
 +
|CPU.USB2_VBUS
 +
|D9
 +
| -
 +
|S
 +
|
 +
|
 +
|
 
|-
 
|-
−
|ALT2
+
|J1.190
−
|USDHC3_DATA5
+
|DGND
 +
|DGND
 +
| -
 +
|<nowiki>-</nowiki>
 +
|G
 +
|
 +
|
 +
|
 
|-
 
|-
−
|ALT5
+
|J1.192
−
|GPIO3_IO03
+
|USB1_ID
 +
|CPU.USB1_ID
 +
|C14
 +
|VDD_PHY_3V3
 +
|I
 +
|
 +
|
 +
|
 
|-
 
|-
−
| rowspan="2" |J1.134
+
|J1.194
−
(NAND on board)
+
|USB2_ID
−
| rowspan="2" |SD1_STROBE
+
|CPU.USB2_ID
−
| rowspan="2" |CPU.SD1_STROBE
+
|C9
−
| rowspan="2" |R24
+
|VDD_PHY_3V3
−
| rowspan="2" |NVCC_3V3
+
|I
−
(NVCC_1V8 on request)
+
|
−
| rowspan="2" |I/O
+
|
−
| rowspan="2" |
+
|
−
|ALT0
 
−
|USDHC1_STROBE
 
 
|-
 
|-
−
|ALT5
+
|J1.196
−
|GPIO2_IO11
+
|USB1_DN
 +
|CPU.USB1_DN
 +
|B14
 +
| -
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
| rowspan="4" |J1.134
+
|J1.198
−
(eMMC on board)
+
|USB1_DP
−
| rowspan="4" |NAND_CE3_B
+
|CPU.USB1_DP
−
| rowspan="4" |CPU.NAND_CE3_B
+
|A14
−
| rowspan="4" |L27
+
| -
−
| rowspan="4" |NVCC_3V3
+
|D
−
| rowspan="4" |I/O
 
−
| rowspan="4" |
 
−
|ALT0
 
−
|RAWNAND_CE3_B
 
−
|-
 
−
|ALT1
 
−
|QSPI_B_SS1_B
 
−
|-
 
−
|ALT2
 
−
|USDHC3_DATA6
 
−
|-
 
−
|ALT5
 
−
|GPIO3_IO034
 
−
|-
 
−
|J1.136
 
−
(NAND on board)
 
−
|NAND_CLE
 
−
|CPU.NAND_CLE
 
−
|K27
 
−
|NVCC_3V3
 
−
|I/O
 
−
|Internally used for NAND, do not connect
 
−
|
 
−
|
 
−
|-
 
−
| rowspan="4" |J1.136
 
−
(eMMC on board)
 
−
| rowspan="4" |NAND_CLE
 
−
| rowspan="4" |CPU.NAND_CLE
 
−
| rowspan="4" |K27
 
−
| rowspan="4" |NVCC_3V3
 
−
| rowspan="4" |I/O
 
−
| rowspan="4" |
 
−
|ALT0
 
−
|RAWNAND_CLE
 
−
|-
 
−
|ALT1
 
−
|QSPI_B_SCLK
 
−
|-
 
−
|ALT2
 
−
|USDHC3_DATA7
 
−
|-
 
−
|ALT5
 
−
|GPIO3_IO05
 
−
|-
 
−
| rowspan="2" |J1.138
 
−
(NAND on board)
 
−
| rowspan="2" |SD1_DATA0
 
−
| rowspan="2" |CPU.SD1_DATA0
 
−
| rowspan="2" |Y27
 
−
| rowspan="2" |NVCC_3V3
 
−
(NVCC_1V8 on request)
 
−
| rowspan="2" |I/O
 
−
| rowspan="2" |
 
−
|ALT0
 
−
|USDHC1_DATA0
 
−
|-
 
−
|ALT5
 
−
|GPIO2_IO02
 
−
|-
 
−
| rowspan="3" |J1.138
 
−
(eMMC on board)
 
−
| rowspan="3" |NAND_DATA00
 
−
| rowspan="3" |CPU.NAND_DATA00
 
−
| rowspan="3" |P23
 
−
| rowspan="3" |NVCC_3V3
 
−
| rowspan="3" |I/O
 
−
| rowspan="3" |
 
−
|ALT0
 
−
|RAWNAND_DATA00
 
−
|-
 
−
|ALT1
 
−
|QSPI_A_DATA0
 
−
|-
 
−
|ALT5
 
−
|GPIO3_IO06
 
−
|-
 
−
| rowspan="2" |J1.140
 
−
(NAND on board)
 
−
| rowspan="2" |SD1_DATA1
 
−
| rowspan="2" |CPU.SD1_DATA1
 
−
| rowspan="2" |Y26
 
−
| rowspan="2" |NVCC_3V3
 
−
(NVCC_1V8 on request)
 
−
| rowspan="2" |I/O
 
−
| rowspan="2" |
 
−
|ALT0
 
−
|USDHC1_DATA1
 
−
|-
 
−
|ALT5
 
−
|GPIO2_IO0
 
−
|-
 
−
| rowspan="3" |J1.140
 
−
(eMMC on board)
 
−
| rowspan="3" |NAND_DATA01
 
−
| rowspan="3" |CPU.NAND_DATA01
 
−
| rowspan="3" |K24
 
−
| rowspan="3" |NVCC_3V3
 
−
| rowspan="3" |I/O
 
−
| rowspan="3" |
 
−
|ALT0
 
−
|RAWNAND_DATA01
 
−
|-
 
−
|ALT1
 
−
|QSPI_A_DATA1
 
−
|-
 
−
|ALT5
 
−
|GPIO3_IO07
 
−
|-
 
−
| rowspan="2" |J1.142
 
−
(NAND on board)
 
−
| rowspan="2" |SD1_DATA2
 
−
| rowspan="2" |CPU.SD1_DATA2
 
−
| rowspan="2" |T27
 
−
| rowspan="2" |NVCC_3V3
 
−
(NVCC_1V8 on request)
 
−
| rowspan="2" |I/O
 
−
| rowspan="2" |
 
−
|ALT0
 
−
|USDHC1_DATA2
 
−
|-
 
−
|ALT5
 
−
|GPIO2_IO04
 
−
|-
 
−
| rowspan="4" |J1.142
 
−
(eMMC on board)
 
−
| rowspan="4" |NAND_DATA02
 
−
| rowspan="4" |CPU.NAND_DATA02
 
−
| rowspan="4" |K23
 
−
| rowspan="4" |NVCC_3V3
 
−
| rowspan="4" |I/O
 
−
| rowspan="4" |
 
−
|ALT0
 
−
|RAWNAND_DATA02
 
−
|-
 
−
|ALT1
 
−
|QSPI_A_DATA2
 
−
|-
 
−
|ALT2
 
−
|USDHC3_CD_B
 
−
(Configure register IOMUXC_USDHC3_CD_B_SELECT_INPUT for mode ALT2)
 
−
|-
 
−
|ALT5
 
−
|GPIO3_IO08
 
−
|-
 
−
| rowspan="2" |J1.144
 
−
(NAND on board)
 
−
| rowspan="2" |SD1_DATA3
 
−
| rowspan="2" |CPU.SD1_DATA3
 
−
| rowspan="2" |T26
 
−
| rowspan="2" |NVCC_3V3
 
−
(NVCC_1V8 on request)
 
−
| rowspan="2" |I/O
 
−
| rowspan="2" |
 
−
|ALT0
 
−
|USDHC1_DATA3
 
−
|-
 
−
|ALT5
 
−
|GPIO2_IO05
 
−
|-
 
−
| rowspan="4" |J1.144
 
−
(eMMC on board)
 
−
| rowspan="4" |NAND_DATA03
 
−
| rowspan="4" |CPU.NAND_DATA03
 
−
| rowspan="4" |N23
 
−
| rowspan="4" |NVCC_3V3
 
−
| rowspan="4" |I/O
 
−
| rowspan="4" |
 
−
|ALT0
 
−
|RAWNAND_DATA03
 
−
|-
 
−
|ALT1
 
−
|QSPI_A_DATA3
 
−
|-
 
−
|ALT2
 
−
|USDHC3_WP
 
−
(Configure register IOMUXC_USDHC3_WP_SELECT_INPUT for mode ALT2)
 
−
|-
 
−
|ALT5
 
−
|GPIO3_IO09
 
−
|-
 
−
|J1.146
 
−
|DGND
 
−
|DGND
 
−
| -
 
−
|<nowiki>-</nowiki>
 
−
|G
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
| rowspan="2" |J1.148
 
−
(NAND on board)
 
−
| rowspan="2" |SD1_DATA4
 
−
| rowspan="2" |CPU.SD1_DATA4
 
−
| rowspan="2" |U27
 
−
| rowspan="2" |NVCC_3V3
 
−
(NVCC_1V8 on request)
 
−
| rowspan="2" |I/O
 
−
| rowspan="2" |
 
−
|ALT0
 
−
|USDHC1_DATA4
 
−
|-
 
−
|ALT5
 
−
|GPIO2_IO06
 
−
|-
 
−
| rowspan="4" |J1.148
 
−
(eMMC on board)
 
−
| rowspan="4" |NAND_DATA04
 
−
| rowspan="4" |CPU.NAND_DATA04
 
−
| rowspan="4" |M26
 
−
| rowspan="4" |NVCC_3V3
 
−
| rowspan="4" |I/O
 
−
| rowspan="4" |
 
−
|ALT0
 
−
|RAWNAND_DATA04
 
−
|-
 
−
|ALT1
 
−
|QSPI_B_DATA0
 
−
|-
 
−
|ALT2
 
−
|USDHC3_DATA0
 
−
|-
 
−
|ALT5
 
−
|GPIO3_IO10
 
−
|-
 
−
| rowspan="2" |J1.150
 
−
(NAND on board)
 
−
| rowspan="2" |SD1_DATA5
 
−
| rowspan="2" |CPU.SD1_DATA5
 
−
| rowspan="2" |U26
 
−
| rowspan="2" |NVCC_3V3
 
−
(NVCC_1V8 on request)
 
−
| rowspan="2" |I/O
 
−
| rowspan="2" |
 
−
|ALT0
 
−
|USDHC1_DATA5
 
−
|-
 
−
|ALT5
 
−
|GPIO2_IO07
 
−
|-
 
−
| rowspan="4" |J1.150
 
−
(eMMC on board)
 
−
| rowspan="4" |NAND_DATA05
 
−
| rowspan="4" |CPU.NAND_DATA05
 
−
| rowspan="4" |L26
 
−
| rowspan="4" |NVCC_3V3
 
−
| rowspan="4" |I/O
 
−
| rowspan="4" |
 
−
|ALT0
 
−
|RAWNAND_DATA05
 
−
|-
 
−
|ALT1
 
−
|QSPI_B_DATA1
 
−
|-
 
−
|ALT2
 
−
|USDHC3_DATA1
 
−
|-
 
−
|ALT5
 
−
|GPIO3_IO11
 
−
|-
 
−
| rowspan="2" |J1.152
 
−
(NAND on board)
 
−
| rowspan="2" |SD1_DATA6
 
−
| rowspan="2" |CPU.SD1_DATA6
 
−
| rowspan="2" |W27
 
−
| rowspan="2" |NVCC_3V3
 
−
(NVCC_1V8 on request)
 
−
| rowspan="2" |I/O
 
−
| rowspan="2" |
 
−
|ALT0
 
−
|USDHC1_DATA6
 
−
|-
 
−
|ALT5
 
−
|GPIO2_IO08
 
−
|-
 
−
| rowspan="4" |J1.152
 
−
(eMMC on board)
 
−
| rowspan="4" |NAND_DATA06
 
−
| rowspan="4" |CPU.NAND_DATA06
 
−
| rowspan="4" |K26
 
−
| rowspan="4" |NVCC_3V3
 
−
| rowspan="4" |I/O
 
−
| rowspan="4" |
 
−
|ALT0
 
−
|RAWNAND_DATA06
 
−
|-
 
−
|ALT1
 
−
|QSPI_B_DATA2
 
−
|-
 
−
|ALT2
 
−
|USDHC3_DATA2
 
−
|-
 
−
|ALT5
 
−
|GPIO3_IO12
 
−
|-
 
−
| rowspan="2" |J1.154
 
−
(NAND on board)
 
−
| rowspan="2" |SD1_DATA7
 
−
| rowspan="2" |CPU.SD1_DATA7
 
−
| rowspan="2" |W26
 
−
| rowspan="2" |NVCC_3V3
 
−
(NVCC_1V8 on request)
 
−
| rowspan="2" |I/O
 
−
| rowspan="2" |
 
−
|ALT0
 
−
|USDHC1_DATA7
 
−
|-
 
−
|ALT5
 
−
|GPIO2_IO09
 
−
|-
 
−
| rowspan="4" |J1.154
 
−
(eMMC on board)
 
−
| rowspan="4" |NAND_DATA07
 
−
| rowspan="4" |CPU.NAND_DATA07
 
−
| rowspan="4" |N26
 
−
| rowspan="4" |NVCC_3V3
 
−
| rowspan="4" |I/O
 
−
| rowspan="4" |
 
−
|ALT0
 
−
|RAWNAND_DATA07
 
−
|-
 
−
|ALT1
 
−
|QSPI_B_DATA3
 
−
|-
 
−
|ALT2
 
−
|USDHC3_DATA3
 
−
|-
 
−
|ALT5
 
−
|GPIO3_IO13
 
−
|-
 
−
|J1.156
 
−
(NAND on board)
 
−
|NAND_RE_B
 
−
|CPU.NAND_RE_B
 
−
|N27
 
−
|NVCC_3V3
 
−
|I/O
 
−
|Internally used for NAND, do not connect
 
−
|
 
−
|
 
−
|-
 
−
| rowspan="4" |J1.156
 
−
(eMMC on board)
 
−
| rowspan="4" |NAND_RE_B
 
−
| rowspan="4" |CPU.NAND_RE_B
 
−
| rowspan="4" |N27
 
−
| rowspan="4" |NVCC_3V3
 
−
| rowspan="4" |I/O
 
−
| rowspan="4" |
 
−
|ALT0
 
−
|RAWNAND_RE_B
 
−
|-
 
−
|ALT1
 
−
|QSPI_B_DQS
 
−
|-
 
−
|ALT2
 
−
|USDHC3_DATA4
 
−
|-
 
−
|ALT5
 
−
|GPIO3_IO15
 
−
|-
 
−
|J1.158
 
−
(NAND on board)
 
−
|NAND_READY_B
 
−
|CPU.NAND_READY_B
 
−
|P26
 
−
|NVCC_3V3
 
−
|I/O
 
−
|Internally used for NAND, do not connect
 
−
|
 
−
|
 
−
|-
 
−
| rowspan="3" |J1.158
 
−
(eMMC on board)
 
−
| rowspan="3" |NAND_READY_B
 
−
| rowspan="3" |CPU.NAND_READY_B
 
−
| rowspan="3" |P26
 
−
| rowspan="3" |NVCC_3V3
 
−
| rowspan="3" |I/O
 
−
| rowspan="3" |
 
−
|ALT0
 
−
|RAWNAND_READY_B
 
−
|-
 
−
|ALT2
 
−
|USDHC3_RESET_B
 
−
|-
 
−
|ALT5
 
−
|GPIO3_IO16
 
−
|-
 
−
|J1.160
 
−
(NAND on board)
 
−
|NAND_WE_B
 
−
|CPU.NAND_WE_B
 
−
|R26
 
−
|NVCC_3V3
 
−
|I/O
 
−
|Internally used for NAND, do not connect
 
−
|
 
−
|
 
−
|-
 
−
| rowspan="3" |J1.160
 
−
(eMMC on board)
 
−
| rowspan="3" |NAND_WE_B
 
−
| rowspan="3" |CPU.NAND_WE_B
 
−
| rowspan="3" |R26
 
−
| rowspan="3" |NVCC_3V3
 
−
| rowspan="3" |I/O
 
−
| rowspan="3" |
 
−
|ALT0
 
−
|RAWNAND_WE_B
 
−
|-
 
−
|ALT2
 
−
|USDHC3_CLK
 
−
|-
 
−
|ALT5
 
−
|GPIO3_IO17
 
−
|-
 
−
|J1.162
 
−
(NAND on board)
 
−
|NAND_WP_B
 
−
|CPU.NAND_WP_B
 
−
|R27
 
−
|NVCC_3V3
 
−
|I/O
 
−
|Internally used for NAND, do not connect
 
−
|
 
−
|
 
−
|-
 
−
| rowspan="3" |J1.162
 
−
(eMMC on board)
 
−
| rowspan="3" |NAND_WP_B
 
−
| rowspan="3" |CPU.NAND_WP_B
 
−
| rowspan="3" |R27
 
−
| rowspan="3" |NVCC_3V3
 
−
| rowspan="3" |I/O
 
−
| rowspan="3" |
 
−
|ALT0
 
−
|RAWNAND_WP_B
 
−
|-
 
−
|ALT2
 
−
|USDHC3_CMD
 
−
|-
 
−
|ALT5
 
−
|GPIO3_IO18
 
−
|-
 
−
|J1.164
 
−
|DGND
 
−
|DGND
 
−
| -
 
−
|<nowiki>-</nowiki>
 
−
|G
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
| rowspan="5" |J1.166
 
−
| rowspan="5" |GPIO1_IO15
 
−
| rowspan="5" |CPU.GPIO1_IO15
 
−
| rowspan="5" |AB9
 
−
| rowspan="5" |NVCC_3V3
 
−
| rowspan="5" |I/O
 
−
| rowspan="5" |
 
−
|ALT0
 
−
|GPIO1_IO15
 
−
|-
 
−
|ALT1
 
−
|USB2_OTG_OC
 
−
|-
 
−
|ALT4
 
−
|USDHC3_WP
 
−
(Configure register IOMUXC_USDHC3_WP_SELECT_INPUT for mode ALT4)
 
−
|-
 
−
|ALT5
 
−
|PWM4_OUT
 
−
|-
 
−
|ALT6
 
−
|CCM_CLKO2
 
−
|-
 
−
| rowspan="4" |J1.168
 
−
| rowspan="4" |GPIO1_IO07
 
−
| rowspan="4" |CPU.GPIO1_IO07
 
−
| rowspan="4" |AF11
 
−
| rowspan="4" |NVCC_3V3
 
−
| rowspan="4" |I/O
 
−
| rowspan="4" |
 
−
|ALT0
 
−
|GPIO1_IO07
 
−
|-
 
−
|ALT1
 
−
|ENET1_MDIO
 
−
(Configure register IOMUXC_ENET1_MDIO_SELECT_INPUT for mode ALT1)
 
−
|-
 
−
|ALT5
 
−
|USDHC1_WP
 
−
|-
 
−
|ALT6
 
−
|CCM_EXT_CLK4
 
−
|-
 
−
| rowspan="6" |J1.170
 
−
| rowspan="6" |SAI1_TXD4
 
−
| rowspan="6" |CPU.SAI1_TXD4
 
−
| rowspan="6" |AG22
 
−
| rowspan="6" |NVCC_3V3
 
−
| rowspan="6" |I/O
 
−
| rowspan="6" |Internally used for BOOT mode configuration:
 
−
 
 
−
can be pulled-up or down depending on
 
−
 
 
−
[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
 
−
|ALT0
 
−
|SAI1_TX_DATA4
 
−
|-
 
−
|ALT1
 
−
|SAI6_RX_BCLK
 
−
(Configure register IOMUXC_SAI6_RX_BCLK_SELECT_INPUT for mode ALT1)
 
−
|-
 
−
|ALT2
 
−
|SAI6_TX_BCLK
 
−
(Configure register IOMUXC_SAI6_TX_BCLK_SELECT_INPUT for mode ALT2)
 
−
|-
 
−
|ALT4
 
−
|CORESIGHT_TRACE12
 
−
|-
 
−
|ALT5
 
−
|GPIO4_IO16
 
−
|-
 
−
|ALT6
 
−
|SRC_BOOT_CFG12
 
−
|-
 
−
| rowspan="6" |J1.172
 
−
| rowspan="6" |SAI1_TXD5
 
−
| rowspan="6" |CPU.SAI1_TXD5
 
−
| rowspan="6" |AF22
 
−
| rowspan="6" |NVCC_3V3
 
−
| rowspan="6" |I/O
 
−
| rowspan="6" |Internally used for BOOT mode configuration:
 
−
 
 
−
can be pulled-up or down depending on
 
−
 
 
−
[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
 
−
|ALT0
 
−
|SAI1_TX_DATA5
 
−
|-
 
−
|ALT1
 
−
|SAI6_RX_DATA0
 
−
(Configure register IOMUXC_SAI6_RX_DATA_SELECT_INPUT_0 for mode ALT1)
 
−
|-
 
−
|ALT2
 
−
|SAI6_TX_DATA0
 
−
|-
 
−
|ALT4
 
−
|CORESIGHT_TRACE13
 
−
|-
 
−
|ALT5
 
−
|GPIO4_IO17
 
−
|-
 
−
|ALT6
 
−
|SRC_BOOT_CFG13
 
−
|-
 
−
| rowspan="6" |J1.174
 
−
| rowspan="6" |SAI1_TXD6
 
−
| rowspan="6" |CPU.SAI1_TXD6
 
−
| rowspan="6" |AG23
 
−
| rowspan="6" |NVCC_3V3
 
−
| rowspan="6" |I/O
 
−
| rowspan="6" |Internally used for BOOT mode configuration:
 
−
 
 
−
can be pulled-up or down depending on
 
−
 
 
−
[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
 
−
|ALT0
 
−
|SAI1_TX_DATA6
 
−
|-
 
−
|ALT1
 
−
|SAI6_RX_SYNC
 
−
(Configure register IOMUXC_SAI6_RX_SYNC_SELECT_INPUT for mode ALT1)
 
−
|-
 
−
|ALT2
 
−
|SAI6_TX_SYNC
 
−
(Configure register IOMUXC_SAI6_TX_SYNC_SELECT_INPUT for mode ALT2)
 
−
|-
 
−
|ALT4
 
−
|CORESIGHT_TRACE14
 
−
|-
 
−
|ALT5
 
−
|GPIO4_IO18
 
−
|-
 
−
|ALT6
 
−
|SRC_BOOT_CFG14
 
−
|-
 
−
| rowspan="6" |J1.176
 
−
| rowspan="6" |SAI1_TXD7
 
−
| rowspan="6" |CPU.SAI1_TXD7
 
−
| rowspan="6" |AF23
 
−
| rowspan="6" |NVCC_3V3
 
−
| rowspan="6" |I/O
 
−
| rowspan="6" |Internally used for BOOT mode configuration:
 
−
 
 
−
can be pulled-up or down depending on
 
−
 
 
−
[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
 
−
|ALT0
 
−
|SAI1_TX_DATA7
 
−
|-
 
−
|ALT1
 
−
|SAI6_MCLK
 
−
(Configure register IOMUXC_SAI6_MCLK_SELECT_INPUT for mode ALT1)
 
−
|-
 
−
|ALT3
 
−
|PDM_CLK
 
−
|-
 
−
|ALT4
 
−
|CORESIGHT_TRACE15
 
−
|-
 
−
|ALT5
 
−
|GPIO4_IO19
 
−
|-
 
−
|ALT6
 
−
|SRC_BOOT_CFG15
 
−
|-
 
−
| rowspan="7" |J1.178
 
−
| rowspan="7" |SAI1_RXD7
 
−
| rowspan="7" |CPU.SAI1_RXD7
 
−
| rowspan="7" |AF19
 
−
| rowspan="7" |NVCC_3V3
 
−
| rowspan="7" |I/O
 
−
| rowspan="7" |Internally used for BOOT mode configuration:
 
−
 
 
−
can be pulled-up or down depending on
 
−
 
 
−
[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
 
−
|ALT0
 
−
|SAI1_RX_DATA7
 
−
|-
 
−
|ALT1
 
−
|SAI6_MCLK
 
−
(Configure register IOMUXC_SAI6_MCLK_SELECT_INPUT for mode ALT1)
 
−
|-
 
−
|ALT2
 
−
|SAI1_TX_SYNC
 
−
(Configure register IOMUXC_SAI1_TX_SYNC_SELECT_INPUT for mode ALT2)
 
−
|-
 
−
|ALT3
 
−
|SAI1_TX_DATA4
 
−
|-
 
−
|ALT4
 
−
|CORESIGHT_TRACE7
 
−
|-
 
−
|ALT5
 
−
|GPIO4_IO09
 
−
|-
 
−
|ALT6
 
−
|SRC_BOOT_CFG7
 
−
|-
 
−
| rowspan="6" |J1.180
 
−
| rowspan="6" |SAI1_RXD6
 
−
| rowspan="6" |CPU.SAI1_RXD6
 
−
| rowspan="6" |AG19
 
−
| rowspan="6" |NVCC_3V3
 
−
| rowspan="6" |I/O
 
−
| rowspan="6" |Internally used for BOOT mode configuration:
 
−
 
 
−
can be pulled-up or down depending on
 
−
 
 
−
[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
 
−
|ALT0
 
−
|SAI1_RX_DATA6
 
−
|-
 
−
|ALT1
 
−
|SAI6_TX_SYNC
 
−
(Configure register IOMUXC_SAI6_TX_SYNC_SELECT_INPUT for mode ALT1)
 
−
|-
 
−
|ALT2
 
−
|SAI6_RX_SYNC
 
−
(Configure register IOMUXC_SAI6_RX_SYNC_SELECT_INPUT for mode ALT2)
 
−
|-
 
−
|ALT4
 
−
|CORESIGHT_TRACE6
 
−
|-
 
−
|ALT5
 
−
|GPIO4_IO08
 
−
|-
 
−
|ALT6
 
−
|SRC_BOOT_CFG6
 
−
|-
 
−
| rowspan="7" |J1.182
 
−
| rowspan="7" |SAI1_RXD5
 
−
| rowspan="7" |CPU.SAI1_RXD5
 
−
| rowspan="7" |AF18
 
−
| rowspan="7" |NVCC_3V3
 
−
| rowspan="7" |I/O
 
−
| rowspan="7" |Internally used for BOOT mode configuration:
 
−
 
 
−
can be pulled-up or down depending on
 
−
 
 
−
[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
 
−
|ALT0
 
−
|SAI1_RX_DATA5
 
−
|-
 
−
|ALT1
 
−
|SAI6_TX_DATA0
 
−
|-
 
−
|ALT2
 
−
|SAI6_RX_DATA0
 
−
(Configure register IOMUXC_SAI6_RX_DATA_SELECT_INPUT_0 for mode ALT2)
 
−
|-
 
−
|ALT3
 
−
|SAI1_RX_SYNC
 
−
(Configure register IOMUXC_SAI1_RX_SYNC_SELECT_INPUT for mode ALT3)
 
−
|-
 
−
|ALT4
 
−
|CORESIGHT_TRACE5
 
−
|-
 
−
|ALT5
 
−
|GPIO4_IO07
 
−
|-
 
−
|ALT6
 
−
|SRC_BOOT_CFG
 
−
|-
 
−
| rowspan="6" |J1.184
 
−
| rowspan="6" |SAI1_RXD4
 
−
| rowspan="6" |CPU.SAI1_RXD4
 
−
| rowspan="6" |AG18
 
−
| rowspan="6" |NVCC_3V3
 
−
| rowspan="6" |I/O
 
−
| rowspan="6" |Internally used for BOOT mode configuration:
 
−
 
 
−
can be pulled-up or down depending on
 
−
 
 
−
[[MITO 8M Mini SOM/Part number composition|MITO 8M Mini SOM P/N composition]]
 
−
|ALT0
 
−
|SAI1_RX_DATA4
 
−
|-
 
−
|ALT1
 
−
|SAI1_RX_DATA4
 
−
(Configure register IOMUXC_SAI6_TX_BCLK_SELECT_INPUT for mode ALT1)
 
−
|-
 
−
|ALT2
 
−
|SAI6_RX_BCLK
 
−
(Configure register IOMUXC_SAI6_RX_BCLK_SELECT_INPUT for mode ALT2)
 
−
|-
 
−
|ALT4
 
−
|CORESIGHT_TRACE4
 
−
|-
 
−
|ALT5
 
−
|GPIO4_IO06
 
−
|-
 
−
|ALT6
 
−
|SRC_BOOT_CFG4
 
−
|-
 
−
|J1.186
 
−
|USB1_VBUS
 
−
|CPU.USB1_VBUS
 
−
|F22
 
 
|
 
|
−
|S
 
−
|Connected with 30K resistor on SOM.
 
−
See IMX8MM datasheet for 5V tolerance info.
 
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.188
+
|J1.200
−
|USB2_VBUS
+
|USB2_DP
−
|CPU.USB2_VBUS
+
|CPU.USB2_DP
−
|F23
+
|A10
−
|
 
−
|S
 
−
|Connected with 30K resistor on SOM.
 
−
See IMX8MM datasheet for 5V tolerance info.
 
−
|
 
−
|
 
−
|-
 
−
|J1.190
 
−
|DGND
 
−
|DGND
 
 
| -
 
| -
−
|<nowiki>-</nowiki>
+
|D
−
|G
 
 
|
 
|
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.192
+
|J1.202
−
|USB1_ID
+
|USB2_DN
−
|CPU.USB1_ID
+
|CPU.USB2_DN
−
|D22
+
|B10
−
|VDDA_1V8
 
−
|I
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J1.194
 
−
|USB2_ID
 
−
|CPU.USB2_ID
 
−
|D23
 
−
|VDDA_1V8
 
−
|I
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J1.196
 
−
|USB1_DN
 
−
|CPU.USB1_DN
 
−
|A22
 
−
| -
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J1.198
 
−
|USB1_DP
 
−
|CPU.USB1_DP
 
−
|B22
 
−
| -
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J1.200
 
−
|USB2_DP
 
−
|CPU.USB2_DP
 
−
|B23
 
−
| -
 
−
|D
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
|J1.202
 
−
|USB2_DN
 
−
|CPU.USB2_DN
 
−
|A23
 
 
| -
 
| -
 
|D
 
|D
Line 3,654: Line 2,986:
 
|-
 
|-
 
|}
 
|}
−
'''(*)''' PMIC_PWRON can be used in two configuration: ''Embedded-like'' (default mounting option) or ''Tablet-like''. In the first case, the system reboots in case of PMIC_PWR_ON signal activity.
 
−
 
−
In the second case, the system will shut down waiting for a CPU_ONOFF signal raising (like a button-mode in a tablet) and the PMIC_PWRON Voltage domain is NVCC_SNVS_1V8
 
  
−
Please contact [mailto:sales@dave.eu sales dept.] for more information
 
 
----
 
----
  
 
[[Category:MITO 8M Mini]]
 
[[Category:MITO 8M Mini]]
−
[[Category:MITO 8M Nano]]
 

Revision as of 14:56, 29 December 2020

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History
Version Issue Date Notes
1.0.0 Dec 2020 First release


Connectors and Pinout Table description[edit | edit source]

Connectors description[edit | edit source]

In the following table are described all available connectors integrated on MITO 8M Mini SOM:

Connector name Connector Type Notes Carrier board counterpart
J1 SODIMM edge connector 204 pin partially compatible with AXEL Lite SOM TE Connectivity 2-2013289-1

The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to MITO 8M Mini pinout specifications. See the images below for reference:

MITO 8M TOP view
MITO 8M BOTTOM view

Below a detailed description of the pinout, grouped in the following tables:

  • two tables (ODD and EVEN pins) that report the pin mapping of the 204-pin SO-DIMM edge

Pinout Table description[edit | edit source]

Each row in the pinout tables contains the following information:

Pin Reference to the connector pin
Pin Name Pin (signal) name on the MITO 8M connectors
Internal
connections 		Connections to the components
  • CPU.<x> : pin connected to CPU pad named <x>
  • PMIC.<x> : pin connected to the Power Manager IC (NXP PF4210)
  • LAN.<x> : pin connected to the LAN PHY (MICROCHIP KSZ9031RNX)
  • BRIDGE.<x>  : pin connected to the MIPI-to-LVDS bridge (TI SN65DSI84)
Ball/pin # Component ball/pin number connected to signal
Voltage I/O voltage levels
Type Pin type:
  • I = Input
  • O = Output
  • D = Differential
  • Z = High impedance
  • S = Power supply voltage
  • G = Ground
  • A = Analog signal
Notes Remarks on special pin characteristics
Pin MUX alternative functions Muxes:
  • Pin ALT-0
  • Pin ALT-1
  • Pin ALT-2
  • Pin ALT-3
  • Pin ALT-4
  • Pin ALT-5
  • Pin ALT-6
  • Pin ALT-7
  • Pin ALT-8

SODIMM J1 ODD pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage domain Type Notes Alternative Functions
J1.1 DGND DGND - - G
J1.3 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.5 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.7 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.9 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.11 DGND DGND - - G
J1.13 ETH0_LED1 LAN.LED1/PME_N1 17 NVCC_1V8 I/O Must be level translated if used @ 3V3

Internally pulled-up to 1.8V during bootstrap

J1.15 ETH0_LED2 LAN.LED2 15 NVCC_1V8 I/O Must be level translated if used @ 3V3

Internally pulled-up to 1.8V during bootstrap

J1.17 DGND DGND - - G
J1.19 ETH0_TXRX0_P LAN.TXRXP_A 2 - D
J1.21 ETH0_TXRX0_M LAN.TXRXM_A 3 - D
J1.23 ETH0_TXRX1_P LAN.TXRXP_B 5 - D
J1.25 ETH0_TXRX1_M LAN.TXRXM_B 6 - D
J1.27 ETH0_TXRX2_P LAN.TXRXP_C 7 - D
J1.29 ETH0_TXRX2_M LAN.TXRXM_C 8 - D
J1.31 ETH0_TXRX3_P LAN.TXRXP_D 10 - D
J1.33 ETH0_TXRX3_M LAN.TXRXM_D 11 - D
J1.35 DGND DGND - - G
J1.37 GPIO1_IO00 CPU.GPIO1_IO00 T6 NVCC_3V3 I/O ALT0 GPIO1_IO00
ALT1 CCM_ENET_PHY_REF_CLK_ROOT
ALT5 ANAMIX_REF_CLK_32K
ALT6 CCM_EXT_CLK1
J1.39 GPIO1_IO01 CPU.GPIO1_IO01 T7 NVCC_3V3 I/O Internally used for ETH PHY reset, do not connect ALT0 GPIO1_IO01
ALT1 PWM1_OUT
ALT5 ANAMIX_REF_CLK_25M
ALT6 CCM_EXT_CLK2
J1.41 SPDIF_EXT_CLK CPU.SPDIF_EXT_CLK E6 NVCC_3V3 I/O ALT0 SPDIF1_EXT_CLK
ALT1 PWM1_OUT
ALT5 GPIO5_IO05
J1.43 GPIO1_IO13 CPU.GPIO1_IO13 K6 NVCC_3V3 I/O Internally used, do not connect ALT0 GPIO1_IO13
ALT1 USB1_OTG_OC
ALT5 PWM2_OUT
J1.45 VDD_PHY_1V8
J1.47 ECSPI2_SCLK CPU.ECSPI2_SCLK C5 NVCC_3V3 I/O ALT0 ECSPI2_SCLK
ALT1 UART4_RX
ALT5 GPIO5_IO10
J1.49 ECSPI2_MOSI CPU.ECSPI2_MOSI E5 NVCC_3V3 I/O ALT0 ECSPI2_MOSI
ALT1 UART4_TX
ALT5 GPIO5_IO11
J1.51 GPIO1_IO08 CPU.GPIO1_IO08 N7 NVCC_3V3 I/O ALT0 GPIO1_IO08
ALT1 ENET1_1588_EVENT0_IN
ALT5 USDHC2_RESET_B
J1.53 GPIO1_IO09 CPU.GPIO1_IO09 M7 NVCC_3V3 I/O ALT0 GPIO1_IO09
ALT1 ENET1_1588_EVENT0_OUT
ALT5 SDMA2_EXT_EVENT0
J1.55 ECSPI2_MISO CPU.ECSPI2_MISO B5 NVCC_3V3 I/O ALT0 ECSPI2_MISO
ALT1 UART4_CTS_B
ALT5 GPIO5_IO12
J1.57 DGND DGND - - G
J1.59 ECSPI2_SS0 CPU.ECSPI2_SS0 A5 NVCC_3V3 I/O ALT0 ECSPI2_SS0
ALT1 UART4_RTS_B
ALT5 GPIO5_IO13
J1.61 GPIO1_IO05 CPU.GPIO1_IO05 P7 NVCC_3V3 I/O Internally used for MIPI-to-LVDS interrupt, do not connect

Pulled-up to NVCC_3V3

ALT0 GPIO1_IO05
ALT1 M4_NMI
ALT5 CCM_PMIC_READY
J1.63 I2C2_SCL CPU.I2C2_SCL G7 NVCC_3V3 I/O ALT0 I2C2_SCL
ALT1 ENET1_1588_EVENT1_IN
ALT5 GPIO5_IO16
J1.65 I2C2_SDA CPU.I2C2_SDA F7 NVCC_3V3 I/O ALT0 I2C2_SDA
ALT1 ENET1_1588_EVENT1_OUT
ALT5 GPIO5_IO17
J1.67 GPIO1_IO06 CPU.GPIO1_IO06 N5 NVCC_3V3 I/O Internally used for MIPI-to-LVDS enable, do not connect ALT0 GPIO1_IO06
ALT1 ENET1_MDC
ALT5 USDHC1_CD_B
ALT6 CCM_EXT_CLK3
J1.69 SAI2_RXC CPU.SAI2_RXC H3 NVCC_3V3 I/O ALT0 SAI2_RX_BCLK
ALT1 SAI5_TX_BCLK
ALT5 GPIO4_IO22
J1.71 SAI2_RXFS CPU.SAI2_RXFS J4 NVCC_3V3 I/O ALT0 SAI2_RX_SYNC
ALT1 SAI5_TX_SYNC
ALT5 GPIO4_IO21
J1.73 DGND DGND - - G
J1.75 SD2_DATA0 CPU.SD2_DATA0 N22 NVCC_3V3 I/O ALT0 USDHC2_DATA0
ALT5 GPIO2_IO15
J1.77 SD2_DATA1 CPU.SD2_DATA1 N21 NVCC_3V3 I/O ALT0 USDHC2_DATA1
ALT5 GPIO2_IO16
J1.79 SD2_DATA2 CPU.SD2_DATA2 P22 NVCC_3V3 I/O ALT0 USDHC2_DATA2
ALT5 GPIO2_IO17
J1.81 SD2_DATA3 CPU.SD2_DATA03 P21 NVCC_3V3 I/O ALT0 USDHC2_DATA3
ALT5 GPIO2_IO18
J1.83 SD2_CMD CPU.SD2_CMD M22 NVCC_3V3 I/O ALT0 USDHC2_CMD
ALT5 GPIO2_IO14
J1.85 SD2_CLK CPU.SD2_CLK L22 NVCC_3V3 I/O ALT0 USDHC2_CLK
ALT5 GPIO2_IO13
J1.87 DGND DGND - - G
J1.89 UART3_TXD CPU.UART3_TXD B7 NVCC_3V3 I/O ALT0 UART3_TX
ALT1 UART1_RTS_B
ALT5 GPIO5_IO27
J1.91 UART3_RXD CPU.UART3_RXD A6 NVCC_3V3 I/O ALT0 UART3_RX
ALT1 UART1_CTS_B
ALT5 GPIO5_IO26
J1.93 UART4_TXD CPU.UART4_TXD D7 NVCC_3V3 I/O ALT0 UART4_TX
ALT1 UART2_RTS_B
ALT2 PCIE2_CLKREQ_B
ALT5 GPIO5_IO29
J1.95 UART4_RXD CPU.UART4_RXD C6 NVCC_3V3 I/O ALT0 UART4_RX
ALT1 UART2_CTS_B
ALT2 PCIE1_CLKREQ_B
ALT5 GPIO5_IO28
J1.97 SD2_WP CPU.SD2_WP M21 NVCC_3V3 I/O ALT0 USDHC2_WP
ALT5 GPIO2_IO20
J1.99 SD2_RST_B CPU.SD2_RESET_B R22 NVCC_3V3 I/O ALT0 USDHC2_RESET_B
ALT5 GPIO2_IO19
J1.101 HDMI_DDC_SCL CPU.HDMI_DDC_SCL R3 VDD_PHY_1V8 I/O
J1.103 HDMI_DDC_SDA CPU.HDMI_DDC_SDA P3 VDD_PHY_1V8 I/O
J1.105 HDMI_AUX_N CPU.HDMI_AUX_N V2 - D connected with capacitor in series
J1.107 HDMI_AUX_P CPU.HDMI_AUX_P V1 - D connected with capacitor in series
J1.109 DGND DGND - - G
J1.111 HDMI_TX_M_LN_3 CPU.HDMI_TX_M_LN_3 M2 - D connected with capacitor in series
J1.113 HDMI_TX_P_LN_3 CPU.HDMI_TX_P_LN_3 M1 - D connected with capacitor in series
J1.115 HDMI_TX_M_LN_0 CPU.HDMI_TX_M_LN_0 T2 - D connected with capacitor in series
J1.117 HDMI_TX_P_LN_0 CPU.HDMI_TX_P_LN_0 T1 - D connected with capacitor in series
J1.119 HDMI_TX_M_LN_1 CPU.HDMI_TX_M_LN_1 U1 - D connected with capacitor in series
J1.121 HDMI_TX_P_LN_1 CPU.HDMI_TX_P_LN_1 U2 - D connected with capacitor in series
J1.123 HDMI_TX_M_LN_2 CPU.HDMI_TX_M_LN_2 N1 - D connected with capacitor in series
J1.125 HDMI_TX_P_LN_2 CPU.HDMI_TX_P_LN_2 N2 - D connected with capacitor in series
J1.127 HDMI_CEC CPU.HDMI_CEC W3 VDD_PHY_1V8 I/O
J1.129 HDMI_HPD CPU.HDMI_HPD W2 VDD_PHY_1V8 I/O
J1.131 DGND DGND - - G
J1.133 LVDS0_CLK_N BRIDGE.A_CLKN F9 - D
J1.135 LVDS0_CLK_P BRIDGE.A_CLKP F8 - D
J1.137 LVDS0_TX0_N BRIDGE.A_Y0N C9 - D
J1.139 LVDS0_TX0_P BRIDGE.A_Y0P C8 - D
J1.141 LVDS0_TX1_N BRIDGE.A_Y1N D9 - D
J1.143 LVDS0_TX1_P BRIDGE.A_Y1P D8 - D
J1.145 LVDS0_TX2_N BRIDGE.A_Y2N E9 - D
J1.147 LVDS0_TX2_P BRIDGE.A_Y2P E8 - D
J1.149 LVDS0_TX3_N BRIDGE.A_Y3N G9 - D
J1.151 LVDS0_TX3_P BRIDGE.A_Y3P G8 - D
J1.153 DGND DGND - - G
J1.155 LVDS1_CLK_N BRIDGE.B_CLKN A6 - D
J1.157 LVDS1_CLK_P BRIDGE.B_CLKP B6 - D
J1.159 LVDS1_TX0_N BRIDGE.B_Y0N A3 - D
J1.161 LVDS1_TX0_P BRIDGE.B_Y0P B3 - D
J1.163 LVDS1_TX1_N BRIDGE.B_Y1N A4 - D
J1.165 LVDS1_TX1_P BRIDGE.B_Y1P B4 - D
J1.167 LVDS1_TX2_N BRIDGE.B_Y2N A5 - D
J1.169 LVDS1_TX2_P BRIDGE.B_Y2P B5 - D
J1.171 LVDS1_TX3_N BRIDGE.B_Y3N A7 - D
J1.173 LVDS1_TX3_P BRIDGE.B_Y3P B7 - D
J1.175 DGND DGND - - G
J1.177 SD2_CD_B CPU.SD2_CD_B L21 NVCC_3V3 I/O ALT0 USDHC2_CD_B
ALT5 GPIO2_IO12
J1.179 ECSPI1_SS0 CPU.ECSPI1_SS0 D4 NVCC_3V3 I/O ALT0 ECSPI1_SS0
ALT1 UART3_RTS_B
ALT5 GPIO5_IO09
J1.181 ECSPI1_SCLK CPU.ECSPI1_SCLK D5 NVCC_3V3 I/O ALT0 ECSPI1_SCLK
ALT1 UART3_RX
ALT5 GPIO5_IO06
J1.183 ECSPI1_MISO CPU.ECSPI1_MISO B4 NVCC_3V3 I/O ALT0 ECSPI1_MISO
ALT1 UART3_CTS_B
ALT5 GPIO5_IO08
J1.185 GPIO1_IO03 CPU.GPIO1_IO03 P4 NVCC_3V3 I/O ALT0 GPIO1_IO03
ALT1 USDHC1_VSELECT
ALT5 SDMA1_EXT_EVENT0
J1.187 UART2_TXD CPU.UART2_TXD D6 NVCC_3V3 I/O used as default Linux console ALT0 UART2_TX
ALT1 ECSPI3_SS0
ALT5 GPIO5_IO25
J1.189 UART2_RXD CPU.UART2_RXD B6 NVCC_3V3 I/O used as default Linux console ALT0 UART2_RXD
ALT1 ECSPI3_MISO
ALT5 GPIO5_IO24
J1.191 UART1_TXD CPU.UART1_TXD A7 NVCC_3V3 I/O ALT0 UART1_TX
ALT1 ECSPI3_MOSI
ALT5 GPIO5_IO23
J1.193 UART1_RXD CPU.UART1_RXD C7 NVCC_3V3 I/O ALT0 UART1_RXD
ALT1 ECSPI3_SCLK
ALT5 GPIO5_IO22
J1.195 ECSPI1_MOSI CPU.ECSPI1_MOSI A4 NVCC_3V3 I/O ALT0 ECSPI1_MOSI
ALT1 UART3_TX
ALT5 GPIO5_IO07
J1.197 GPIO1_IO14 CPU.GPIO1_IO14 K7 NVCC_3V3 I/O ALT0 GPIO1_IO14
ALT1 USB2_OTG_PWR
ALT5 PWM3_OUT
ALT6 CCM_CLKO1
J1.199 GPIO1_IO04 CPU.GPIO1_IO04 P5 NVCC_3V3 I/O ALT0 GPIO1_IO04
ALT1 USDHC2_VSELECT
ALT5 SDMA1_EXT_EVENT1
J1.201 GPIO1_IO12 CPU.GPIO1_IO12 L7 NVCC_3V3 I/O ALT0 GPIO1_IO12
ALT1 USB1_OTG_PWR
ALT5 SDMA2_EXT_EVENT1
J1.203 DGND DGND - - G

SODIMM J1 EVEN pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage domain Type Notes Alternative Functions
J1.2 DGND DGND - - G
J1.4 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.6 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.8 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.10 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.12 DGND DGND - - G
J1.14 PMIC_LICELL PMIC.LICELL 30 - S
J1.16 CPU_ONOFF CPU.ONOFF W21 NVCC_SNVS I internal pull-up 100k to NVCC_SNVS
J1.18 BOARD_PGOOD - - NVCC_3V3 O
J1.20 BOOT_MODE_SEL BOOT MODE SELECTION - NVCC_3V3 I internal pull-up to NVCC_3V3
J1.22 CPU_PORn CPU.POR_B

PMIC.RESETMCU

W20

3

NVCC_SNVS I/O internal pull-up 100k to NVCC_SNVS
J1.24 EXT_RESET MASTER RESET - - I internal pull-up to NVCC_SNVS
J1.26 SAI3_RXC CPU.SAI3_RXC F4 NVCC_3V3 I/O ALT0 SAI3_RX_BCLK
ALT1 GPT1_CAPTURE2
ALT2 SAI5_RX_BCLK
ALT5 GPIO4_IO29
J1.28 GPIO1_IO02 CPU.GPIO1_IO02 R4 NVCC_3V3 I/O Internally used for SW reset, do not connect ALT0 GPIO1_IO02
ALT1 WDOG1_WDOG_B
ALT5 WDOG1_WDOG_ANY
ALT7 SJC_DE_B
J1.30 DGND DGND - - G
J1.32 SAI3_RXD CPU.SAI3_RXD F3 NVCC_3V3 I/O ALT0 SAI3_RX_DATA0
ALT1 GPT1_COMPARE1
ALT2 SAI5_RX_DATA0
ALT5 GPIO4_IO30
J1.34 SAI2_MCLK CPU.SAI2_MCLK H5 NVCC_3V3 I/O ALT0 SAI2_MCLK
ALT1 SAI5_MCLK
ALT5 GPIO4_IO27
J1.36 SAI3_RXFS CPU.SAI3_RXFS G4 NVCC_3V3 I/O ALT0 SAI3_RX_SYNC
ALT1 GPT1_CAPTURE1
ALT2 SAI5_RX_SYNC
ALT5 GPIO4_IO28
J1.38 I2C3_SCL CPU.I2C3_SCL G8 NVCC_3V3 I/O ALT0 I2C3_SCL
ALT1 PWM4_OUT
ALT2 GPT2_CLK
ALT5 GPIO5_IO18
J1.40 SAI3_TXFS CPU.SAI3_TXFS G3 NVCC_3V3 I/O ALT0 SAI3_TX_SYNC
ALT1 GPT1_CLK
ALT2 SAI5_RX_DATA1
ALT5 GPIO4_IO31
J1.42 SPDIF_RX CPU.SPDIF_RX G6 NVCC_3V3 I/O ALT0 SPDIF1_IN
ALT1 PWM2_OUT
ALT5 GPIO5_IO04
J1.44 SPDIF_TX CPU.SPDIF_TX F6 NVCC_3V3 I/O ALT0 SPDIF1_OUT
ALT1 PWM3_OUT
ALT5 GPIO5_IO03
J1.46 SAI3_MCLK CPU.SAI3_MCLK D3 NVCC_3V3 I/O ALT0 SAI3_MCLK
ALT1 PWM4_OUT
ALT2 SAI5_MCLK
ALT5 GPIO5_IO02
J1.48 I2C3_SDA CPU.I2C3_SDA E9 NVCC_3V3 I/O ALT0 I2C3_SDA
ALT1 PWM3_OUT
ALT2 GPT3_CLK
ALT5 GPIO5_IO19
J1.50 SAI3_TXC CPU.SAI3_TXC C4 NVCC_3V3 I/O ALT0 SAI3_TX_BCLK
ALT1 GPT1_COMPARE2
ALT2 SAI5_RX_DATA2
ALT5 GPIO5_IO00
J1.52 SAI3_TXD CPU.SAI3_TXD C3 NVCC_3V3 I/O ALT0 SAI3_TX_DATA0
ALT1 GPT1_COMPARE3
ALT2 SAI5_RX_DATA3
ALT5 GPIO5_IO01
J1.54 GPIO1_IO10 CPU.GPIO1_IO10 M7 NVCC_3V3 I/O Internally used for ETH PHY interrupt, do not connect ALT0 GPIO1_IO10
ALT1 USB1_OTG_ID
J1.56 DGND DGND - - G
J1.58 SAI5_MCLK CPU.SAI5_MCLK K4 NVCC_3V3 I/O ALT0 SAI5_MCLK
ALT1 SAI1_TX_BCLK
ALT2 SAI4_MCLK
ALT5 GPIO3_IO25
J1.60 GPIO1_IO15 CPU.GPIO1_IO15 J6 NVCC_3V3 I/O ALT0 GPIO1_IO15
ALT1 USB2_OTG_OC
ALT5 PWM4_OUT
ALT6 CCM_CLKO2
J1.62 SAI5_RXFS CPU.SAI5_RXFS N4 NVCC_3V3 I/O ALT0 SAI5_RX_SYNC
ALT1 SAI1_TX_DATA0
ALT5 GPIO3_IO19
J1.64 SAI5_RXC CPU.SAI5_RXC L5 NVCC_3V3 I/O ALT0 SAI5_RX_BCLK
ALT1 SAI1_TX_DATA1
ALT5 GPIO3_IO20
J1.66 SAI2_TXC CPU.SAI2_TXC J5 NVCC_3V3 I/O ALT0 SAI2_TX_BCLK
ALT1 SAI5_TX_DATA2
ALT5 GPIO4_IO25
J1.68 SAI2_TXD0 CPU.SAI2_TXD0 G5 NVCC_3V3 I/O ALT0 SAI2_TX_DATA0
ALT1 SAI5_TX_DATA3
ALT5 GPIO4_IO26
J1.70 SAI2_TXFS CPU.SAI2_TXFS H4 NVCC_3V3 I/O ALT0 SAI2_TX_SYNC
ALT1 SAI5_TX_DATA1
ALT5 GPIO4_IO24
J1.72 SAI2_RXD0 CPU.SAI2_RXD0 H6 NVCC_3V3 I/O ALT0 SAI2_RX_DATA0
ALT1 SAI5_TX_DATA0
ALT5 GPIO4_IO23
J1.74 SAI5_RXD0 CPU.SAI5_RXD0 M5 NVCC_3V3 I/O ALT0 SAI5_RX_DATA0
ALT1 SAI1_TX_DATA2
ALT5 GPIO3_IO21
J1.76 SAI5_RXD1 CPU.SAI5_RXD1 L4 NVCC_3V3 I/O ALT0 SAI5_RX_DATA1
ALT1 SAI1_TX_DATA3
ALT2 SAI1_TX_SYNC
ALT3 SAI5_TX_SYNC
ALT5 GPIO3_IO212
J1.78 SAI5_RXD2 CPU.SAI5_RXD2 M4 NVCC_3V3 I/O ALT0 SAI5_RX_DATA2
ALT1 SAI1_TX_DATA4
ALT2 SAI1_TX_SYNC
ALT3 SAI5_TX_BCLK
ALT5 GPIO3_IO23
J1.80 SAI5_RXD3 CPU.SAI5_RXD3 K5 NVCC_3V3 I/O ALT0 SAI5_RX_DATA3
ALT1 SAI1_TX_DATA5
ALT2 SAI1_TX_SYNC
ALT3 SAI5_TX_DATA0
ALT5 GPIO3_IO24
J1.82 DGND DGND - - G
J1.84 CLK2_N CPU.CLK2_N T22 VDDA_1V8 D Internally used for PCIe CLK, do not connect
J1.86 CLK2_P CPU.CLK2_P U22 VDDA_1V8 D Internally used for PCIe CLK, do not connect
J1.88 PCIE1_REF_CLKN CPU.PCIE1_REF_PAD_CLK_N K24 VDD_PHY_3V3 D
J1.90 PCIE1_REF_CLKP CPU.PCIE1_REF_PAD_CLK_P K25 VDD_PHY_3V3 D
J1.92 PCIE1_RXN CPU.PCIE1_RXN_N H24 VDD_PHY_3V3 D
J1.94 PCIE1_RXP CPU.PCIE1_RXN_P H25 VDD_PHY_3V3 D
J1.96 PCIE1_TXN CPU.PCIE1_TXN_N J24 VDD_PHY_3V3 D
J1.98 PCIE1_TXP CPU.PCIE1_TXN_P J25 VDD_PHY_3V3 D
J1.100 DGND DGND - - G
J1.102 CSI1_CLK_N CPU.MIPI_CSI1_CLK_N A22 - D
J1.104 CSI1_CLK_P CPU.MIPI_CSI1_CLK_P B22 - D
J1.106 CSI1_D0_N CPU.MIPI_CSI1_D0_N A23 - D
J1.108 CSI1_D0_P CPU.MIPI_CSI1_D0_P B23 - D
J1.110 CSI1_D1_N CPU.MIPI_CSI1_D1_N C22 - D
J1.112 CSI1_D1_P CPU.MIPI_CSI1_D1_P D22 - D
J1.114 CSI1_D2_N CPU.MIPI_CSI1_D2_N B24 - D
J1.116 CSI1_D2_P CPU.MIPI_CSI1_D2_P C23 - D
J1.118 CSI1_D3_N CPU.MIPI_CSI1_D3_N C21 - D
J1.120 CSI1_D3_P CPU.MIPI_CSI1_D3_P D21 - D
J1.122 DGND DGND - - G
J1.124

(NAND on board)

NAND_DQS CPU.NAND_DQS M20 NVCC_3V3 I/O Internally used for NAND, do not connect
J1.124

(eMMC on board)

NAND_DQS CPU.NAND_DQS M20 NVCC_3V3 I/O ALT0 RAWNAND_DQS
ALT1 QSPI_A_DQS
ALT5 GPIO3_IO14
J1.126

(NAND on board)

NAND_ALE CPU.NAND_ALE G19 NVCC_3V3 I/O Internally used for NAND, do not connect
J1.126

(eMMC on board)

NAND_ALE CPU.NAND_ALE G19 NVCC_3V3 I/O ALT0 RAWNAND_ALE
ALT1 QSPI_A_SCLK
ALT5 GPIO3_IO00
J1.128

(NAND on board)

SD1_CLK CPU.SD1_CLK L25 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_CLK
ALT5 GPIO2_IO00
J1.128

(eMMC on board)

NAND_CE0_B CPU.NAND_CE0_B H19 NVCC_3V3 I/O ALT0 RAWNAND_CE0_B
ALT1 QSPI_A_SS0_B
ALT5 GPIO3_IO01
J1.130

(NAND on board)

SD1_CMD CPU.SD1_CMD L24 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_CMD
ALT5 GPIO2_IO01
J1.130

(eMMC on board)

NAND_CE1_B CPU.NAND_CE1_B G21 NVCC_3V3 I/O ALT0 RAWNAND_CE1_B
ALT1 QSPI_A_SS1_B
ALT5 GPIO3_IO02
J1.132

(NAND on board)

SD1_RST_B CPU.SD1_RST_B R24 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_RESET_B
ALT5 GPIO2_IO10
J1.132

(eMMC on board)

NAND_CE2_B CPU.NAND_CE2_B F21 NVCC_3V3 I/O ALT0 RAWNAND_CE2_B
ALT1 QSPI_B_SS0_B
ALT5 GPIO3_IO03
J1.134

(NAND on board)

SD1_STROBE CPU.SD1_STROBE T24 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_STROBE
ALT5 GPIO2_IO11
J1.134

(eMMC on board)

NAND_CE3_B CPU.NAND_CE3_B H20 NVCC_3V3 I/O ALT0 RAWNAND_CE3_B
ALT1 QSPI_B_SS1_B
ALT5 GPIO3_IO034
J1.136

(NAND on board)

NAND_CLE CPU.NAND_CLE H21 NVCC_3V3 I/O Internally used for NAND, do not connect
J1.136

(eMMC on board)

NAND_CLE CPU.NAND_CLE H21 NVCC_3V3 I/O ALT0 RAWNAND_CLE
ALT1 QSPI_B_SCLK
ALT5 GPIO3_IO05
J1.138

(NAND on board)

SD1_DATA0 CPU.SD1_DATA0 M25 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_DATA0
ALT5 GPIO2_IO02
J1.138

(eMMC on board)

NAND_DATA00 CPU.NAND_DATA00 G20 NVCC_3V3 I/O ALT0 RAWNAND_DATA00
ALT1 QSPI_A_DATA0
ALT5 GPIO3_IO06
J1.140

(NAND on board)

SD1_DATA1 CPU.SD1_DATA1 M24 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_DATA1
ALT5 GPIO2_IO0
J1.140

(eMMC on board)

NAND_DATA01 CPU.NAND_DATA01 J20 NVCC_3V3 I/O ALT0 RAWNAND_DATA01
ALT1 QSPI_A_DATA1
ALT5 GPIO3_IO07
J1.142

(NAND on board)

SD1_DATA2 CPU.SD1_DATA2 N25 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_DATA2
ALT5 GPIO2_IO04
J1.142

(eMMC on board)

NAND_DATA02 CPU.NAND_DATA02 H22 NVCC_3V3 I/O ALT0 RAWNAND_DATA02
ALT1 QSPI_A_DATA2
ALT5 GPIO3_IO08
J1.144

(NAND on board)

SD1_DATA3 CPU.SD1_DATA3 P25 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_DATA3
ALT5 GPIO2_IO05
J1.144

(eMMC on board)

NAND_DATA03 CPU.NAND_DATA03 J21 NVCC_3V3 I/O ALT0 RAWNAND_DATA03
ALT1 QSPI_A_DATA3
ALT5 GPIO3_IO09
J1.146 DGND DGND - - G
J1.148

(NAND on board)

SD1_DATA4 CPU.SD1_DATA4 N24 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_DATA4
ALT5 GPIO2_IO06
J1.148

(eMMC on board)

NAND_DATA04 CPU.NAND_DATA04 L20 NVCC_3V3 I/O ALT0 RAWNAND_DATA04
ALT1 QSPI_B_DATA0
ALT5 GPIO3_IO10
J1.150

(NAND on board)

SD1_DATA5 CPU.SD1_DATA5 P24 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_DATA5
ALT5 GPIO2_IO07
J1.150

(eMMC on board)

NAND_DATA05 CPU.NAND_DATA05 J22 NVCC_3V3 I/O ALT0 RAWNAND_DATA05
ALT1 QSPI_B_DATA1
ALT5 GPIO3_IO11
J1.152

(NAND on board)

SD1_DATA6 CPU.SD1_DATA6 R25 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_DATA6
ALT5 GPIO2_IO08
J1.152

(eMMC on board)

NAND_DATA06 CPU.NAND_DATA06 L19 NVCC_3V3 I/O ALT0 RAWNAND_DATA06
ALT1 QSPI_B_DATA2
ALT5 GPIO3_IO12
J1.154

(NAND on board)

SD1_DATA7 CPU.SD1_DATA7 T25 NVCC_3V3

(NVCC_1V8 on request)

I/O ALT0 USDHC1_DATA7
ALT5 GPIO2_IO09
J1.154

(eMMC on board)

NAND_DATA07 CPU.NAND_DATA07 M19 NVCC_3V3 I/O ALT0 RAWNAND_DATA07
ALT1 QSPI_B_DATA3
ALT5 GPIO3_IO13
J1.156

(NAND on board)

NAND_RE_B CPU.NAND_RE_B K19 NVCC_3V3 I/O Internally used for NAND, do not connect
J1.156

(eMMC on board)

NAND_RE_B CPU.NAND_RE_B K19 NVCC_3V3 I/O ALT0 RAWNAND_RE_B
ALT1 QSPI_B_DQS
ALT5 GPIO3_IO15
J1.158

(NAND on board)

NAND_READY_B CPU.NAND_READY_B K20 NVCC_3V3 I/O Internally used for NAND, do not connect
J1.158

(eMMC on board)

NAND_READY_B CPU.NAND_READY_B K20 NVCC_3V3 I/O ALT0 RAWNAND_READY_B
ALT5 GPIO3_IO16
J1.160

(NAND on board)

NAND_WE_B CPU.NAND_WE_B K22 NVCC_3V3 I/O Internally used for NAND, do not connect
J1.160

(eMMC on board)

NAND_WE_B CPU.NAND_WE_B K22 NVCC_3V3 I/O ALT0 RAWNAND_WE_B
ALT5 GPIO3_IO17
J1.162

(NAND on board)

NAND_WP_B CPU.NAND_WP_B K21 NVCC_3V3 I/O Internally used for NAND, do not connect
J1.162

(eMMC on board)

NAND_WP_B CPU.NAND_WP_B K21 NVCC_3V3 I/O ALT0 RAWNAND_WP_B
ALT5 GPIO3_IO18
J1.164 DGND DGND - - G
J1.166 CLK1_N CPU.CLK1_N T23 D
J1.168 CLK1_P CPU.CLK1_P R23 D
J1.170 USB2_RXN CPU.USB2_RX_N B8 D
J1.172 USB2_RXP CPU.USB2_RX_P A8 D
J1.174 USB2_TXN CPU.USB2_TX_N B9 D
J1.176 USB2_TXP CPU.USB2_TX_P A9 D
J1.178 USB1_RXN CPU.USB1_RX_N B12 D
J1.180 USB1_RXP CPU.USB1_RX_P A12 D
J1.182 USB1_TXN CPU.USB1_TX_N B13 D
J1.184 USB1_TXP CPU.USB1_TX_P A13 D
J1.186 USB1_VBUS CPU.USB1_VBUS D14 - S
J1.188 USB2_VBUS CPU.USB2_VBUS D9 - S
J1.190 DGND DGND - - G
J1.192 USB1_ID CPU.USB1_ID C14 VDD_PHY_3V3 I
J1.194 USB2_ID CPU.USB2_ID C9 VDD_PHY_3V3 I
J1.196 USB1_DN CPU.USB1_DN B14 - D
J1.198 USB1_DP CPU.USB1_DP A14 - D
J1.200 USB2_DP CPU.USB2_DP A10 - D
J1.202 USB2_DN CPU.USB2_DN B10 - D
J1.204 DGND DGND - - G
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