Difference between revisions of "ETRA SOM/ETRA Hardware/Pinout Table"

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(Add 16 alternate functions for CPU ports (ODD pins))
(22 intermediate revisions by 2 users not shown)
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! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
 
! colspan="4" style="width:100%; text-align:left" ; border-bottom:solid 2px #ededed" |History
 
|-  
 
|-  
 +
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Version
 
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
 
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Issue Date
 
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
 
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#73B2C7; padding:5px; color:white" |Notes
 
|-
 
|-
−
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |{{oldid|13190|2020/12/31}}
+
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |X.Y.Z
−
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |First release
+
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Month Year
 +
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |TBD
 
|-
 
|-
−
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |{{oldid|18542|2023/06/09}}
 
−
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Pinout update
 
 
|-
 
|-
−
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |{{oldid|18979|2023/11/23}}
+
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |[TBD_link X.Y.Z]
−
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Pinout update
+
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |Month Year
 +
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |TBD
 
|-
 
|-
−
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |2023/11/28
+
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |...
−
! style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#ededed; padding:5px; color:#000000" |Add pinmux spreadsheet download
+
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |...
 +
| style="border-left:solid 2px #73B2C7; border-right:solid 2px #73B2C7;border-top:solid 2px #73B2C7; border-bottom:solid 2px #73B2C7; background-color:#edf8fb; padding:5px; color:#000000" |...
 
|-
 
|-
 
|}
 
|}
 +
<section end="History" />
 +
<section begin="Body" />
 +
''TBD:  modificare la tabella seguente con le caratteristiche dei pin del SOM''
 +
 +
''TBD:  modificare le due tabelle ODD e EVEN con la mappa completa dei pins''
 +
 +
'''TBD:  nella tabella naming conventions,  inserire il codice dei vari IC presenti (PMIC, PHY ETH, ecc.)'''
  
−
<section end="History" /><section begin="Body" /><section end="History" /><section begin="Body" />
 
 
==Connectors and Pinout Table==
 
==Connectors and Pinout Table==
  
 
=== Connectors description ===
 
=== Connectors description ===
−
In the following table are described all available connectors integrated on [[ETRA SOM]]:
+
In the following table are described all available connectors integrated on [[ETRA]]:
 
{| class="wikitable"
 
{| class="wikitable"
 
|-
 
|-
Line 39: Line 47:
 
The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to ETRA pinout specifications. See the images below for reference:
 
The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to ETRA pinout specifications. See the images below for reference:
  
−
[[File:ETRA_SOM_-_top_pin1_203.png|500px|thumb|ETRA TOP view|none]]
+
[[File:ETRA-top.png|500px|thumb|ETRA TOP view|none]]
−
[[File:ETRA_SOM_-_bottom_pin2_204.png|500px|thumb|ETRA BOTTOM view|none]]
+
[[File:ETRA-bottom.png|500px|thumb|ETRA BOTTOM view|none]]
  
 
===Pinout table naming conventions ===
 
===Pinout table naming conventions ===
  
−
This chapter contains the pinout description of the ETRA module, grouped in two tables (odd and even pins) that report the pin mapping of the SODIMM-DDR3 edge connector.
+
This chapter contains the pinout description of the ETRA module, grouped in two tables (odd and even pins) that report the pin mapping of the ''TBD: connector type'' ETRA connector.
  
 
Each row in the pinout tables contains the following information:
 
Each row in the pinout tables contains the following information:
Line 92: Line 100:
 
|-
 
|-
 
|}
 
|}
−
 
−
===Pinout table XLS file ===
 
−
For your convenience, please find a spreadsheet with the STM32MP15x pinout and pinmux table [https://www.dave.eu/links/p/2hxFRECdQPg6uJOy here].
 
  
 
==Pinout Table ODD pins declaration ==
 
==Pinout Table ODD pins declaration ==
Line 179: Line 184:
 
|-
 
|-
 
|J1.15
 
|J1.15
−
| VINTLDO
+
| -
−
|PMIC.INTLDO
+
|NC
−
|40
+
| -
−
|INTLDO
+
| -
−
|S
+
| -
−
|do not connect
+
|
 
|
 
|
 
|
 
|
Line 269: Line 274:
 
|-
 
|-
 
|J1.33
 
|J1.33
−
|ETH_INT
+
| -
−
|LAN.INTRP
+
|NC
−
|18
+
| -
−
|VDD
+
| -
−
|O
+
| -
−
|open drain with internal pull-up to VDD
+
|
 
|
 
|
 
|
 
|
Line 288: Line 293:
 
|
 
|
 
|-
 
|-
−
|J1.37
+
| rowspan="16" |J1.37
−
(NAND on board)
+
| rowspan="16" |PD1
−
|PD1
+
| rowspan="16" |CPU.PD1
−
|CPU.PD1
+
| rowspan="16" |A4
−
|A4
+
| rowspan="16" |VDD
−
|VDD
+
| rowspan="16" |I/O
−
|I/O
+
| rowspan="16" |
−
|internally used for NAND flash,
+
|Pin AF0
−
do not connect
+
|TBD
−
|
+
|-
−
|
+
|Pin AF1
 +
|TBD
 
|-
 
|-
−
| rowspan="10" |J1.37
 
−
| rowspan="10" |PD1
 
−
| rowspan="10" |CPU.PD1
 
−
| rowspan="10" |A4
 
−
| rowspan="10" |VDD
 
−
| rowspan="10" |I/O
 
−
| rowspan="10" |
 
 
|Pin AF2
 
|Pin AF2
−
|I2C6_SCL
+
|TBD
 
|-
 
|-
 
|Pin AF3
 
|Pin AF3
−
|DFSDM1_DATIN6
+
|TBD
 
|-
 
|-
 
|Pin AF4
 
|Pin AF4
−
|I2C5_SCL
+
|TBD
 +
|-
 +
|Pin AF5
 +
|TBD
 
|-
 
|-
 
|Pin AF6
 
|Pin AF6
−
|SAI3_SD_A
+
|TBD
 +
|-
 +
|Pin AF7
 +
|TBD
 
|-
 
|-
 
|Pin AF8
 
|Pin AF8
−
|UART4_TX
+
|TBD
 
|-
 
|-
 
|Pin AF9
 
|Pin AF9
−
|FDCAN1_TX
+
|TBD
 
|-
 
|-
 
|Pin AF10
 
|Pin AF10
−
|SDMMC3_D0
+
|TBD
 
|-
 
|-
 
|Pin AF11
 
|Pin AF11
−
|DFSDM1_CKIN7
+
|TBD
 
|-
 
|-
 
|Pin AF12
 
|Pin AF12
−
|FMC_AD3/FMC_D3
+
|TBD
 
|-
 
|-
−
|Pin AF15
+
|Pin AF13
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
|J1.39
+
|Pin AF14
−
(NAND on board)
+
|TBD
−
|PD4
 
−
|CPU.PD4
 
−
|D6
 
−
|VDD
 
−
|I/O
 
−
|internally used for NAND flash,
 
−
do not connect
 
−
|
 
−
|
 
−
|-
 
−
| rowspan="6" |J1.39
 
−
| rowspan="6" |PD4
 
−
| rowspan="6" |CPU.PD4
 
−
| rowspan="6" |D6
 
−
| rowspan="6" |VDD
 
−
| rowspan="6" |I/O
 
−
| rowspan="6" |
 
−
|Pin AF6
 
−
|SAI3_FS_A
 
−
|-
 
−
|Pin AF7
 
−
|USART2_RTS/USART2_DE
 
−
|-
 
−
|Pin AF10
 
−
|SDMMC3_D1
 
−
|-
 
−
|Pin AF11
 
−
|DFSDM1_CKIN0
 
−
|-
 
−
|Pin AF12
 
−
|FMC_NOE
 
 
|-
 
|-
 
|Pin AF15
 
|Pin AF15
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
|J1.41
+
| rowspan="16" |J1.39
−
(NAND on board)
+
| rowspan="16" |PD4
−
|PD5
+
| rowspan="16" |CPU.PD4
−
|CPU.PD5
+
| rowspan="16" |D6
−
|D7
+
| rowspan="16" |VDD
−
|VDD
+
| rowspan="16" |I/O
−
|I/O
+
| rowspan="16" |TBD
−
|internally used for NAND flash,
+
|Pin AF0
−
do not connect
+
|TBD
−
|
 
−
|
 
 
|-
 
|-
−
| rowspan="4" |J1.41
+
|Pin AF1
−
| rowspan="4" |PD5
+
|TBD
−
| rowspan="4" |CPU.PD5
 
−
| rowspan="4" |D7
 
−
| rowspan="4" |VDD
 
−
| rowspan="4" |I/O
 
−
| rowspan="4" |
 
−
|Pin AF7
 
−
|USART2_TX
 
 
|-
 
|-
−
|Pin AF10
+
|Pin AF2
−
|SDMMC3_D2
+
|TBD
−
|-
 
−
|Pin AF12
 
−
|FMC_NWE
 
−
|-
 
−
|Pin AF15
 
−
|EVENTOUT
 
−
|-
 
−
| rowspan="9" |J1.43
 
−
| rowspan="9" |PD7
 
−
| rowspan="9" |CPU.PD7
 
−
| rowspan="9" |B4
 
−
| rowspan="9" |VDD
 
−
| rowspan="9" |I/O
 
−
| rowspan="9" |
 
−
|Pin AF0
 
−
|TRACED6
 
 
|-
 
|-
 
|Pin AF3
 
|Pin AF3
−
|DFSDM1_DATIN4
+
|TBD
 
|-
 
|-
 
|Pin AF4
 
|Pin AF4
−
|I2C2_SCL
+
|TBD
 +
|-
 +
|Pin AF5
 +
|TBD
 
|-
 
|-
 
|Pin AF6
 
|Pin AF6
−
|DFSDM1_CKIN1
+
|TBD
 
|-
 
|-
 
|Pin AF7
 
|Pin AF7
−
|USART2_CK
+
|TBD
 +
|-
 +
|Pin AF8
 +
|TBD
 
|-
 
|-
 
|Pin AF9
 
|Pin AF9
−
|SPDIFRX_IN1
+
|TBD
 
|-
 
|-
 
|Pin AF10
 
|Pin AF10
−
|SDMMC3_D3
+
|TBD
 +
|-
 +
|Pin AF11
 +
|TBD
 
|-
 
|-
 
|Pin AF12
 
|Pin AF12
−
|FMC_NE1
+
|TBD
 +
|-
 +
|Pin AF13
 +
|TBD
 +
|-
 +
|Pin AF14
 +
|TBD
 
|-
 
|-
 
|Pin AF15
 
|Pin AF15
−
|EVENTOUT
+
|TBD
 +
|-
 +
| rowspan="16" |J1.41
 +
| rowspan="16" |PD5
 +
| rowspan="16" |CPU.PD5
 +
| rowspan="16" |D7
 +
| rowspan="16" |VDD
 +
| rowspan="16" |I/O
 +
| rowspan="16" |TBD
 +
|Pin AF0
 +
|TBD
 
|-
 
|-
−
|J1.45
+
|Pin AF1
−
 
+
|TBD
−
(NAND on board)
 
−
|PD0
 
−
|CPU.PD0
 
−
|A3
 
−
|VDD
 
−
|I/O
 
−
|internally used for NAND flash,
 
−
 
 
−
do not connect
 
−
|
 
−
|
 
 
|-
 
|-
−
| rowspan="10" |J1.45
 
−
| rowspan="10" |PD0
 
−
| rowspan="10" |CPU.PD0
 
−
| rowspan="10" |A3
 
−
| rowspan="10" |VDD
 
−
| rowspan="10" |I/O
 
−
| rowspan="10" |
 
 
|Pin AF2
 
|Pin AF2
−
|I2C6_SDA
+
|TBD
 
|-
 
|-
 
|Pin AF3
 
|Pin AF3
−
|DFSDM1_CKIN6
+
|TBD
 
|-
 
|-
 
|Pin AF4
 
|Pin AF4
−
|I2C5_SDA
+
|TBD
 +
|-
 +
|Pin AF5
 +
|TBD
 
|-
 
|-
 
|Pin AF6
 
|Pin AF6
−
|SAI3_SCK_A
+
|TBD
 +
|-
 +
|Pin AF7
 +
|TBD
 
|-
 
|-
 
|Pin AF8
 
|Pin AF8
−
|UART4_RX
+
|TBD
 
|-
 
|-
 
|Pin AF9
 
|Pin AF9
−
|FDCAN1_RX
+
|TBD
 
|-
 
|-
 
|Pin AF10
 
|Pin AF10
−
|SDMMC3_CMD
+
|TBD
 
|-
 
|-
 
|Pin AF11
 
|Pin AF11
−
|DFSDM1_DATIN7
+
|TBD
 
|-
 
|-
 
|Pin AF12
 
|Pin AF12
−
|FMC_AD2/FMC_D2
+
|TBD
 +
|-
 +
|Pin AF13
 +
|TBD
 +
|-
 +
|Pin AF14
 +
|TBD
 
|-
 
|-
 
|Pin AF15
 
|Pin AF15
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
| rowspan="8" |J1.47
+
| rowspan="16" |J1.43
−
| rowspan="8" |PG15
+
| rowspan="16" |PD7
−
| rowspan="8" |CPU.PG15
+
| rowspan="16" |CPU.PD7
−
| rowspan="8" |A2
+
| rowspan="16" |B4
−
| rowspan="8" |VDD
+
| rowspan="16" |VDD
−
| rowspan="8" |I/O
+
| rowspan="16" |I/O
−
| rowspan="8" |
+
| rowspan="16" |TBD
 
|Pin AF0
 
|Pin AF0
−
|TRACED7
+
|TBD
 +
|-
 +
|Pin AF1
 +
|TBD
 
|-
 
|-
 
|Pin AF2
 
|Pin AF2
−
|SAI1_D2
+
|TBD
 +
|-
 +
|Pin AF3
 +
|TBD
 
|-
 
|-
 
|Pin AF4
 
|Pin AF4
−
|I2C2_SDA
+
|TBD
 +
|-
 +
|Pin AF5
 +
|TBD
 
|-
 
|-
 
|Pin AF6
 
|Pin AF6
−
|SAI1_FS_A
+
|TBD
 
|-
 
|-
 
|Pin AF7
 
|Pin AF7
−
|USART6_CTS/USART6_NSS
+
|TBD
 +
|-
 +
|Pin AF8
 +
|TBD
 +
|-
 +
|Pin AF9
 +
|TBD
 
|-
 
|-
 
|Pin AF10
 
|Pin AF10
−
|SDMMC3_CK
+
|TBD
 +
|-
 +
|Pin AF11
 +
|TBD
 +
|-
 +
|Pin AF12
 +
|TBD
 
|-
 
|-
 
|Pin AF13
 
|Pin AF13
−
|DCMI_D13
+
|TBD
 +
|-
 +
|Pin AF14
 +
|TBD
 
|-
 
|-
 
|Pin AF15
 
|Pin AF15
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
|J1.49
+
| rowspan="16" |J1.45
−
(NOR on board)
+
| rowspan="16" |PD0
−
|PF10
+
| rowspan="16" |CPU.PD0
−
|CPU.PF10
+
| rowspan="16" |A3
−
|U9
+
| rowspan="16" |VDD
−
|VDD
+
| rowspan="16" |I/O
−
|I/O
+
| rowspan="16" |TBD
−
|internally used for NOR flash,
+
|Pin AF0
−
do not connect
+
|TBD
−
|
 
−
|
 
 
|-
 
|-
−
| rowspan="9" |J1.49
 
−
| rowspan="9" |PF10
 
−
| rowspan="9" |CPU.PF10
 
−
| rowspan="9" |U9
 
−
| rowspan="9" |VDD
 
−
| rowspan="9" |I/O
 
−
| rowspan="9" |
 
 
|Pin AF1
 
|Pin AF1
−
|TIM16_BKIN
+
|TBD
 
|-
 
|-
 
|Pin AF2
 
|Pin AF2
−
|SAI1_D3
+
|TBD
 
|-
 
|-
 
|Pin AF3
 
|Pin AF3
−
|SAI4_D4
+
|TBD
 +
|-
 +
|Pin AF4
 +
|TBD
 +
|-
 +
|Pin AF5
 +
|TBD
 
|-
 
|-
 
|Pin AF6
 
|Pin AF6
−
|SAI1_D4
+
|TBD
 +
|-
 +
|Pin AF7
 +
|TBD
 +
|-
 +
|Pin AF8
 +
|TBD
 
|-
 
|-
 
|Pin AF9
 
|Pin AF9
−
|QUADSPI_CLK
+
|TBD
 +
|-
 +
|Pin AF10
 +
|TBD
 +
|-
 +
|Pin AF11
 +
|TBD
 
|-
 
|-
 
|Pin AF12
 
|Pin AF12
−
|SAI4_D3
+
|TBD
 
|-
 
|-
 
|Pin AF13
 
|Pin AF13
−
|DCMI_D11
+
|TBD
 
|-
 
|-
 
|Pin AF14
 
|Pin AF14
−
|LCD_DE
+
|TBD
 
|-
 
|-
 
|Pin AF15
 
|Pin AF15
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
|J1.51
+
| rowspan="16" |J1.47
−
(NAND on board)
+
| rowspan="16" |PG15
−
|PE7
+
| rowspan="16" |CPU.PG15
−
|CPU.PE7
+
| rowspan="16" |A2
−
|T10
+
| rowspan="16" |VDD
−
|VDD
+
| rowspan="16" |I/O
−
|I/O
+
| rowspan="16" |TBD
−
|internally used for NAND flash,
+
|Pin AF0
−
do not connect
+
|TBD
−
|
 
−
|
 
 
|-
 
|-
−
| rowspan="7" |J1.51
 
−
| rowspan="7" |PE7
 
−
| rowspan="7" |CPU.PE7
 
−
| rowspan="7" |T10
 
−
| rowspan="7" |VDD
 
−
| rowspan="7" |I/O
 
−
| rowspan="7" |
 
 
|Pin AF1
 
|Pin AF1
−
|TIM1_ETR
+
|TBD
 
|-
 
|-
 
|Pin AF2
 
|Pin AF2
−
|TIM3_ETR
+
|TBD
 
|-
 
|-
 
|Pin AF3
 
|Pin AF3
−
|DFSDM1_DATIN2
+
|TBD
 
|-
 
|-
−
|Pin AF7
+
|Pin AF4
−
|UART7_RX
+
|TBD
 
|-
 
|-
−
|Pin AF10
+
|Pin AF5
−
|QUADSPI_BK2_IO0
+
|TBD
 +
|-
 +
|Pin AF6
 +
|TBD
 +
|-
 +
|Pin AF7
 +
|TBD
 +
|-
 +
|Pin AF8
 +
|TBD
 +
|-
 +
|Pin AF9
 +
|TBD
 +
|-
 +
|Pin AF10
 +
|TBD
 +
|-
 +
|Pin AF11
 +
|TBD
 
|-
 
|-
 
|Pin AF12
 
|Pin AF12
−
|FMC_AD4/FMC_D4
+
|TBD
 +
|-
 +
|Pin AF13
 +
|TBD
 +
|-
 +
|Pin AF14
 +
|TBD
 
|-
 
|-
 
|Pin AF15
 
|Pin AF15
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
|J1.53
+
| rowspan="16" |J1.49
−
(NAND on board)
+
| rowspan="16" |PF10
−
|PE8
+
| rowspan="16" |CPU.PF10
−
|CPU.PE8
+
| rowspan="16" |U9
−
|T11
+
| rowspan="16" |VDD
−
|VDD
+
| rowspan="16" |I/O
−
|I/O
+
| rowspan="16" |TBD
−
|internally used for NAND flash,
+
|Pin AF0
−
do not connect
+
|TBD
−
|
 
−
|
 
 
|-
 
|-
−
| rowspan="6" |J1.53
 
−
| rowspan="6" |PE8
 
−
| rowspan="6" |CPU.PE8
 
−
| rowspan="6" |T11
 
−
| rowspan="6" |VDD
 
−
| rowspan="6" |I/O
 
−
| rowspan="6" |
 
 
|Pin AF1
 
|Pin AF1
−
|TIM1_CH1N
+
|TBD
 +
|-
 +
|Pin AF2
 +
|TBD
 
|-
 
|-
 
|Pin AF3
 
|Pin AF3
−
|DFSDM1_CKIN2
+
|TBD
 +
|-
 +
|Pin AF4
 +
|TBD
 +
|-
 +
|Pin AF5
 +
|TBD
 +
|-
 +
|Pin AF6
 +
|TBD
 
|-
 
|-
 
|Pin AF7
 
|Pin AF7
−
|UART7_TX
+
|TBD
 
|-
 
|-
−
|Pin AF10
+
|Pin AF8
−
|QUADSPI_BK2_IO1
+
|TBD
 
|-
 
|-
−
|Pin AF12
+
|Pin AF9
−
|FMC_AD5/FMC_D5
+
|TBD
 
|-
 
|-
−
|Pin AF15
+
|Pin AF10
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
|J1.55
+
|Pin AF11
−
|NOR_WP#
+
|TBD
−
|NOR.WPn
 
−
|C4
 
−
|VDD
 
−
|I/O
 
−
|internal pull-up to VDD,
 
−
this NOR pin is shared with QSPI_IO2 function
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.57
+
|Pin AF12
−
|DGND
+
|TBD
−
|DGND
 
−
| -
 
−
| -
 
−
|G
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.59
+
|Pin AF13
−
| -
+
|TBD
−
|NC
 
−
| -
 
−
| -
 
−
| -
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.61
+
|Pin AF14
−
(eMMC on board)
+
|TBD
−
|PB14
 
−
|CPU.PB14
 
−
|C9
 
−
|VDD
 
−
|I/O
 
−
|internally used for eMMC flash,
 
−
do not connect
 
−
|
 
−
|
 
 
|-
 
|-
−
| rowspan="9" |J1.61
+
|Pin AF15
−
| rowspan="9" |PB14
+
|TBD
−
| rowspan="9" |CPU.PB14
 
−
| rowspan="9" |C9
 
−
| rowspan="9" |VDD
 
−
| rowspan="9" |I/O
 
−
| rowspan="9" |
 
−
|Pin AF1
 
−
|TIM1_CH2N
 
 
|-
 
|-
−
|Pin AF2
+
| rowspan="16" |J1.51
−
|TIM12_CH1
+
| rowspan="16" |PE7
 +
| rowspan="16" |CPU.PE7
 +
| rowspan="16" |T10
 +
| rowspan="16" |VDD
 +
| rowspan="16" |I/O
 +
| rowspan="16" |TBD
 +
|Pin AF0
 +
|TBD
 +
|-
 +
|Pin AF1
 +
|TBD
 +
|-
 +
|Pin AF2
 +
|TBD
 
|-
 
|-
 
|Pin AF3
 
|Pin AF3
−
|TIM8_CH2N
+
|TBD
 
|-
 
|-
 
|Pin AF4
 
|Pin AF4
−
|USART1_TX
+
|TBD
 
|-
 
|-
 
|Pin AF5
 
|Pin AF5
−
|SPI2_MISO/I2S2_SDI
+
|TBD
 
|-
 
|-
 
|Pin AF6
 
|Pin AF6
−
|DFSDM1_DATIN2
+
|TBD
 
|-
 
|-
 
|Pin AF7
 
|Pin AF7
−
|USART3_RTS/USART3_DE
+
|TBD
 +
|-
 +
|Pin AF8
 +
|TBD
 
|-
 
|-
 
|Pin AF9
 
|Pin AF9
−
|SDMMC2_D0
+
|TBD
 +
|-
 +
|Pin AF10
 +
|TBD
 +
|-
 +
|Pin AF11
 +
|TBD
 +
|-
 +
|Pin AF12
 +
|TBD
 +
|-
 +
|Pin AF13
 +
|TBD
 +
|-
 +
|Pin AF14
 +
|TBD
 
|-
 
|-
 
|Pin AF15
 
|Pin AF15
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
|J1.63
+
| rowspan="16" |J1.53
−
 
+
| rowspan="16" |PE8
−
(eMMC on board)
+
| rowspan="16" |CPU.PE8
−
|PB15
+
| rowspan="16" |T11
−
|CPU.PB15
+
| rowspan="16" |VDD
−
|A8
+
| rowspan="16" |I/O
−
|VDD
+
| rowspan="16" |TBD
−
|I/O
 
−
|internally used for eMMC flash,
 
−
 
 
−
do not connect
 
−
|
 
−
|
 
−
|-
 
−
| rowspan="9" |J1.63
 
−
| rowspan="9" |PB15
 
−
| rowspan="9" |CPU.PB15
 
−
| rowspan="9" |A8
 
−
| rowspan="9" |VDD
 
−
| rowspan="9" |I/O
 
−
| rowspan="9" |
 
 
|Pin AF0
 
|Pin AF0
−
|RTC_REFIN
+
|TBD
 
|-
 
|-
 
|Pin AF1
 
|Pin AF1
−
|TIM1_CH3N
+
|TBD
 
|-
 
|-
 
|Pin AF2
 
|Pin AF2
−
|TIM12_CH2
+
|TBD
 
|-
 
|-
 
|Pin AF3
 
|Pin AF3
−
|TIM8_CH3N
+
|TBD
 
|-
 
|-
 
|Pin AF4
 
|Pin AF4
−
|USART1_RX
+
|TBD
 
|-
 
|-
 
|Pin AF5
 
|Pin AF5
−
|SPI2_MOSI/I2S2_SDO
+
|TBD
 
|-
 
|-
 
|Pin AF6
 
|Pin AF6
−
|DFSDM1_CKIN2
+
|TBD
 +
|-
 +
|Pin AF7
 +
|TBD
 +
|-
 +
|Pin AF8
 +
|TBD
 
|-
 
|-
 
|Pin AF9
 
|Pin AF9
−
|SDMMC2_D1
+
|TBD
 
|-
 
|-
−
|Pin AF15
+
|Pin AF10
−
|EVENTOUT
+
|TBD
−
|-
+
|-
−
|J1.65
+
|Pin AF11
−
 
+
|TBD
−
(eMMC on board)
 
−
|PB3
 
−
|CPU.PB3
 
−
|A7
 
−
|VDD
 
−
|I/O
 
−
|internally used for eMMC flash,
 
−
 
 
−
do not connect
 
−
|
 
−
|
 
−
|-
 
−
| rowspan="10" |J1.65
 
−
| rowspan="10" |PB3
 
−
| rowspan="10" |CPU.PB3
 
−
| rowspan="10" |A7
 
−
| rowspan="10" |VDD
 
−
| rowspan="10" |I/O
 
−
| rowspan="10" |
 
−
|Pin AF0
 
−
|TRACED9
 
−
|-
 
−
|Pin AF1
 
−
|TIM2_CH2
 
−
|-
 
−
|Pin AF4
 
−
|SAI4_CK1
 
−
|-
 
−
|Pin AF5
 
−
|SPI1_SCK/I2S1_CK
 
−
|-
 
−
|Pin AF6
 
−
|SPI3_SCK/I2S3_CK
 
−
|-
 
−
|Pin AF8
 
−
|SPI6_SCK
 
−
|-
 
−
|Pin AF9
 
−
|SDMMC2_D2
 
 
|-
 
|-
 
|Pin AF12
 
|Pin AF12
−
|SAI4_MCLK_A
+
|TBD
 
|-
 
|-
 
|Pin AF13
 
|Pin AF13
−
|UART7_RX
+
|TBD
 +
|-
 +
|Pin AF14
 +
|TBD
 
|-
 
|-
 
|Pin AF15
 
|Pin AF15
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
|J1.67
+
|J1.55
−
 
+
| -
−
(eMMC on board)
+
|NC
−
|PB4
+
| -
−
|CPU.PB4
+
| -
−
|B9
+
| -
−
|VDD
+
|
−
|I/O
 
−
|internally used for eMMC flash,
 
−
 
 
−
do not connect
 
 
|
 
|
 
|
 
|
 
|-
 
|-
−
| rowspan="12" |J1.67
+
|J1.57
−
| rowspan="12" |PB4
+
|DGND
−
| rowspan="12" |CPU.PB4
+
|DGND
−
| rowspan="12" |B9
+
| -
−
| rowspan="12" |VDD
+
| -
−
| rowspan="12" |I/O
+
|G
−
| rowspan="12" |
+
|
−
|Pin AF0
+
|
−
|TRACED8
+
|
 +
|-
 +
|J1.59
 +
| -
 +
|NC
 +
| -
 +
| -
 +
| -
 +
|
 +
|
 +
|
 +
|-
 +
| rowspan="16" |J1.61
 +
| rowspan="16" |PB14
 +
| rowspan="16" |CPU.PB14
 +
| rowspan="16" |C9
 +
| rowspan="16" |VDD
 +
| rowspan="16" |I/O
 +
| rowspan="16" |TBD
 +
|Pin AF0
 +
|TBD
 
|-
 
|-
 
|Pin AF1
 
|Pin AF1
−
|TIM16_BKIN
+
|TBD
 
|-
 
|-
 
|Pin AF2
 
|Pin AF2
−
|TIM3_CH1
+
|TBD
 +
|-
 +
|Pin AF3
 +
|TBD
 
|-
 
|-
 
|Pin AF4
 
|Pin AF4
−
|SAI4_CK2
+
|TBD
 
|-
 
|-
 
|Pin AF5
 
|Pin AF5
−
|SPI1_MISO/I2S1_SDI
+
|TBD
 
|-
 
|-
 
|Pin AF6
 
|Pin AF6
−
|SPI3_MISO/I2S3_SDI
+
|TBD
 
|-
 
|-
 
|Pin AF7
 
|Pin AF7
−
|SPI2_NSS/I2S2_WS
+
|TBD
 
|-
 
|-
 
|Pin AF8
 
|Pin AF8
−
|SPI6_MISO
+
|TBD
 
|-
 
|-
 
|Pin AF9
 
|Pin AF9
−
|SDMMC2_D3
+
|TBD
 +
|-
 +
|Pin AF10
 +
|TBD
 +
|-
 +
|Pin AF11
 +
|TBD
 
|-
 
|-
 
|Pin AF12
 
|Pin AF12
−
|SAI4_SCK_A
+
|TBD
 
|-
 
|-
 
|Pin AF13
 
|Pin AF13
−
|UART7_TX
+
|TBD
 +
|-
 +
|Pin AF14
 +
|TBD
 
|-
 
|-
 
|Pin AF15
 
|Pin AF15
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
|J1.69
+
| rowspan="16" |J1.63
−
(eMMC on board)
+
| rowspan="16" |PB15
−
|PG6
+
| rowspan="16" |CPU.PB15
−
|CPU.PG6
+
| rowspan="16" |A8
−
|A6
+
| rowspan="16" |VDD
−
|VDD
+
| rowspan="16" |I/O
−
|I/O
+
| rowspan="16" |TBD
−
|internally used for eMMC flash,
+
|Pin AF0
−
 
+
|TBD
−
do not connect
+
|-
−
|
+
|Pin AF1
−
|
+
|TBD
 +
|-
 +
|Pin AF2
 +
|TBD
 
|-
 
|-
−
| rowspan="6" |J1.69
+
|Pin AF3
−
| rowspan="6" |PG6
+
|TBD
−
| rowspan="6" |CPU.PG6
 
−
| rowspan="6" |A6
 
−
| rowspan="6" |VDD
 
−
| rowspan="6" |I/O
 
−
| rowspan="6" |
 
−
|Pin AF0
 
−
|TRACED14
 
 
|-
 
|-
−
|Pin AF1
+
|Pin AF4
−
|TIM17_BKIN
+
|TBD
 
|-
 
|-
−
|Pin AF10
+
|Pin AF5
−
|SDMMC2_CMD
+
|TBD
 
|-
 
|-
−
|Pin AF13
+
|Pin AF6
−
|DCMI_D12
+
|TBD
 
|-
 
|-
−
|Pin AF14
+
|Pin AF7
−
|LCD_R7
+
|TBD
 
|-
 
|-
−
|Pin AF15
+
|Pin AF8
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
|J1.71
+
|Pin AF9
−
(eMMC on board)
+
|TBD
−
|PE3
 
−
|CPU.PE3
 
−
|A5
 
−
|VDD
 
−
|I/O
 
−
|internally used for eMMC flash,
 
−
 
 
−
do not connect
 
−
|
 
−
|
 
 
|-
 
|-
−
| rowspan="6" |J1.71
+
|Pin AF10
−
| rowspan="6" |PE3
+
|TBD
−
| rowspan="6" |CPU.PE3
 
−
| rowspan="6" |A5
 
−
| rowspan="6" |VDD
 
−
| rowspan="6" |I/O
 
−
| rowspan="6" |
 
−
|Pin AF0
 
−
|TRACED0
 
 
|-
 
|-
−
|Pin AF4
+
|Pin AF11
−
|TIM15_BKIN
+
|TBD
 
|-
 
|-
−
|Pin AF6
+
|Pin AF12
−
|SAI1_SD_B
+
|TBD
 
|-
 
|-
−
|Pin AF9
+
|Pin AF13
−
|SDMMC2_CK
+
|TBD
 
|-
 
|-
−
|Pin AF12
+
|Pin AF14
−
|FMC_A19
+
|TBD
 
|-
 
|-
 
|Pin AF15
 
|Pin AF15
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
|J1.73
+
| rowspan="16" |J1.65
−
|DGND
+
| rowspan="16" |PB3
−
|DGND
+
| rowspan="16" |CPU.PB3
−
| -
+
| rowspan="16" |A7
−
| -
+
| rowspan="16" |VDD
−
|G
+
| rowspan="16" |I/O
−
|
+
| rowspan="16" |TBD
−
|
+
|Pin AF0
−
|
+
|TBD
 
|-
 
|-
−
| rowspan="9" |J1.75
+
|Pin AF1
−
| rowspan="9" |PC8
+
|TBD
−
| rowspan="9" |CPU.PC8
 
−
| rowspan="9" |C11
 
−
| rowspan="9" |VDD
 
−
| rowspan="9" |I/O
 
−
| rowspan="9" |
 
−
|Pin AF0
 
−
|TRACED0
 
 
|-
 
|-
 
|Pin AF2
 
|Pin AF2
−
|TIM3_CH3
+
|TBD
 
|-
 
|-
 
|Pin AF3
 
|Pin AF3
−
|TIM8_CH3
+
|TBD
 +
|-
 +
|Pin AF4
 +
|TBD
 +
|-
 +
|Pin AF5
 +
|TBD
 
|-
 
|-
 
|Pin AF6
 
|Pin AF6
−
|UART4_TX
+
|TBD
 
|-
 
|-
 
|Pin AF7
 
|Pin AF7
−
|USART6_CK
+
|TBD
 
|-
 
|-
 
|Pin AF8
 
|Pin AF8
−
|UART5_RTS/UART5_DE
+
|TBD
 +
|-
 +
|Pin AF9
 +
|TBD
 +
|-
 +
|Pin AF10
 +
|TBD
 +
|-
 +
|Pin AF11
 +
|TBD
 
|-
 
|-
 
|Pin AF12
 
|Pin AF12
−
|SDMMC1_D0
+
|TBD
 
|-
 
|-
 
|Pin AF13
 
|Pin AF13
−
|DCMI_D2
+
|TBD
 +
|-
 +
|Pin AF14
 +
|TBD
 
|-
 
|-
 
|Pin AF15
 
|Pin AF15
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
| rowspan="11" |J1.77
+
| rowspan="16" |J1.67
−
| rowspan="11" |PC9
+
| rowspan="16" |PB4
−
| rowspan="11" |CPU.PC9
+
| rowspan="16" |CPU.PB4
−
| rowspan="11" |A10
+
| rowspan="16" |B9
−
| rowspan="11" |VDD
+
| rowspan="16" |VDD
−
| rowspan="11" |I/O
+
| rowspan="16" |I/O
−
| rowspan="11" |
+
| rowspan="16" |TBD
 
|Pin AF0
 
|Pin AF0
−
|TRACED1
+
|TBD
 +
|-
 +
|Pin AF1
 +
|TBD
 
|-
 
|-
 
|Pin AF2
 
|Pin AF2
−
|TIM3_CH4
+
|TBD
 
|-
 
|-
 
|Pin AF3
 
|Pin AF3
−
|TIM8_CH4
+
|TBD
 
|-
 
|-
 
|Pin AF4
 
|Pin AF4
−
|I2C3_SDA
+
|TBD
 
|-
 
|-
 
|Pin AF5
 
|Pin AF5
−
|I2S_CKIN
+
|TBD
 +
|-
 +
|Pin AF6
 +
|TBD
 +
|-
 +
|Pin AF7
 +
|TBD
 
|-
 
|-
 
|Pin AF8
 
|Pin AF8
−
|UART5_CTS
+
|TBD
 
|-
 
|-
 
|Pin AF9
 
|Pin AF9
−
|QUADSPI_BK1_IO0
+
|TBD
 +
|-
 +
|Pin AF10
 +
|TBD
 +
|-
 +
|Pin AF11
 +
|TBD
 
|-
 
|-
 
|Pin AF12
 
|Pin AF12
−
|SDMMC1_D1
+
|TBD
 
|-
 
|-
 
|Pin AF13
 
|Pin AF13
−
|DCMI_D3
+
|TBD
 
|-
 
|-
 
|Pin AF14
 
|Pin AF14
−
|LCD_B2
+
|TBD
 
|-
 
|-
 
|Pin AF15
 
|Pin AF15
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
| rowspan="13" |J1.79
+
| rowspan="16" |J1.69
−
| rowspan="13" |PE6
+
| rowspan="16" |PG6
−
| rowspan="13" |CPU.PE6
+
| rowspan="16" |CPU.PG6
−
| rowspan="13" |B3
+
| rowspan="16" |A6
−
| rowspan="13" |VDD
+
| rowspan="16" |VDD
−
| rowspan="13" |I/O
+
| rowspan="16" |I/O
−
| rowspan="13" |for LCD_G1 function
+
| rowspan="16" |TBD
−
use pin J1.180
 
−
 
 
−
(RGB lenght match)
 
 
|Pin AF0
 
|Pin AF0
−
|TRACED2
+
|TBD
 
|-
 
|-
 
|Pin AF1
 
|Pin AF1
−
|TIM1_BKIN2
+
|TBD
 
|-
 
|-
 
|Pin AF2
 
|Pin AF2
−
|SAI1_D1
+
|TBD
 +
|-
 +
|Pin AF3
 +
|TBD
 
|-
 
|-
 
|Pin AF4
 
|Pin AF4
−
|TIM15_CH2
+
|TBD
 
|-
 
|-
 
|Pin AF5
 
|Pin AF5
−
|SPI4_MOSI
+
|TBD
 
|-
 
|-
 
|Pin AF6
 
|Pin AF6
−
|SAI1_SD_A
+
|TBD
 
|-
 
|-
 
|Pin AF7
 
|Pin AF7
−
|SDMMC2_D0
+
|TBD
 
|-
 
|-
 
|Pin AF8
 
|Pin AF8
−
|SDMMC1_D2
+
|TBD
 +
|-
 +
|Pin AF9
 +
|TBD
 
|-
 
|-
 
|Pin AF10
 
|Pin AF10
−
|SAI2_MCLK_B
+
|TBD
 +
|-
 +
|Pin AF11
 +
|TBD
 
|-
 
|-
 
|Pin AF12
 
|Pin AF12
−
|FMC_A22
+
|TBD
 
|-
 
|-
 
|Pin AF13
 
|Pin AF13
−
|DCMI_D7
+
|TBD
 
|-
 
|-
−
|<s>Pin AF14</s>
+
|Pin AF14
−
|<s>LCD_G1</s>
+
|TBD
 
|-
 
|-
 
|Pin AF15
 
|Pin AF15
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
| rowspan="10" |J1.81
+
| rowspan="16" |J1.71
−
| rowspan="10" |PC11
+
| rowspan="16" |PE3
−
| rowspan="10" |CPU.PC11
+
| rowspan="16" |CPU.PE3
−
| rowspan="10" |A11
+
| rowspan="16" |A5
−
| rowspan="10" |VDD
+
| rowspan="16" |VDD
−
| rowspan="10" |I/O
+
| rowspan="16" |I/O
−
| rowspan="10" |
+
| rowspan="16" |TBD
 
|Pin AF0
 
|Pin AF0
−
|TRACED3
+
|TBD
 +
|-
 +
|Pin AF1
 +
|TBD
 +
|-
 +
|Pin AF2
 +
|TBD
 
|-
 
|-
 
|Pin AF3
 
|Pin AF3
−
|DFSDM1_DATIN5
+
|TBD
 +
|-
 +
|Pin AF4
 +
|TBD
 +
|-
 +
|Pin AF5
 +
|TBD
 
|-
 
|-
 
|Pin AF6
 
|Pin AF6
−
|SPI3_MISO/I2S3_SDI
+
|TBD
 
|-
 
|-
 
|Pin AF7
 
|Pin AF7
−
|USART3_RX
+
|TBD
 
|-
 
|-
 
|Pin AF8
 
|Pin AF8
−
|UART4_RX
+
|TBD
 
|-
 
|-
 
|Pin AF9
 
|Pin AF9
−
|QUADSPI_BK2_NCS
+
|TBD
 
|-
 
|-
 
|Pin AF10
 
|Pin AF10
−
|SAI4_SCK_B
+
|TBD
 +
|-
 +
|Pin AF11
 +
|TBD
 
|-
 
|-
 
|Pin AF12
 
|Pin AF12
−
|SDMMC1_D3
+
|TBD
 
|-
 
|-
 
|Pin AF13
 
|Pin AF13
−
|DCMI_D4
+
|TBD
 +
|-
 +
|Pin AF14
 +
|TBD
 
|-
 
|-
 
|Pin AF15
 
|Pin AF15
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
| rowspan="7" |J1.83
+
|J1.73
−
| rowspan="7" |PD2
+
|DGND
−
| rowspan="7" |CPU.PD2
+
|DGND
−
| rowspan="7" |B10
+
| -
−
| rowspan="7" |VDD
+
| -
−
| rowspan="7" |I/O
+
|G
−
| rowspan="7" |
+
|
−
|Pin AF2
+
|
−
|TIM3_ETR
+
|
−
|-
+
|-
−
|Pin AF4
+
| rowspan="16" |J1.75
−
|I2C5_SMBA
+
| rowspan="16" |PC8
 +
| rowspan="16" |CPU.PC8
 +
| rowspan="16" |C11
 +
| rowspan="16" |VDD
 +
| rowspan="16" |I/O
 +
| rowspan="16" |TBD
 +
|Pin AF0
 +
|TBD
 +
|-
 +
|Pin AF1
 +
|TBD
 +
|-
 +
|Pin AF2
 +
|TBD
 +
|-
 +
|Pin AF3
 +
|TBD
 +
|-
 +
|Pin AF4
 +
|TBD
 +
|-
 +
|Pin AF5
 +
|TBD
 
|-
 
|-
 
|Pin AF6
 
|Pin AF6
−
|UART4_RX
+
|TBD
 +
|-
 +
|Pin AF7
 +
|TBD
 
|-
 
|-
 
|Pin AF8
 
|Pin AF8
−
|UART5_RX
+
|TBD
 +
|-
 +
|Pin AF9
 +
|TBD
 +
|-
 +
|Pin AF10
 +
|TBD
 +
|-
 +
|Pin AF11
 +
|TBD
 
|-
 
|-
 
|Pin AF12
 
|Pin AF12
−
|SDMMC1_CMD
+
|TBD
 
|-
 
|-
 
|Pin AF13
 
|Pin AF13
−
|DCMI_D11
+
|TBD
 +
|-
 +
|Pin AF14
 +
|TBD
 
|-
 
|-
 
|Pin AF15
 
|Pin AF15
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
| rowspan="10" |J1.85
+
| rowspan="16" |J1.77
−
| rowspan="10" |PC12
+
| rowspan="16" |PC9
−
| rowspan="10" |CPU.PC12
+
| rowspan="16" |CPU.PC9
−
| rowspan="10" |C10
+
| rowspan="16" |A10
−
| rowspan="10" |VDD
+
| rowspan="16" |VDD
−
| rowspan="10" |I/O
+
| rowspan="16" |I/O
−
| rowspan="10" |
+
| rowspan="16" |TBD
 
|Pin AF0
 
|Pin AF0
−
|TRACECLK
+
|TBD
 
|-
 
|-
 
|Pin AF1
 
|Pin AF1
−
|MCO2
+
|TBD
 
|-
 
|-
 
|Pin AF2
 
|Pin AF2
−
|SAI4_D3
+
|TBD
 +
|-
 +
|Pin AF3
 +
|TBD
 +
|-
 +
|Pin AF4
 +
|TBD
 +
|-
 +
|Pin AF5
 +
|TBD
 
|-
 
|-
 
|Pin AF6
 
|Pin AF6
−
|SPI3_MOSI/I2S3_SDO
+
|TBD
 
|-
 
|-
 
|Pin AF7
 
|Pin AF7
−
|USART3_CK
+
|TBD
 
|-
 
|-
 
|Pin AF8
 
|Pin AF8
−
|UART5_TX
+
|TBD
 +
|-
 +
|Pin AF9
 +
|TBD
 
|-
 
|-
 
|Pin AF10
 
|Pin AF10
−
|SAI4_SD_B
+
|TBD
 +
|-
 +
|Pin AF11
 +
|TBD
 
|-
 
|-
 
|Pin AF12
 
|Pin AF12
−
|SDMMC1_CK
+
|TBD
 
|-
 
|-
 
|Pin AF13
 
|Pin AF13
−
|DCMI_D9
+
|TBD
 +
|-
 +
|Pin AF14
 +
|TBD
 
|-
 
|-
 
|Pin AF15
 
|Pin AF15
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
|J1.87
+
| rowspan="16" |J1.79
−
|DGND
+
| rowspan="16" |PE6
−
|DGND
+
| rowspan="16" |CPU.PE6
−
| -
+
| rowspan="16" |B3
−
| -
+
| rowspan="16" |VDD
−
|G
+
| rowspan="16" |I/O
−
|
+
| rowspan="16" |TBD
−
|
+
|Pin AF0
−
|
+
|TBD
 +
|-
 +
|Pin AF1
 +
|TBD
 +
|-
 +
|Pin AF2
 +
|TBD
 
|-
 
|-
−
| rowspan="7" |J1.89
 
−
| rowspan="7" |PD8
 
−
| rowspan="7" |CPU.PD8
 
−
| rowspan="7" |F2
 
−
| rowspan="7" |VDD
 
−
| rowspan="7" |I/O
 
−
| rowspan="7" |
 
 
|Pin AF3
 
|Pin AF3
−
|DFSDM1_CKIN3
+
|TBD
 +
|-
 +
|Pin AF4
 +
|TBD
 +
|-
 +
|Pin AF5
 +
|TBD
 
|-
 
|-
 
|Pin AF6
 
|Pin AF6
−
|SAI3_SCK_B
+
|TBD
 
|-
 
|-
 
|Pin AF7
 
|Pin AF7
−
|USART3_TX
+
|TBD
 +
|-
 +
|Pin AF8
 +
|TBD
 
|-
 
|-
 
|Pin AF9
 
|Pin AF9
−
|SPDIFRX_IN2
+
|TBD
 
|-
 
|-
−
|Pin AF12
+
|Pin AF10
−
|FMC_AD13/FMC_D13
+
|TBD
 
|-
 
|-
−
|Pin AF14
+
|Pin AF11
−
|LCD_B7
+
|TBD
−
|-
 
−
|Pin AF15
 
−
|EVENTOUT
 
−
|-
 
−
| rowspan="7" |J1.91
 
−
| rowspan="7" |PD9
 
−
| rowspan="7" |CPU.PD9
 
−
| rowspan="7" |G3
 
−
| rowspan="7" |VDD
 
−
| rowspan="7" |I/O
 
−
| rowspan="7" |
 
−
|Pin AF3
 
−
|DFSDM1_DATIN3
 
−
|-
 
−
|Pin AF6
 
−
|SAI3_SD_B
 
−
|-
 
−
|Pin AF7
 
−
|USART3_RX
 
 
|-
 
|-
 
|Pin AF12
 
|Pin AF12
−
|FMC_AD14/FMC_D14
+
|TBD
 
|-
 
|-
 
|Pin AF13
 
|Pin AF13
−
|DCMI_HSYNC
+
|TBD
 
|-
 
|-
 
|Pin AF14
 
|Pin AF14
−
|LCD_B0
+
|TBD
 
|-
 
|-
 
|Pin AF15
 
|Pin AF15
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
|J1.93
+
| rowspan="16" |J1.81
−
(I/O EXP on board)
+
| rowspan="16" |PC11
−
|PC2
+
| rowspan="16" |CPU.PC11
−
|CPU.PC2
+
| rowspan="16" |A11
−
|T2
+
| rowspan="16" |VDD
−
|VDD
+
| rowspan="16" |I/O
−
|I/O
+
| rowspan="16" |TBD
−
|internally used for I/O EXP,
+
|Pin AF0
−
 
+
|TBD
−
do not connect
 
−
|
 
−
|
 
−
|-
 
−
| rowspan="7" |J1.93
 
−
| rowspan="7" |PC2
 
−
| rowspan="7" |CPU.PC2
 
−
| rowspan="7" |T2
 
−
| rowspan="7" |VDD
 
−
| rowspan="7" |I/O
 
−
| rowspan="7" |
 
−
|Pin AF3
 
−
|DFSDM1_CKIN1
 
−
|-
 
−
|Pin AF5
 
−
|SPI2_MISO/I2S2_SDI
 
−
|-
 
−
|Pin AF6
 
−
|DFSDM1_CKOUT
 
−
|-
 
−
|Pin AF11
 
−
|ETH1_GMII_TXD2/
 
−
 
 
−
ETH1_MII_TXD2/
 
−
 
 
−
ETH1_RGMII_TXD2
 
−
|-
 
−
|Pin AF13
 
−
|DCMI_PIXCLK
 
−
|-
 
−
|Pin AF15
 
−
|EVENTOUT
 
−
|-
 
−
|Additional
 
−
functions
 
−
|ADC1_INP12
 
−
 
 
−
ADC1_INN11
 
−
|-
 
−
|J1.95
 
−
|PA0
 
−
|CPU.PA0
 
−
|R3
 
−
|VDD
 
−
|I/O
 
−
|internally used for PMIC,
 
−
 
 
−
do not connect
 
−
|
 
−
|
 
 
|-
 
|-
−
| rowspan="11" |J1.97
 
−
| rowspan="11" |PD13
 
−
| rowspan="11" |CPU.PD13
 
−
| rowspan="11" |U12
 
−
| rowspan="11" |VDD
 
−
| rowspan="11" |I/O
 
−
| rowspan="11" |
 
 
|Pin AF1
 
|Pin AF1
−
|LPTIM1_OUT
+
|TBD
 
|-
 
|-
 
|Pin AF2
 
|Pin AF2
−
|TIM4_CH2
+
|TBD
 +
|-
 +
|Pin AF3
 +
|TBD
 
|-
 
|-
 
|Pin AF4
 
|Pin AF4
−
|I2C4_SDA
+
|TBD
 
|-
 
|-
 
|Pin AF5
 
|Pin AF5
−
|I2C1_SDA
+
|TBD
 
|-
 
|-
 
|Pin AF6
 
|Pin AF6
−
|I2S3_MCK
+
|TBD
 +
|-
 +
|Pin AF7
 +
|TBD
 
|-
 
|-
 
|Pin AF8
 
|Pin AF8
−
|SDMMC1_D123DIR
+
|TBD
 
|-
 
|-
 
|Pin AF9
 
|Pin AF9
−
|QUADSPI_BK1_IO3
+
|TBD
 
|-
 
|-
 
|Pin AF10
 
|Pin AF10
−
|SAI2_SCK_A
+
|TBD
 +
|-
 +
|Pin AF11
 +
|TBD
 
|-
 
|-
 
|Pin AF12
 
|Pin AF12
−
|FMC_A18
+
|TBD
 
|-
 
|-
 
|Pin AF13
 
|Pin AF13
−
|DSI_TE
+
|TBD
 +
|-
 +
|Pin AF14
 +
|TBD
 
|-
 
|-
 
|Pin AF15
 
|Pin AF15
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
|J1.99
+
| rowspan="16" |J1.83
−
(NAND on board)
+
| rowspan="16" |PD2
−
|PD12
+
| rowspan="16" |CPU.PD2
−
|CPU.PD12
+
| rowspan="16" |B10
−
|U11
+
| rowspan="16" |VDD
−
|VDD
+
| rowspan="16" |I/O
−
|I/O
+
| rowspan="16" |TBD
−
|internally used for NAND flash,
+
|Pin AF0
−
do not connect
+
|TBD
−
|
 
−
|
 
 
|-
 
|-
−
| rowspan="10" |J1.99
 
−
| rowspan="10" |PD12
 
−
| rowspan="10" |CPU.PD12
 
−
| rowspan="10" |U11
 
−
| rowspan="10" |VDD
 
−
| rowspan="10" |I/O
 
−
| rowspan="10" |
 
 
|Pin AF1
 
|Pin AF1
−
|LPTIM1_IN1
+
|TBD
 
|-
 
|-
 
|Pin AF2
 
|Pin AF2
−
|TIM4_CH1
+
|TBD
 
|-
 
|-
 
|Pin AF3
 
|Pin AF3
−
|LPTIM2_IN1
+
|TBD
 
|-
 
|-
 
|Pin AF4
 
|Pin AF4
−
|I2C4_SCL
+
|TBD
 
|-
 
|-
 
|Pin AF5
 
|Pin AF5
−
|I2C1_SCL
+
|TBD
 +
|-
 +
|Pin AF6
 +
|TBD
 
|-
 
|-
 
|Pin AF7
 
|Pin AF7
−
|USART3_RTS/USART3_DE
+
|TBD
 +
|-
 +
|Pin AF8
 +
|TBD
 
|-
 
|-
 
|Pin AF9
 
|Pin AF9
−
|QUADSPI_BK1_IO1
+
|TBD
 
|-
 
|-
 
|Pin AF10
 
|Pin AF10
−
|SAI2_FS_A
+
|TBD
 +
|-
 +
|Pin AF11
 +
|TBD
 
|-
 
|-
 
|Pin AF12
 
|Pin AF12
−
|FMC_A17/FMC_ALE
+
|TBD
 +
|-
 +
|Pin AF13
 +
|TBD
 +
|-
 +
|Pin AF14
 +
|TBD
 
|-
 
|-
 
|Pin AF15
 
|Pin AF15
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
|J1.101
+
| rowspan="16" |J1.85
−
(NAND on board)
+
| rowspan="16" |PC12
−
|PD11
+
| rowspan="16" |CPU.PC12
−
|CPU.PD11
+
| rowspan="16" |C10
−
|V8
+
| rowspan="16" |VDD
−
|VDD
+
| rowspan="16" |I/O
−
|I/O
+
| rowspan="16" |TBD
−
|internally used for NAND flash,
+
|Pin AF0
−
 
+
|TBD
−
do not connect
+
|-
−
|
+
|Pin AF1
−
|
+
|TBD
 +
|-
 +
|Pin AF2
 +
|TBD
 
|-
 
|-
−
| rowspan="8" |J1.101
 
−
| rowspan="8" |PD11
 
−
| rowspan="8" |CPU.PD11
 
−
| rowspan="8" |V8
 
−
| rowspan="8" |VDD
 
−
| rowspan="8" |I/O
 
−
| rowspan="8" |
 
 
|Pin AF3
 
|Pin AF3
−
|LPTIM2_IN2
+
|TBD
 
|-
 
|-
 
|Pin AF4
 
|Pin AF4
−
|I2C4_SMBA
+
|TBD
 
|-
 
|-
 
|Pin AF5
 
|Pin AF5
−
|I2C1_SMBA
+
|TBD
 +
|-
 +
|Pin AF6
 +
|TBD
 
|-
 
|-
 
|Pin AF7
 
|Pin AF7
−
|USART3_CTS/USART3_NSS
+
|TBD
 +
|-
 +
|Pin AF8
 +
|TBD
 
|-
 
|-
 
|Pin AF9
 
|Pin AF9
−
|QUADSPI_BK1_IO0
+
|TBD
 
|-
 
|-
 
|Pin AF10
 
|Pin AF10
−
|SAI2_SD_A
+
|TBD
 +
|-
 +
|Pin AF11
 +
|TBD
 
|-
 
|-
 
|Pin AF12
 
|Pin AF12
−
|FMC_A16/FMC_CLE
+
|TBD
 +
|-
 +
|Pin AF13
 +
|TBD
 +
|-
 +
|Pin AF14
 +
|TBD
 
|-
 
|-
 
|Pin AF15
 
|Pin AF15
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
|J1.103
+
|J1.87
−
| -
+
|DGND
−
|NC
+
|DGND
−
| -
 
 
| -
 
| -
 
| -
 
| -
 +
|G
 
|
 
|
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.105
+
| rowspan="16" |J1.89
−
(NAND on board)
+
| rowspan="16" |PD8
−
|PG9
+
| rowspan="16" |CPU.PD8
−
|CPU.PG9
+
| rowspan="16" |F2
−
|T14
+
| rowspan="16" |VDD
−
|VDD
+
| rowspan="16" |I/O
−
|I/O
+
| rowspan="16" |TBD
−
|internally used for NAND flash,
+
|Pin AF0
−
 
+
|TBD
−
do not connect
+
|-
−
|
+
|Pin AF1
−
|
+
|TBD
 +
|-
 +
|Pin AF2
 +
|TBD
 +
|-
 +
|Pin AF3
 +
|TBD
 +
|-
 +
|Pin AF4
 +
|TBD
 +
|-
 +
|Pin AF5
 +
|TBD
 
|-
 
|-
−
| rowspan="9" |J1.105
+
|Pin AF6
−
| rowspan="9" |PG9
+
|TBD
−
| rowspan="9" |CPU.PG9
 
−
| rowspan="9" |T14
 
−
| rowspan="9" |VDD
 
−
| rowspan="9" |I/O
 
−
| rowspan="9" |
 
−
|Pin AF0
 
−
|DBTRGO
 
 
|-
 
|-
 
|Pin AF7
 
|Pin AF7
−
|USART6_RX
+
|TBD
 
|-
 
|-
 
|Pin AF8
 
|Pin AF8
−
|SPDIFRX_IN4
+
|TBD
 
|-
 
|-
 
|Pin AF9
 
|Pin AF9
−
|QUADSPI_BK2_IO2
+
|TBD
 
|-
 
|-
 
|Pin AF10
 
|Pin AF10
−
|SAI2_FS_B
+
|TBD
 +
|-
 +
|Pin AF11
 +
|TBD
 
|-
 
|-
 
|Pin AF12
 
|Pin AF12
−
|FMC_NE2/FMC_NCE
+
|TBD
 
|-
 
|-
 
|Pin AF13
 
|Pin AF13
−
|DCMI_VSYNC
+
|TBD
 
|-
 
|-
 
|Pin AF14
 
|Pin AF14
−
|LCD_R1
+
|TBD
 
|-
 
|-
 
|Pin AF15
 
|Pin AF15
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
|J1.107
+
| rowspan="16" |J1.91
−
| -
+
| rowspan="16" |PD9
−
|NC
+
| rowspan="16" |CPU.PD9
−
| -
+
| rowspan="16" |G3
−
| -
+
| rowspan="16" |VDD
−
| -
+
| rowspan="16" |I/O
−
|
+
| rowspan="16" |TBD
−
|
+
|Pin AF0
−
|
+
|TBD
 +
|-
 +
|Pin AF1
 +
|TBD
 
|-
 
|-
−
|J1.109
+
|Pin AF2
−
|DGND
+
|TBD
−
|DGND
 
−
| -
 
−
| -
 
−
|G
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.111
+
|Pin AF3
−
|DSI_CKN
+
|TBD
−
|CPU.DSI_CKN
 
−
|A14
 
−
| -
 
−
|D
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.113
+
|Pin AF4
−
|DSI_CKP
+
|TBD
−
|CPU.DSI_CKP
 
−
|B14
 
−
| -
 
−
|D
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.115
+
|Pin AF5
−
|DSI_D0N
+
|TBD
−
|CPU.DSI_D0N
 
−
|A13
 
−
| -
 
−
|D
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.117
+
|Pin AF6
−
|DSI_D0P
+
|TBD
−
|DSI_D0P
 
−
|B13
 
−
| -
 
−
|D
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.119
+
|Pin AF7
−
|DSI_D1N
+
|TBD
−
|CPU.DSI_D1N
 
−
|A15
 
−
| -
 
−
|D
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.121
+
|Pin AF8
−
|DSI_D1P
+
|TBD
−
|CPU.DSI_D1P
+
|-
−
|B15
+
|Pin AF9
−
| -
+
|TBD
−
|D
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.123
+
|Pin AF10
−
| -
+
|TBD
−
|NC
 
−
| -
 
−
| -
 
−
| -
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.125
+
|Pin AF11
−
| -
+
|TBD
−
|NC
 
−
| -
 
−
| -
 
−
| -
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.127
+
|Pin AF12
−
| -
+
|TBD
−
|NC
+
|-
−
| -
+
|Pin AF13
−
| -
+
|TBD
−
| -
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.129
+
|Pin AF14
−
| -
+
|TBD
−
|NC
 
−
| -
 
−
| -
 
−
| -
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.131
+
|Pin AF15
−
|DGND
+
|TBD
−
|DGND
 
−
| -
 
−
| -
 
−
|G
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
| rowspan="2" |J1.133
+
| rowspan="16" |J1.93
−
| rowspan="2" |ADP5589_R7
+
| rowspan="16" |PC2
−
| rowspan="2" |EXP.R7
+
| rowspan="16" |CPU.PC2
−
| rowspan="2" |1
+
| rowspan="16" |T2
−
| rowspan="2" |VDD
+
| rowspan="16" |VDD
−
| rowspan="2" |I/O
+
| rowspan="16" |I/O
−
| rowspan="2" |
+
| rowspan="16" |TBD
 
|Pin AF0
 
|Pin AF0
−
|Keypad row 7
+
|TBD
 
|-
 
|-
−
|Pin AF5
+
|Pin AF1
−
|GPIO 8
+
|TBD
 
|-
 
|-
−
| rowspan="2" |J1.135
+
|Pin AF2
−
| rowspan="2" |ADP5589_R6
+
|TBD
−
| rowspan="2" |EXP.R6
 
−
| rowspan="2" |2
 
−
| rowspan="2" |VDD
 
−
| rowspan="2" |I/O
 
−
| rowspan="2" |
 
−
|Pin AF0
 
−
|Keypad row 6
 
 
|-
 
|-
−
|Pin AF5
+
|Pin AF3
−
|GPIO 7
+
|TBD
 
|-
 
|-
−
| rowspan="2" |J1.137
+
|Pin AF4
−
| rowspan="2" |ADP5589_R5
+
|TBD
−
| rowspan="2" |EXP.R5
 
−
| rowspan="2" |3
 
−
| rowspan="2" |VDD
 
−
| rowspan="2" |I/O
 
−
| rowspan="2" |
 
−
|Pin AF0
 
−
|Keypad row 5
 
 
|-
 
|-
 
|Pin AF5
 
|Pin AF5
−
|GPIO 6
+
|TBD
 
|-
 
|-
−
| rowspan="3" |J1.139
+
|Pin AF6
−
| rowspan="3" |ADP5589_R4
+
|TBD
−
| rowspan="3" |EXP.R4
+
|-
−
| rowspan="3" |4
+
|Pin AF7
−
| rowspan="3" |VDD
+
|TBD
−
| rowspan="3" |I/O
+
|-
−
| rowspan="3" |
+
|Pin AF8
−
|Pin AF0
+
|TBD
−
|Keypad row 4
 
 
|-
 
|-
−
|Pin AF1
+
|Pin AF9
−
|RESET1
+
|TBD
 
|-
 
|-
−
|Pin AF5
+
|Pin AF10
−
|GPIO 5
+
|TBD
 
|-
 
|-
−
| rowspan="5" |J1.141
+
|Pin AF11
−
| rowspan="5" |ADP5589_R3
+
|TBD
−
| rowspan="5" |EXP.R3
 
−
| rowspan="5" |5
 
−
| rowspan="5" |VDD
 
−
| rowspan="5" |I/O
 
−
| rowspan="5" |
 
−
|Pin AF0
 
−
|Keypad row 3
 
 
|-
 
|-
−
|Pin AF1
+
|Pin AF12
−
|Logic LC1
+
|TBD
 
|-
 
|-
−
|Pin AF2
+
|Pin AF13
−
|PWM_OUT
+
|TBD
 
|-
 
|-
−
|Pin AF3
+
|Pin AF14
−
|CLK_OUT
+
|TBD
 
|-
 
|-
−
|Pin AF5
+
|Pin AF15
−
|GPIO 4
+
|TBD
 
|-
 
|-
−
| rowspan="3" |J1.143
+
| rowspan="16" |J1.95
−
| rowspan="3" |ADP5589_R2
+
| rowspan="16" |PA0
−
| rowspan="3" |EXP.R2
+
| rowspan="16" |CPU.PA0
−
| rowspan="3" |6
+
| rowspan="16" |R3
−
| rowspan="3" |VDD
+
| rowspan="16" |VDD
−
| rowspan="3" |I/O
+
| rowspan="16" |I/O
−
| rowspan="3" |
+
| rowspan="16" |TBD
 
|Pin AF0
 
|Pin AF0
−
|Keypad row 2
+
|TBD
 
|-
 
|-
 
|Pin AF1
 
|Pin AF1
−
|LOGIC LB1
+
|TBD
 
|-
 
|-
−
|Pin AF5
+
|Pin AF2
−
|GPIO 3
+
|TBD
 
|-
 
|-
−
| rowspan="3" |J1.145
+
|Pin AF3
−
| rowspan="3" |ADP5589_R1
+
|TBD
−
| rowspan="3" |EXP.R1
 
−
| rowspan="3" |7
 
−
| rowspan="3" |VDD
 
−
| rowspan="3" |I/O
 
−
| rowspan="3" |
 
−
|Pin AF0
 
−
|Keypad row 1
 
 
|-
 
|-
−
|Pin AF1
+
|Pin AF4
−
|Logic LA1
+
|TBD
 
|-
 
|-
 
|Pin AF5
 
|Pin AF5
−
|GPIO 2
+
|TBD
 
|-
 
|-
−
| rowspan="3" |J1.147
+
|Pin AF6
−
| rowspan="3" |ADP5589_R0
+
|TBD
−
| rowspan="3" |EXP.R0
 
−
| rowspan="3" |8
 
−
| rowspan="3" |VDD
 
−
| rowspan="3" |I/O
 
−
| rowspan="3" |
 
−
|Pin AF0
 
−
|Keypad row 0
 
 
|-
 
|-
−
|Pin AF1
+
|Pin AF7
−
|Logic LY1
+
|TBD
 
|-
 
|-
−
|Pin AF5
+
|Pin AF8
−
|GPIO 1
+
|TBD
 
|-
 
|-
−
| rowspan="2" |J1.149
+
|Pin AF9
−
| rowspan="2" |ADP5589_C0
+
|TBD
−
| rowspan="2" |EXP.C0
 
−
| rowspan="2" |9
 
−
| rowspan="2" |VDD
 
−
| rowspan="2" |I/O
 
−
| rowspan="2" |
 
−
|Pin AF0
 
−
|Keypad column 0
 
 
|-
 
|-
−
|Pin AF5
+
|Pin AF10
−
|GPIO 9
+
|TBD
 
|-
 
|-
−
| rowspan="2" |J1.151
+
|Pin AF11
−
| rowspan="2" |ADP5589_C1
+
|TBD
−
| rowspan="2" |EXP.C1
 
−
| rowspan="2" |10
 
−
| rowspan="2" |VDD
 
−
| rowspan="2" |I/O
 
−
| rowspan="2" |
 
−
|Pin AF0
 
−
|Keypad column 1
 
 
|-
 
|-
−
|Pin AF5
+
|Pin AF12
−
|GPIO 10
+
|TBD
 
|-
 
|-
−
|J1.153
+
|Pin AF13
−
|DGND
+
|TBD
−
|DGND
 
−
| -
 
−
| -
 
−
|G
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
| rowspan="2" |J1.155
+
|Pin AF14
−
| rowspan="2" |ADP5589_C2
+
|TBD
−
| rowspan="2" |EXP.C2
 
−
| rowspan="2" |11
 
−
| rowspan="2" |VDD
 
−
| rowspan="2" |I/O
 
−
| rowspan="2" |
 
−
|Pin AF0
 
−
|Keypad column 2
 
 
|-
 
|-
−
|Pin AF5
+
|Pin AF15
−
|GPIO 11
+
|TBD
 
|-
 
|-
−
| rowspan="2" |J1.157
+
| rowspan="16" |J1.97
−
| rowspan="2" |ADP5589_C3
+
| rowspan="16" |PD13
−
| rowspan="2" |EXP.C3
+
| rowspan="16" |CPU.PD13
−
| rowspan="2" |12
+
| rowspan="16" |U12
−
| rowspan="2" |VDD
+
| rowspan="16" |VDD
−
| rowspan="2" |I/O
+
| rowspan="16" |I/O
−
| rowspan="2" |
+
| rowspan="16" |TBD
 
|Pin AF0
 
|Pin AF0
−
|Keypad column 3
+
|TBD
 
|-
 
|-
−
|Pin AF5
+
|Pin AF1
−
|GPIO 12
+
|TBD
 
|-
 
|-
−
| rowspan="3" |J1.159
+
|Pin AF2
−
| rowspan="3" |ADP5589_C4
+
|TBD
−
| rowspan="3" |EXP.C4
 
−
| rowspan="3" |13
 
−
| rowspan="3" |VDD
 
−
| rowspan="3" |I/O
 
−
| rowspan="3" |
 
−
|Pin AF0
 
−
|Keypad column 4
 
 
|-
 
|-
−
|Pin AF1
+
|Pin AF3
−
|RESET2
+
|TBD
 +
|-
 +
|Pin AF4
 +
|TBD
 
|-
 
|-
 
|Pin AF5
 
|Pin AF5
−
|GPIO 13
+
|TBD
 
|-
 
|-
−
| rowspan="2" |J1.161
+
|Pin AF6
−
| rowspan="2" |ADP5589_C5
+
|TBD
−
| rowspan="2" |EXP.C5
 
−
| rowspan="2" |14
 
−
| rowspan="2" |VDD
 
−
| rowspan="2" |I/O
 
−
| rowspan="2" |
 
−
|Pin AF0
 
−
|Keypad column 5
 
 
|-
 
|-
−
|Pin AF5
+
|Pin AF7
−
|GPIO 14
+
|TBD
 
|-
 
|-
−
| rowspan="5" |J1.163
+
|Pin AF8
−
| rowspan="5" |ADP5589_C6
+
|TBD
−
| rowspan="5" |EXP.C6
 
−
| rowspan="5" |15
 
−
| rowspan="5" |VDD
 
−
| rowspan="5" |I/O
 
−
| rowspan="5" |
 
−
|Pin AF0
 
−
|Keypad column 6
 
 
|-
 
|-
−
|Pin AF1
+
|Pin AF9
−
|Logic LC2
+
|TBD
 
|-
 
|-
−
|Pin AF2
+
|Pin AF10
−
|PWM_IN
+
|TBD
 
|-
 
|-
−
|Pin AF3
+
|Pin AF11
−
|CLK_IN
+
|TBD
 
|-
 
|-
−
|Pin AF5
+
|Pin AF12
−
|GPIO 15
+
|TBD
 
|-
 
|-
−
| rowspan="3" |J1.165
+
|Pin AF13
−
| rowspan="3" |ADP5589_C7
+
|TBD
−
| rowspan="3" |EXP.C7
 
−
| rowspan="3" |16
 
−
| rowspan="3" |VDD
 
−
| rowspan="3" |I/O
 
−
| rowspan="3" |
 
−
|Pin AF0
 
−
|Keypad column 7
 
 
|-
 
|-
−
|Pin AF1
+
|Pin AF14
−
|Logic LB2
+
|TBD
 
|-
 
|-
−
|Pin AF5
+
|Pin AF15
−
|GPIO 16
+
|TBD
 
|-
 
|-
−
| rowspan="3" |J1.167
+
| rowspan="16" |J1.99
−
| rowspan="3" |ADP5589_C8
+
| rowspan="16" |PD12
−
| rowspan="3" |EXP.C8
+
| rowspan="16" |CPU.PD12
−
| rowspan="3" |19
+
| rowspan="16" |U11
−
| rowspan="3" |VDD
+
| rowspan="16" |VDD
−
| rowspan="3" |I/O
+
| rowspan="16" |I/O
−
| rowspan="3" |
+
| rowspan="16" |TBD
 
|Pin AF0
 
|Pin AF0
−
|Keypad column 8
+
|TBD
 
|-
 
|-
 
|Pin AF1
 
|Pin AF1
−
|Logic LA2
+
|TBD
 
|-
 
|-
−
|Pin AF5
+
|Pin AF2
−
|GPIO 17
+
|TBD
 
|-
 
|-
−
| rowspan="3" |J1.169
+
|Pin AF3
−
| rowspan="3" |ADP5589_C9
+
|TBD
−
| rowspan="3" |EXP.C9
 
−
| rowspan="3" |20
 
−
| rowspan="3" |VDD
 
−
| rowspan="3" |I/O
 
−
| rowspan="3" |
 
−
|Pin AF0
 
−
|Keypad column 9
 
 
|-
 
|-
−
|Pin AF1
+
|Pin AF4
−
|Logic LY2
+
|TBD
 
|-
 
|-
 
|Pin AF5
 
|Pin AF5
−
|GPIO 18
+
|TBD
 
|-
 
|-
−
| rowspan="2" |J1.171
+
|Pin AF6
−
| rowspan="2" |ADP5589_C10
+
|TBD
−
| rowspan="2" |EXP.C10
 
−
| rowspan="2" |21
 
−
| rowspan="2" |VDD
 
−
| rowspan="2" |I/O
 
−
| rowspan="2" |
 
−
|Pin AF0
 
−
|Keypad column 10
 
 
|-
 
|-
−
|Pin AF5
+
|Pin AF7
−
|GPIO 19
+
|TBD
 
|-
 
|-
−
|J1.173
+
|Pin AF8
−
| -
+
|TBD
−
|NC
 
−
| -
 
−
| -
 
−
| -
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.175
+
|Pin AF9
−
|DGND
+
|TBD
−
|DGND
 
−
| -
 
−
| -
 
−
|G
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.177
+
|Pin AF10
−
 
+
|TBD
−
(NAND on board)
 
−
|PE9
 
−
|CPU.PE9
 
−
|W7
 
−
|VDD
 
−
|I/O
 
−
|internally used for NAND flash,
 
−
do not connect
 
−
|
 
−
|
 
 
|-
 
|-
−
| rowspan="6" |J1.177
+
|Pin AF11
−
| rowspan="6" |PE9
+
|TBD
−
| rowspan="6" |CPU.PE9
 
−
| rowspan="6" |W7
 
−
| rowspan="6" |VDD
 
−
| rowspan="6" |I/O
 
−
| rowspan="6" |
 
−
|Pin AF1
 
−
|TIM1_CH1
 
 
|-
 
|-
−
|Pin AF3
+
|Pin AF12
−
|DFSDM1_CKOUT
+
|TBD
 
|-
 
|-
−
|Pin AF7
+
|Pin AF13
−
|UART7_RTS/UART7_DE
+
|TBD
 
|-
 
|-
−
|Pin AF10
+
|Pin AF14
−
|QUADSPI_BK2_IO2
+
|TBD
−
|-
 
−
|Pin AF12
 
−
|FMC_AD6/FMC_D6
 
 
|-
 
|-
 
|Pin AF15
 
|Pin AF15
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
|J1.179
+
| rowspan="16" |J1.101
−
 
+
| rowspan="16" |PD11
−
(I/O EXP on board)
+
| rowspan="16" |CPU.PD11
−
|PC3
+
| rowspan="16" |V8
−
|CPU.PC3
+
| rowspan="16" |VDD
−
|T3
+
| rowspan="16" |I/O
−
|VDD
+
| rowspan="16" |TBD
−
|I/O
 
−
|internally used for I/O EXP,
 
−
 
 
−
do not connect
 
−
|
 
−
|
 
−
|-
 
−
| rowspan="6" |J1.179
 
−
| rowspan="6" |PC3
 
−
| rowspan="6" |CPU.PC3
 
−
| rowspan="6" |T3
 
−
| rowspan="6" |VDD
 
−
| rowspan="6" |I/O
 
−
| rowspan="6" |
 
 
|Pin AF0
 
|Pin AF0
−
|TRACECLK
+
|TBD
−
|-
 
−
|Pin AF3
 
−
|DFSDM1_DATIN1
 
−
|-
 
−
|Pin AF5
 
−
|SPI2_MOSI/I2S2_SDO
 
−
|-
 
−
|Pin AF11
 
−
|ETH1_GMII_TX_CLK/
 
−
 
 
−
ETH1_MII_TX_CLK
 
−
|-
 
−
|Pin AF15
 
−
|EVENTOUT
 
−
|-
 
−
|Additional
 
−
functions
 
−
|ADC1_INP13
 
−
 
 
−
ADC1_INN12
 
−
|-
 
−
|J1.181
 
−
 
 
−
(NAND on board)
 
−
|PD6
 
−
|CPU.PD6
 
−
|E3
 
−
|VDD
 
−
|I/O
 
−
|internally used for NAND flash,
 
−
 
 
−
do not connect
 
−
|
 
−
|
 
 
|-
 
|-
−
| rowspan="11" |J1.181
 
−
| rowspan="11" |PD6
 
−
| rowspan="11" |CPU.PD6
 
−
| rowspan="11" |E3
 
−
| rowspan="11" |VDD
 
−
| rowspan="11" |I/O
 
−
| rowspan="11" |
 
 
|Pin AF1
 
|Pin AF1
−
|TIM16_CH1N
+
|TBD
 
|-
 
|-
 
|Pin AF2
 
|Pin AF2
−
|SAI1_D1
+
|TBD
 
|-
 
|-
 
|Pin AF3
 
|Pin AF3
−
|DFSDM1_CKIN4
+
|TBD
 
|-
 
|-
 
|Pin AF4
 
|Pin AF4
−
|DFSDM1_DATIN1
+
|TBD
 
|-
 
|-
 
|Pin AF5
 
|Pin AF5
−
|SPI3_MOSI/I2S3_SDO
+
|TBD
 
|-
 
|-
 
|Pin AF6
 
|Pin AF6
−
|SAI1_SD_A
+
|TBD
 
|-
 
|-
 
|Pin AF7
 
|Pin AF7
−
|USART2_RX
+
|TBD
 
|-
 
|-
−
|Pin AF12
+
|Pin AF8
−
|FMC_NWAIT
+
|TBD
 
|-
 
|-
−
|Pin AF13
+
|Pin AF9
−
|DCMI_D10
+
|TBD
 +
|-
 +
|Pin AF10
 +
|TBD
 +
|-
 +
|Pin AF11
 +
|TBD
 +
|-
 +
|Pin AF12
 +
|TBD
 +
|-
 +
|Pin AF13
 +
|TBD
 
|-
 
|-
 
|Pin AF14
 
|Pin AF14
−
|LCD_B2
+
|TBD
 
|-
 
|-
 
|Pin AF15
 
|Pin AF15
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
|J1.183
+
|J1.103
−
 
+
| -
−
(NAND on board)
+
|NC
−
|PE10
+
| -
−
|CPU.PE10
+
| -
−
|V10
+
| -
−
|VDD
+
|
−
|I/O
 
−
|internally used for NAND flash,
 
−
 
 
−
do not connect
 
 
|
 
|
 
|
 
|
 
|-
 
|-
−
| rowspan="6" |J1.183
+
| rowspan="16" |J1.105
−
| rowspan="6" |PE10
+
| rowspan="16" |PG9
−
| rowspan="6" |CPU.PE10
+
| rowspan="16" |CPU.PG9
−
| rowspan="6" |V10
+
| rowspan="16" |T14
−
| rowspan="6" |VDD
+
| rowspan="16" |VDD
−
| rowspan="6" |I/O
+
| rowspan="16" |I/O
−
| rowspan="6" |
+
| rowspan="16" |TBD
 +
|Pin AF0
 +
|TBD
 +
|-
 
|Pin AF1
 
|Pin AF1
−
|TIM1_CH2N
+
|TBD
 +
|-
 +
|Pin AF2
 +
|TBD
 
|-
 
|-
 
|Pin AF3
 
|Pin AF3
−
|DFSDM1_DATIN4
+
|TBD
 +
|-
 +
|Pin AF4
 +
|TBD
 +
|-
 +
|Pin AF5
 +
|TBD
 +
|-
 +
|Pin AF6
 +
|TBD
 
|-
 
|-
 
|Pin AF7
 
|Pin AF7
−
|UART7_CTS
+
|TBD
 +
|-
 +
|Pin AF8
 +
|TBD
 +
|-
 +
|Pin AF9
 +
|TBD
 
|-
 
|-
 
|Pin AF10
 
|Pin AF10
−
|QUADSPI_BK2_IO3
+
|TBD
 +
|-
 +
|Pin AF11
 +
|TBD
 
|-
 
|-
 
|Pin AF12
 
|Pin AF12
−
|FMC_AD7/FMC_D7
+
|TBD
−
|-
 
−
|Pin AF15
 
−
|EVENTOUT
 
−
|-
 
−
|J1.185
 
−
|VBUS_OTG_OUT
 
−
|PMIC.VBUSOTG
 
−
|35
 
−
|VBUSOTG
 
−
|S
 
−
|USB OTG VOUT
 
−
|
 
−
|
 
−
|-
 
−
| rowspan="8" |J1.187
 
−
| rowspan="8" |PG11
 
−
| rowspan="8" |CPU.PG11
 
−
| rowspan="8" |V6
 
−
| rowspan="8" |VDD
 
−
| rowspan="8" |I/O
 
−
| rowspan="8" |
 
−
|Pin AF0
 
−
|TRACED11
 
−
|-
 
−
|Pin AF4
 
−
|USART1_TX
 
−
|-
 
−
|Pin AF6
 
−
|UART4_TX
 
−
|-
 
−
|Pin AF8
 
−
|SPDIFRX_IN1
 
−
|-
 
−
|Pin AF11
 
−
|ETH1_GMII_TX_EN/
 
−
 
 
−
ETH1_MII_TX_EN/
 
−
 
 
−
ETH1_RGMII_TX_CTL/
 
−
 
 
−
ETH1_RMII_TX_EN
 
 
|-
 
|-
 
|Pin AF13
 
|Pin AF13
−
|DCMI_D3
+
|TBD
 
|-
 
|-
 
|Pin AF14
 
|Pin AF14
−
|LCD_B3
+
|TBD
 
|-
 
|-
 
|Pin AF15
 
|Pin AF15
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
| rowspan="11" |J1.189
+
|J1.107
−
| rowspan="11" |PB2
+
| -
−
| rowspan="11" |CPU.PB2
+
|NC
−
| rowspan="11" |T13
+
| -
−
| rowspan="11" |VDD
+
| -
−
| rowspan="11" |I/O
+
| -
−
| rowspan="11" |
+
|
−
|Pin AF0
+
|
−
|TRACED4
+
|
 
|-
 
|-
−
|Pin AF1
+
|J1.109
−
|RTC_OUT2
+
|DGND
 +
|DGND
 +
| -
 +
| -
 +
|G
 +
|
 +
|
 +
|
 
|-
 
|-
−
|Pin AF2
+
|J1.111
−
|SAI1_D1
+
|DSI_CKN
 +
|CPU.DSI_CKN
 +
|A14
 +
| -
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
|Pin AF3
+
|J1.113
−
|DFSDM1_CKIN1
+
|DSI_CKP
 +
|CPU.DSI_CKP
 +
|B14
 +
| -
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
|Pin AF4
+
|J1.115
−
|USART1_RX
+
|DSI_D0N
−
|-
+
|CPU.DSI_D0N
−
|Pin AF5
+
|A13
−
|I2S_CKIN
+
| -
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
|Pin AF6
+
|J1.117
−
|SAI1_SD_A
+
|DSI_D0P
 +
|DSI_D0P
 +
|B13
 +
| -
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
|Pin AF7
+
|J1.119
−
|SPI3_MOSI/I2S3_SDO
+
|DSI_D1N
 +
|CPU.DSI_D1N
 +
|A15
 +
| -
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
|Pin AF8
+
|J1.121
−
|UART4_RX
+
|DSI_D1P
 +
|CPU.DSI_D1P
 +
|B15
 +
| -
 +
|D
 +
|
 +
|
 +
|
 
|-
 
|-
−
|Pin AF9
+
|J1.123
−
|QUADSPI_CLK
+
| -
 +
|NC
 +
| -
 +
| -
 +
| -
 +
|
 +
|
 +
|
 
|-
 
|-
−
|Pin AF15
+
|J1.125
−
|EVENTOUT
+
| -
 +
|NC
 +
| -
 +
| -
 +
| -
 +
|
 +
|
 +
|
 
|-
 
|-
−
| rowspan="7" |J1.191
+
|J1.127
−
| rowspan="7" |PE1
+
| -
−
| rowspan="7" |CPU.PE1
+
|NC
−
| rowspan="7" |B1
+
| -
−
| rowspan="7" |VDD
+
| -
−
| rowspan="7" |I/O
+
| -
−
| rowspan="7" |
+
|
−
|Pin AF1
+
|
−
|LPTIM1_IN2
+
|
 
|-
 
|-
−
|Pin AF5
+
|J1.129
−
|I2S2_MCK
+
| -
−
|-
+
|NC
−
|Pin AF6
+
| -
−
|SAI3_SD_B
+
| -
 +
| -
 +
|
 +
|
 +
|
 
|-
 
|-
−
|Pin AF8
+
|J1.131
−
|UART8_TX
+
|DGND
 +
|DGND
 +
| -
 +
| -
 +
|G
 +
|
 +
|
 +
|
 
|-
 
|-
−
|Pin AF12
+
| rowspan="5" |J1.133
−
|FMC_NBL1
+
| rowspan="5" |ADP5589_R7
 +
| rowspan="5" |EXP.R7
 +
| rowspan="5" |1
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin AF0
 +
|TBD
 
|-
 
|-
−
|Pin AF13
 
−
|DCMI_D3
 
−
|-
 
−
|Pin AF15
 
−
|EVENTOUT
 
−
|-
 
−
| rowspan="10" |J1.193
 
−
| rowspan="10" |PE0
 
−
| rowspan="10" |CPU.PE0
 
−
| rowspan="10" |C4
 
−
| rowspan="10" |VDD
 
−
| rowspan="10" |I/O
 
−
| rowspan="10" |
 
 
|Pin AF1
 
|Pin AF1
−
|LPTIM1_ETR
+
|TBD
 
|-
 
|-
 
|Pin AF2
 
|Pin AF2
−
|TIM4_ETR
+
|TBD
 
|-
 
|-
−
|Pin AF4
+
|Pin AF3
−
|LPTIM2_ETR
+
|TBD
 
|-
 
|-
 
|Pin AF5
 
|Pin AF5
−
|SPI3_SCK/I2S3_CK
+
|TBD
 
|-
 
|-
−
|Pin AF6
+
| rowspan="5" |J1.135
−
|SAI4_MCLK_B
+
| rowspan="5" |ADP5589_R6
 +
| rowspan="5" |EXP.R6
 +
| rowspan="5" |2
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin AF0
 +
|TBD
 
|-
 
|-
−
|Pin AF8
+
|Pin AF1
−
|UART8_RX
+
|TBD
 
|-
 
|-
−
|Pin AF10
+
|Pin AF2
−
|SAI2_MCLK_A
+
|TBD
 
|-
 
|-
−
|Pin AF12
+
|Pin AF3
−
|FMC_NBL0
+
|TBD
 
|-
 
|-
−
|Pin AF13
+
|Pin AF5
−
|DCMI_D2
+
|TBD
 
|-
 
|-
−
|Pin AF15
+
| rowspan="5" |J1.137
−
|EVENTOUT
+
| rowspan="5" |ADP5589_R5
−
|-
+
| rowspan="5" |EXP.R5
−
|J1.195
+
| rowspan="5" |3
−
|PE2
+
| rowspan="5" |VDD
−
|CPU.PE2
+
| rowspan="5" |I/O
−
|T1
+
| rowspan="5" |TBD
−
|VDD
 
−
|I/O
 
−
|internally used for
 
−
PMIC I2C
 
−
|Pin AF4
 
−
|I2C4_SCL
 
−
|-
 
−
|J1.197
 
−
 
 
−
(LAN PHY on board)
 
−
|PA13
 
−
|CPU.PA13
 
−
|P2
 
−
|VDD
 
−
|I/O
 
−
|internally used for LAN PHY,
 
−
 
 
−
do not connect
 
−
|
 
−
|
 
−
|-
 
−
| rowspan="6" |J1.197
 
−
| rowspan="6" |PA13
 
−
| rowspan="6" |CPU.PA13
 
−
| rowspan="6" |P2
 
−
| rowspan="6" |VDD
 
−
| rowspan="6" |I/O
 
−
| rowspan="6" |
 
 
|Pin AF0
 
|Pin AF0
−
|DBTRGO
+
|TBD
 
|-
 
|-
 
|Pin AF1
 
|Pin AF1
−
|DBTRGI
+
|TBD
 
|-
 
|-
 
|Pin AF2
 
|Pin AF2
−
|MCO1
+
|TBD
 
|-
 
|-
−
|Pin AF8
+
|Pin AF3
−
|UART4_TX
+
|TBD
 
|-
 
|-
−
|Pin AF15
+
|Pin AF5
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
|Additional
+
| rowspan="5" |J1.139
−
functions
+
| rowspan="5" |ADP5589_R4
−
|BOOTFAILN
+
| rowspan="5" |EXP.R4
 +
| rowspan="5" |4
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin AF0
 +
|TBD
 
|-
 
|-
−
|J1.199
+
|Pin AF1
−
 
+
|TBD
−
(NAND on board)
 
−
|PD14
 
−
|CPU.PD14
 
−
|F3
 
−
|VDD
 
−
|I/O
 
−
|internally used for NAND flash,
 
−
 
 
−
do not connect
 
−
|
 
−
|
 
 
|-
 
|-
−
| rowspan="5" |J1.199
 
−
| rowspan="5" |PD14
 
−
| rowspan="5" |CPU.PD14
 
−
| rowspan="5" |F3
 
−
| rowspan="5" |VDD
 
−
| rowspan="5" |I/O
 
−
| rowspan="5" |internally used for
 
−
NAND flash
 
 
|Pin AF2
 
|Pin AF2
−
|TIM4_CH3
+
|TBD
 
|-
 
|-
−
|Pin AF6
+
|Pin AF3
−
|SAI3_MCLK_B
+
|TBD
 
|-
 
|-
−
|Pin AF8
+
|Pin AF5
−
|UART8_CTS
+
|TBD
 
|-
 
|-
−
|Pin AF12
+
| rowspan="5" |J1.141
−
|FMC_AD0/FMC_D0
+
| rowspan="5" |ADP5589_R3
 +
| rowspan="5" |EXP.R3
 +
| rowspan="5" |5
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin AF0
 +
|TBD
 +
|-
 +
|Pin AF1
 +
|TBD
 +
|-
 +
|Pin AF2
 +
|TBD
 
|-
 
|-
−
|Pin AF15
+
|Pin AF3
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
|J1.201
+
|Pin AF5
−
(NAND on board)
+
|TBD
−
|PD15
 
−
|CPU.PD15
 
−
|G1
 
−
|VDD
 
−
|I/O
 
−
|internally used for NAND flash,
 
−
 
 
−
do not connect
 
−
|
 
−
|
 
 
|-
 
|-
−
| rowspan="5" |J1.201
+
| rowspan="5" |J1.143
−
| rowspan="5" |PD15
+
| rowspan="5" |ADP5589_R2
−
| rowspan="5" |CPU.PD15
+
| rowspan="5" |EXP.R2
−
| rowspan="5" |G1
+
| rowspan="5" |6
 
| rowspan="5" |VDD
 
| rowspan="5" |VDD
 
| rowspan="5" |I/O
 
| rowspan="5" |I/O
−
| rowspan="5" |internally used for
+
| rowspan="5" |TBD
−
NAND flash
+
|Pin AF0
 +
|TBD
 +
|-
 +
|Pin AF1
 +
|TBD
 +
|-
 
|Pin AF2
 
|Pin AF2
−
|TIM4_CH4
+
|TBD
 
|-
 
|-
−
|Pin AF6
+
|Pin AF3
−
|SAI3_MCLK_A
+
|TBD
 
|-
 
|-
−
|Pin AF8
+
|Pin AF5
−
|UART8_CTS
+
|TBD
 
|-
 
|-
−
|Pin AF12
+
| rowspan="5" |J1.145
−
|FMC_AD1/FMC_D1
+
| rowspan="5" |ADP5589_R1
 +
| rowspan="5" |EXP.R1
 +
| rowspan="5" |7
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin AF0
 +
|TBD
 
|-
 
|-
−
|Pin AF15
+
|Pin AF1
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
|J1.203
+
|Pin AF2
−
|DGND
+
|TBD
−
|DGND
 
−
| -
 
−
| -
 
−
|G
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|}
+
|Pin AF3
−
 
+
|TBD
−
==Pinout Table EVEN  pins declaration ==
 
−
 
 
−
{| class="wikitable"
 
−
! latexfontsize="scriptsize" | Pin
 
−
! latexfontsize="scriptsize" | Pin Name
 
−
! latexfontsize="scriptsize" | Internal Connections
 
−
! latexfontsize="scriptsize" | Ball/pin #
 
−
! latexfontsize="scriptsize" | Voltage domain
 
−
! latexfontsize="scriptsize" | Type
 
−
! latexfontsize="scriptsize" | Notes
 
−
! colspan="2" latexfontsize="scriptsize" | Alternative Functions
 
 
|-
 
|-
−
|J1.2
+
|Pin AF5
−
|DGND
+
|TBD
−
|DGND
 
−
| -
 
−
| -
 
−
|G
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.4
+
| rowspan="5" |J1.147
−
|3.3VIN
+
| rowspan="5" |ADP5589_R0
−
|INPUT VOLTAGE
+
| rowspan="5" |EXP.R0
−
| -
+
| rowspan="5" |8
−
|3.3VIN
+
| rowspan="5" |VDD
−
|S
+
| rowspan="5" |I/O
−
|
+
| rowspan="5" |TBD
−
|
+
|Pin AF0
−
|
+
|TBD
 +
|-
 +
|Pin AF1
 +
|TBD
 +
|-
 +
|Pin AF2
 +
|TBD
 
|-
 
|-
−
|J1.6
+
|Pin AF3
−
|3.3VIN
+
|TBD
−
|INPUT VOLTAGE
 
−
| -
 
−
|3.3VIN
 
−
|S
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.8
+
|Pin AF5
−
|3.3VIN
+
|TBD
−
|INPUT VOLTAGE
 
−
| -
 
−
|3.3VIN
 
−
|S
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.10
+
| rowspan="5" |J1.149
−
|3.3VIN
+
| rowspan="5" |ADP5589_C0
−
|INPUT VOLTAGE
+
| rowspan="5" |EXP.C0
−
| -
+
| rowspan="5" |9
−
|3.3VIN
+
| rowspan="5" |VDD
−
|S
+
| rowspan="5" |I/O
−
|
+
| rowspan="5" |TBD
−
|
+
|Pin AF0
−
|
+
|TBD
 +
|-
 +
|Pin AF1
 +
|TBD
 +
|-
 +
|Pin AF2
 +
|TBD
 +
|-
 +
|Pin AF3
 +
|TBD
 +
|-
 +
|Pin AF5
 +
|TBD
 +
|-
 +
| rowspan="5" |J1.151
 +
| rowspan="5" |ADP5589_C1
 +
| rowspan="5" |EXP.C1
 +
| rowspan="5" |10
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin AF0
 +
|TBD
 +
|-
 +
|Pin AF1
 +
|TBD
 +
|-
 +
|Pin AF2
 +
|TBD
 +
|-
 +
|Pin AF3
 +
|TBD
 +
|-
 +
|Pin AF5
 +
|TBD
 
|-
 
|-
−
|J1.12
+
|J1.153
 
|DGND
 
|DGND
 
|DGND
 
|DGND
Line 2,488: Line 2,308:
 
|
 
|
 
|-
 
|-
−
|J1.14
+
| rowspan="5" |J1.155
−
|VBAT
+
| rowspan="5" |ADP5589_C2
−
|CPU.VBAT
+
| rowspan="5" |EXP.C2
−
|H3
+
| rowspan="5" |11
−
|VBAT
+
| rowspan="5" |VDD
−
|S
+
| rowspan="5" |I/O
−
|BACKUP VOLTAGE
+
| rowspan="5" |TBD
−
|
+
|Pin AF0
−
|
+
|TBD
 
|-
 
|-
−
|J1.16
+
|Pin AF1
−
|PONKEYn
+
|TBD
−
|PMIC.PONKEYN
 
−
|17
 
−
|3.3VIN
 
−
|I
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.18
+
|Pin AF2
−
|SOM_PGOOD
+
|TBD
−
| -
 
−
| -
 
−
|VDD
 
−
|O
 
−
|internally connected to VDD
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.20
+
|Pin AF3
−
|BOOT_MODE0
+
|TBD
−
|CPU.BOOT0
 
−
|K1
 
−
|VDD
 
−
|I
 
−
|internal pull-up or pull-down
 
−
according to specific model
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.22
+
|Pin AF5
−
|PWR_ON
+
|TBD
−
|CPU.PWR_ON
+
|-
−
|L1
+
| rowspan="5" |J1.157
−
|VDD
+
| rowspan="5" |ADP5589_C3
−
|O
+
| rowspan="5" |EXP.C3
−
|
+
| rowspan="5" |12
−
|
+
| rowspan="5" |VDD
−
|
+
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin AF0
 +
|TBD
 
|-
 
|-
−
|J1.24
+
|Pin AF1
−
|NRST
+
|TBD
−
|CPU.NRST
 
−
PMIC.RSTN
 
−
 
 
−
eMMC.RST_n
 
−
 
 
−
NOR.NRESET
 
−
|J1
 
−
1
 
−
 
 
−
K5
 
−
 
 
−
A4
 
−
|VDD
 
−
|I/O
 
−
|internal 10k pull-up to VDD
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.26
+
|Pin AF2
−
|BOOT_MODE1
+
|TBD
−
|CPU.BOOT1
+
|-
−
|K4
+
|Pin AF3
−
|VDD
+
|TBD
−
|I
+
|-
−
|internal pull-up or pull-down
+
|Pin AF5
−
according to specific model
+
|TBD
−
|
+
|-
−
|
+
| rowspan="5" |J1.159
 +
| rowspan="5" |ADP5589_C4
 +
| rowspan="5" |EXP.C4
 +
| rowspan="5" |13
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin AF0
 +
|TBD
 
|-
 
|-
−
| rowspan="9" |J1.28
 
−
| rowspan="9" |PA9
 
−
| rowspan="9" |CPU.PA9
 
−
| rowspan="9" |C8
 
−
| rowspan="9" |VDD
 
−
| rowspan="9" |I/O
 
−
| rowspan="9" |
 
 
|Pin AF1
 
|Pin AF1
−
|TIM1_CH2
+
|TBD
 
|-
 
|-
−
|Pin AF4
+
|Pin AF2
−
|I2C3_SMBA
+
|TBD
 +
|-
 +
|Pin AF3
 +
|TBD
 
|-
 
|-
 
|Pin AF5
 
|Pin AF5
−
|SPI2_SCK/I2S2_CK
+
|TBD
 
|-
 
|-
−
|Pin AF7
+
| rowspan="5" |J1.161
−
|USART1_TX
+
| rowspan="5" |ADP5589_C5
 +
| rowspan="5" |EXP.C5
 +
| rowspan="5" |14
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin AF0
 +
|TBD
 
|-
 
|-
−
|Pin AF8
+
|Pin AF1
−
|SDMMC2_CDIR
+
|TBD
 
|-
 
|-
−
|Pin AF10
+
|Pin AF2
−
|SDMMC2_D5
+
|TBD
 
|-
 
|-
−
|Pin AF13
+
|Pin AF3
−
|DCMI_D0
+
|TBD
 
|-
 
|-
−
|Pin AF14
+
|Pin AF5
−
|LCD_R5
+
|TBD
 
|-
 
|-
−
|Pin AF15
+
| rowspan="5" |J1.163
−
|EVENTOUT
+
| rowspan="5" |ADP5589_C6
−
|-
+
| rowspan="5" |EXP.C6
−
|J1.30
+
| rowspan="5" |15
−
|DGND
+
| rowspan="5" |VDD
−
|DGND
+
| rowspan="5" |I/O
−
| -
+
| rowspan="5" |TBD
−
| -
+
|Pin AF0
−
|G
+
|TBD
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.32
+
|Pin AF1
−
|WAKEUP
+
|TBD
−
|PMIC.WAKEUP
 
−
|2
 
−
|VINTLDO
 
−
|I
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
| rowspan="10" |J1.34
+
|Pin AF2
−
| rowspan="10" |PB13
+
|TBD
−
| rowspan="10" |CPU.PB13
 
−
| rowspan="10" |T9
 
−
| rowspan="10" |VDD
 
−
| rowspan="10" |I/O
 
−
| rowspan="10" |
 
−
|Pin AF1
 
−
|TIM1_CH1N
 
 
|-
 
|-
 
|Pin AF3
 
|Pin AF3
−
|DFSDM1_CKOUT
+
|TBD
−
|-
 
−
|Pin AF4
 
−
|LPTIM2_OUT
 
 
|-
 
|-
 
|Pin AF5
 
|Pin AF5
−
|SPI2_SCK/I2S2_CK
+
|TBD
 
|-
 
|-
−
|Pin AF6
+
| rowspan="5" |J1.165
−
|DFSDM1_CKIN1
+
| rowspan="5" |ADP5589_C7
 +
| rowspan="5" |EXP.C7
 +
| rowspan="5" |16
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin AF0
 +
|TBD
 
|-
 
|-
−
|Pin AF7
+
|Pin AF1
−
|USART3_CTS/USART3_NSS
+
|TBD
 
|-
 
|-
−
|Pin AF9
+
|Pin AF2
−
|FDCAN2_TX
+
|TBD
 
|-
 
|-
−
|Pin AF11
+
|Pin AF3
−
|ETH1_GMII_TXD1/
+
|TBD
−
 
 
−
ETH1_MII_TXD1/
 
−
 
 
−
ETH1_RGMII_TXD1/
 
−
 
 
−
ETH1_RMII_TXD1
 
 
|-
 
|-
−
|Pin AF14
+
|Pin AF5
−
|UART5_TX
+
|TBD
 
|-
 
|-
−
|Pin AF15
+
| rowspan="5" |J1.167
−
|EVENTOUT
+
| rowspan="5" |ADP5589_C8
−
|-
+
| rowspan="5" |EXP.C8
−
|J1.36
+
| rowspan="5" |19
−
|BOOT_MODE2
+
| rowspan="5" |VDD
−
|CPU-BOOT2
+
| rowspan="5" |I/O
−
|L2
+
| rowspan="5" |TBD
−
|VDD
+
|Pin AF0
−
|I
+
|TBD
−
|internal pull-up or pull-down
 
−
according to specific model
 
−
|
 
−
|
 
 
|-
 
|-
−
| rowspan="10" |J1.38
 
−
| rowspan="10" |PA11
 
−
| rowspan="10" |CPU.PA11
 
−
| rowspan="10" |V17
 
−
| rowspan="10" |VDD
 
−
| rowspan="10" |I/O
 
−
| rowspan="10" |
 
 
|Pin AF1
 
|Pin AF1
−
|TIM1_CH4
+
|TBD
 
|-
 
|-
 
|Pin AF2
 
|Pin AF2
−
|I2C6_SCL
+
|TBD
 
|-
 
|-
−
|Pin AF4
+
|Pin AF3
−
|I2C5_SCL
+
|TBD
 
|-
 
|-
 
|Pin AF5
 
|Pin AF5
−
|SPI2_NSS/I2S2_WS
+
|TBD
 
|-
 
|-
−
|Pin AF6
+
| rowspan="5" |J1.169
−
|UART4_RX
+
| rowspan="5" |ADP5589_C9
 +
| rowspan="5" |EXP.C9
 +
| rowspan="5" |20
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin AF0
 +
|TBD
 
|-
 
|-
−
|Pin AF7
+
|Pin AF1
−
|USART1_CTS/USART1_NSS
+
|TBD
 
|-
 
|-
−
|Pin AF9
+
|Pin AF2
−
|FDCAN1_RX
+
|TBD
 
|-
 
|-
−
|Pin AF14
+
|Pin AF3
−
|LCD_R4
+
|TBD
 
|-
 
|-
−
|Pin AF15
+
|Pin AF5
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
|Additional
+
| rowspan="5" |J1.171
−
functions
+
| rowspan="5" |ADP5589_C10
−
|OTG_FS_DM
+
| rowspan="5" |EXP.C10
 +
| rowspan="5" |21
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin AF0
 +
|TBD
 
|-
 
|-
−
|J1.40
+
|Pin AF1
−
|NAND_WP#
+
|TBD
−
|NAND.WPn
+
|-
−
|19
+
|Pin AF2
−
|VDD
+
|TBD
−
|I/O
+
|-
−
|internal pull-up to VDD
+
|Pin AF3
 +
|TBD
 +
|-
 +
|Pin AF5
 +
|TBD
 +
|-
 +
|J1.173
 +
| -
 +
|NC
 +
| -
 +
| -
 +
| -
 +
|
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.42
+
|J1.175
−
 
+
|DGND
−
(NOR on board)
+
|DGND
−
|PB6
+
| -
−
|CPU.PB6
+
| -
−
|T12
+
|G
−
|VDD
+
|
−
|I/O
 
−
|internally used for NOR flash.
 
−
do not connect
 
 
|
 
|
 
|
 
|
 
|-
 
|-
−
| rowspan="12" |J1.42
+
| rowspan="16" |J1.177
−
| rowspan="12" |PB6
+
| rowspan="16" |PE9
−
| rowspan="12" |CPU.PB6
+
| rowspan="16" |CPU.PE9
−
| rowspan="12" |T12
+
| rowspan="16" |W7
−
| rowspan="12" |VDD
+
| rowspan="16" |VDD
−
| rowspan="12" |I/O
+
| rowspan="16" |I/O
−
| rowspan="12" |
+
| rowspan="16" |TBD
 +
|Pin AF0
 +
|TBD
 +
|-
 
|Pin AF1
 
|Pin AF1
−
|TIM16_CH1N
+
|TBD
 
|-
 
|-
 
|Pin AF2
 
|Pin AF2
−
|TIM4_CH1
+
|TBD
 +
|-
 +
|Pin AF3
 +
|TBD
 
|-
 
|-
 
|Pin AF4
 
|Pin AF4
−
|I2C1_SCL
+
|TBD
 
|-
 
|-
 
|Pin AF5
 
|Pin AF5
−
|CEC
+
|TBD
 
|-
 
|-
 
|Pin AF6
 
|Pin AF6
−
|I2C4_SCL
+
|TBD
 
|-
 
|-
 
|Pin AF7
 
|Pin AF7
−
|USART1_TX
+
|TBD
 +
|-
 +
|Pin AF8
 +
|TBD
 
|-
 
|-
 
|Pin AF9
 
|Pin AF9
−
|FDCAN2_TX
+
|TBD
 
|-
 
|-
 
|Pin AF10
 
|Pin AF10
−
|QUADSPI_BK1_NCS
+
|TBD
 
|-
 
|-
 
|Pin AF11
 
|Pin AF11
−
|DFSDM1_DATIN5
+
|TBD
 
|-
 
|-
 
|Pin AF12
 
|Pin AF12
−
|UART5_TX
+
|TBD
 
|-
 
|-
 
|Pin AF13
 
|Pin AF13
−
|DCMI_D5
+
|TBD
 +
|-
 +
|Pin AF14
 +
|TBD
 
|-
 
|-
 
|Pin AF15
 
|Pin AF15
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
|J1.44
+
| rowspan="16" |J1.179
−
|PB7
+
| rowspan="16" |PC3
−
|CPU.PB7
+
| rowspan="16" |CPU.PC3
−
|B5
+
| rowspan="16" |T3
−
|VDD
+
| rowspan="16" |VDD
−
|I/O
+
| rowspan="16" |I/O
−
|internally used for
+
| rowspan="16" |TBD
−
PMIC I2C
+
|Pin AF0
−
|Pin AF6
+
|TBD
−
|I2C1_SDA
 
 
|-
 
|-
−
| rowspan="9" |J1.46
 
−
| rowspan="9" |PE14
 
−
| rowspan="9" |CPU.PE14
 
−
| rowspan="9" |D3
 
−
| rowspan="9" |VDD
 
−
| rowspan="9" |I/O
 
−
| rowspan="9" |
 
 
|Pin AF1
 
|Pin AF1
−
|TIM1_CH4
+
|TBD
 +
|-
 +
|Pin AF2
 +
|TBD
 +
|-
 +
|Pin AF3
 +
|TBD
 +
|-
 +
|Pin AF4
 +
|TBD
 
|-
 
|-
 
|Pin AF5
 
|Pin AF5
−
|SPI4_MOSI
+
|TBD
 +
|-
 +
|Pin AF6
 +
|TBD
 +
|-
 +
|Pin AF7
 +
|TBD
 
|-
 
|-
 
|Pin AF8
 
|Pin AF8
−
|UART8_RTS/UART8_DE
+
|TBD
 +
|-
 +
|Pin AF9
 +
|TBD
 
|-
 
|-
 
|Pin AF10
 
|Pin AF10
−
|SAI2_MCLK_B
+
|TBD
 
|-
 
|-
 
|Pin AF11
 
|Pin AF11
−
|SDMMC1_D123DIR
+
|TBD
 
|-
 
|-
 
|Pin AF12
 
|Pin AF12
−
|FMC_AD11/FMC_D11
+
|TBD
 
|-
 
|-
 
|Pin AF13
 
|Pin AF13
−
|LCD_G0
+
|TBD
 
|-
 
|-
 
|Pin AF14
 
|Pin AF14
−
|LCD_CLK
+
|TBD
 
|-
 
|-
 
|Pin AF15
 
|Pin AF15
−
|EVENTOUT
+
|TBD
 +
|-
 +
| rowspan="16" |J1.181
 +
| rowspan="16" |PD6
 +
| rowspan="16" |CPU.PD6
 +
| rowspan="16" |E3
 +
| rowspan="16" |VDD
 +
| rowspan="16" |I/O
 +
| rowspan="16" |TBD
 +
|Pin AF0
 +
|TBD
 
|-
 
|-
−
| rowspan="10" |J1.48
 
−
| rowspan="10" |PA12
 
−
| rowspan="10" |CPU.PA12
 
−
| rowspan="10" |U16
 
−
| rowspan="10" |VDD
 
−
| rowspan="10" |I/O
 
−
| rowspan="10" |
 
 
|Pin AF1
 
|Pin AF1
−
|TIM1_ETR
+
|TBD
 
|-
 
|-
 
|Pin AF2
 
|Pin AF2
−
|I2C6_SDA
+
|TBD
 +
|-
 +
|Pin AF3
 +
|TBD
 
|-
 
|-
 
|Pin AF4
 
|Pin AF4
−
|I2C5_SDA
+
|TBD
 +
|-
 +
|Pin AF5
 +
|TBD
 
|-
 
|-
 
|Pin AF6
 
|Pin AF6
−
|UART4_TX
+
|TBD
 
|-
 
|-
 
|Pin AF7
 
|Pin AF7
−
|USART1_RTS/USART1_DE
+
|TBD
 
|-
 
|-
 
|Pin AF8
 
|Pin AF8
−
|SAI2_FS_B
+
|TBD
 
|-
 
|-
 
|Pin AF9
 
|Pin AF9
−
|FDCAN1_TX
+
|TBD
 
|-
 
|-
−
|Pin AF14
+
|Pin AF10
−
|LCD_R5
+
|TBD
 
|-
 
|-
−
|Pin AF15
+
|Pin AF11
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
|Additional
+
|Pin AF12
−
functions
+
|TBD
−
|OTG_FS_DP
 
 
|-
 
|-
−
|J1.50
+
|Pin AF13
−
|BST_OUT
+
|TBD
−
|PMIC.BST_OUT
+
|-
−
|34
+
|Pin AF14
−
|BST_OUT
+
|TBD
−
|S
 
−
|BOOST OUTPUT
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.52
+
|Pin AF15
−
|BST_OUT
+
|TBD
−
|PMIC.BST_OUT
 
−
|34
 
−
|BST_OUT
 
−
|S
 
−
|BOOST OUTPUT
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.54
+
| rowspan="16" |J1.183
−
|PMIC_INT#
+
| rowspan="16" |PE10
−
|PMIC-INTN
+
| rowspan="16" |CPU.PE10
−
|43
+
| rowspan="16" |V10
−
|VDD
+
| rowspan="16" |VDD
−
|O
+
| rowspan="16" |I/O
−
|
+
| rowspan="16" |TBD
−
|
+
|Pin AF0
−
|
+
|TBD
−
|-
 
−
|J1.56
 
−
|DGND
 
−
|DGND
 
−
| -
 
−
| -
 
−
|G
 
−
|
 
−
|
 
−
|
 
−
|-
 
−
| rowspan="4" |J1.58
 
−
| rowspan="4" |PA14
 
−
| rowspan="4" |CPU.PA14
 
−
| rowspan="4" |R1
 
−
| rowspan="4" |VDD
 
−
| rowspan="4" |I/O
 
−
| rowspan="4" |
 
−
|Pin AF0
 
−
|DBTRGO
 
 
|-
 
|-
 
|Pin AF1
 
|Pin AF1
−
|DBTRGI
+
|TBD
 
|-
 
|-
 
|Pin AF2
 
|Pin AF2
−
|MCO2
+
|TBD
 +
|-
 +
|Pin AF3
 +
|TBD
 
|-
 
|-
−
|Pin AF15
+
|Pin AF4
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
|J1.60
+
|Pin AF5
−
|VDD
+
|TBD
−
|VOLTAGE OUTPUT
 
−
| -
 
−
|VDD
 
−
|S
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.62
+
|Pin AF6
−
|VDD
+
|TBD
−
|VOLTAGE OUTPUT
 
−
| -
 
−
|VDD
 
−
|S
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.64
+
|Pin AF7
−
|1V8
+
|TBD
−
|PMIC.LDO6OUT
 
−
|21
 
−
|1V8
 
−
|S
 
−
|Spare LDO output
 
−
|
 
−
|
 
−
|-
 
−
| rowspan="11" |J1.66
 
−
| rowspan="11" |PG12
 
−
| rowspan="11" |CPU.PG12
 
−
| rowspan="11" |F1
 
−
| rowspan="11" |VDD
 
−
| rowspan="11" |I/O
 
−
| rowspan="11" |
 
−
|Pin AF1
 
−
|LPTIM1_IN1
 
−
|-
 
−
|Pin AF5
 
−
|SPI6_MISO
 
−
|-
 
−
|Pin AF6
 
−
|SAI4_CK2
 
−
|-
 
−
|Pin AF7
 
−
|USART6_RTS/USART6_DE
 
 
|-
 
|-
 
|Pin AF8
 
|Pin AF8
−
|SPDIFRX_IN2
+
|TBD
 
|-
 
|-
 
|Pin AF9
 
|Pin AF9
−
|LCD_B4
+
|TBD
 
|-
 
|-
 
|Pin AF10
 
|Pin AF10
−
|SAI4_SCK_A
+
|TBD
 
|-
 
|-
 
|Pin AF11
 
|Pin AF11
−
|ETH1_PHY_INTN
+
|TBD
 
|-
 
|-
 
|Pin AF12
 
|Pin AF12
−
|FMC_NE4
+
|TBD
 +
|-
 +
|Pin AF13
 +
|TBD
 
|-
 
|-
 
|Pin AF14
 
|Pin AF14
−
|LCD_B1
+
|TBD
 
|-
 
|-
 
|Pin AF15
 
|Pin AF15
−
|EVENTOUT
+
|TBD
 +
|-
 +
|J1.185
 +
|VBUS_OTG_OUT
 +
|PMIC.VBUSOTG
 +
|35
 +
|VBUSOTG
 +
|S
 +
|USB OTG VOUT
 +
|
 +
|
 
|-
 
|-
−
| rowspan="16" |J1.68
+
| rowspan="16" |J1.187
−
| rowspan="16" |PB5
+
| rowspan="16" |PG11
−
| rowspan="16" |CPU.PB5
+
| rowspan="16" |CPU.PG11
−
| rowspan="16" |T8
+
| rowspan="16" |V6
 
| rowspan="16" |VDD
 
| rowspan="16" |VDD
 
| rowspan="16" |I/O
 
| rowspan="16" |I/O
−
| rowspan="16" |
+
| rowspan="16" |TBD
 
|Pin AF0
 
|Pin AF0
−
|ETH_CLK
+
|TBD
 
|-
 
|-
 
|Pin AF1
 
|Pin AF1
−
|TIM17_BKIN
+
|TBD
 
|-
 
|-
 
|Pin AF2
 
|Pin AF2
−
|TIM3_CH2
+
|TBD
 
|-
 
|-
 
|Pin AF3
 
|Pin AF3
−
|SAI4_D1
+
|TBD
 
|-
 
|-
 
|Pin AF4
 
|Pin AF4
−
|I2C1_SMBA
+
|TBD
 
|-
 
|-
 
|Pin AF5
 
|Pin AF5
−
|SPI1_MOSI/I2S1_SDO
+
|TBD
 
|-
 
|-
 
|Pin AF6
 
|Pin AF6
−
|I2C4_SMBA
+
|TBD
 
|-
 
|-
 
|Pin AF7
 
|Pin AF7
−
|SPI3_MOSI/I2S3_SDO
+
|TBD
 
|-
 
|-
 
|Pin AF8
 
|Pin AF8
−
|SPI6_MOSI
+
|TBD
 
|-
 
|-
 
|Pin AF9
 
|Pin AF9
−
|FDCAN2_RX
+
|TBD
 
|-
 
|-
 
|Pin AF10
 
|Pin AF10
−
|SAI4_SD_A
+
|TBD
 
|-
 
|-
 
|Pin AF11
 
|Pin AF11
−
|ETH1_PPS_OUT
+
|TBD
 
|-
 
|-
 
|Pin AF12
 
|Pin AF12
−
|UART5_RX
+
|TBD
 
|-
 
|-
 
|Pin AF13
 
|Pin AF13
−
|DCMI_D10
+
|TBD
 
|-
 
|-
 
|Pin AF14
 
|Pin AF14
−
|LCD_G7
+
|TBD
 
|-
 
|-
 
|Pin AF15
 
|Pin AF15
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
| rowspan="13" |J1.70
+
| rowspan="16" |J1.189
−
| rowspan="13" |PG8
+
| rowspan="16" |PB2
−
| rowspan="13" |CPU.PG8
+
| rowspan="16" |CPU.PB2
−
| rowspan="13" |U7
+
| rowspan="16" |T13
−
| rowspan="13" |VDD
+
| rowspan="16" |VDD
−
| rowspan="13" |I/O
+
| rowspan="16" |I/O
−
| rowspan="13" |
+
| rowspan="16" |TBD
 
|Pin AF0
 
|Pin AF0
−
|TRACED15
+
|TBD
 
|-
 
|-
 
|Pin AF1
 
|Pin AF1
−
|TIM2_CH1/TIM2_ETR
+
|TBD
 
|-
 
|-
 
|Pin AF2
 
|Pin AF2
−
|ETH_CLK
+
|TBD
 
|-
 
|-
 
|Pin AF3
 
|Pin AF3
−
|TIM8_ETR
+
|TBD
 +
|-
 +
|Pin AF4
 +
|TBD
 
|-
 
|-
 
|Pin AF5
 
|Pin AF5
−
|SPI6_NSS
+
|TBD
 
|-
 
|-
 
|Pin AF6
 
|Pin AF6
−
|SAI4_D2
+
|TBD
 
|-
 
|-
 
|Pin AF7
 
|Pin AF7
−
|USART6_RTS/USART6_DE
+
|TBD
 
|-
 
|-
 
|Pin AF8
 
|Pin AF8
−
|USART3_RTS/USART3_DE
+
|TBD
 
|-
 
|-
 
|Pin AF9
 
|Pin AF9
−
|SPDIFRX_IN3
+
|TBD
 
|-
 
|-
 
|Pin AF10
 
|Pin AF10
−
|SAI4_FS_A
+
|TBD
 
|-
 
|-
 
|Pin AF11
 
|Pin AF11
−
|ETH1_PPS_OUT
+
|TBD
 +
|-
 +
|Pin AF12
 +
|TBD
 +
|-
 +
|Pin AF13
 +
|TBD
 
|-
 
|-
 
|Pin AF14
 
|Pin AF14
−
|LCD_G7
+
|TBD
 
|-
 
|-
 
|Pin AF15
 
|Pin AF15
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
| rowspan="13" |J1.72
+
| rowspan="16" |J1.191
−
| rowspan="13" |PA8
+
| rowspan="16" |PE1
−
| rowspan="13" |CPU.PA8
+
| rowspan="16" |CPU.PE1
−
| rowspan="13" |B8
+
| rowspan="16" |B1
−
| rowspan="13" |VDD
+
| rowspan="16" |VDD
−
| rowspan="13" |I/O
+
| rowspan="16" |I/O
−
| rowspan="13" |
+
| rowspan="16" |TBD
 
|Pin AF0
 
|Pin AF0
−
|MCO1
+
|TBD
 
|-
 
|-
 
|Pin AF1
 
|Pin AF1
−
|TIM1_CH1
+
|TBD
 +
|-
 +
|Pin AF2
 +
|TBD
 
|-
 
|-
 
|Pin AF3
 
|Pin AF3
−
|TIM8_BKIN2
+
|TBD
 
|-
 
|-
 
|Pin AF4
 
|Pin AF4
−
|I2C3_SCL
+
|TBD
 
|-
 
|-
 
|Pin AF5
 
|Pin AF5
−
|SPI3_MOSI/I2S3_SDO
+
|TBD
 +
|-
 +
|Pin AF6
 +
|TBD
 
|-
 
|-
 
|Pin AF7
 
|Pin AF7
−
|USART1_CK
+
|TBD
 
|-
 
|-
 
|Pin AF8
 
|Pin AF8
−
|SDMMC2_CKIN
+
|TBD
 
|-
 
|-
 
|Pin AF9
 
|Pin AF9
−
|SDMMC2_D4
+
|TBD
 
|-
 
|-
 
|Pin AF10
 
|Pin AF10
−
|OTG_FS_SOF/OTG_HS_SOF
+
|TBD
 +
|-
 +
|Pin AF11
 +
|TBD
 
|-
 
|-
 
|Pin AF12
 
|Pin AF12
−
|SAI4_SD_B
+
|TBD
 
|-
 
|-
 
|Pin AF13
 
|Pin AF13
−
|UART7_RX
+
|TBD
 
|-
 
|-
 
|Pin AF14
 
|Pin AF14
−
|LCD_R6
+
|TBD
 
|-
 
|-
 
|Pin AF15
 
|Pin AF15
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
|J1.74
+
| rowspan="16" |J1.193
−
 
+
| rowspan="16" |PE0
−
(NOR on board)
+
| rowspan="16" |CPU.PE0
−
|PF7
+
| rowspan="16" |C4
−
|CPU.PF7
+
| rowspan="16" |VDD
−
|W8
+
| rowspan="16" |I/O
−
|VDD
+
| rowspan="16" |TBD
−
|I/O
+
|Pin AF0
−
|internally used for NOR flash.
+
|TBD
−
do not connect
 
−
|
 
−
|
 
 
|-
 
|-
−
| rowspan="6" |J1.74
 
−
| rowspan="6" |PF7
 
−
| rowspan="6" |CPU.PF7
 
−
| rowspan="6" |W8
 
−
| rowspan="6" |VDD
 
−
| rowspan="6" |I/O
 
−
| rowspan="6" |
 
 
|Pin AF1
 
|Pin AF1
−
|TIM17_CH1
+
|TBD
 +
|-
 +
|Pin AF2
 +
|TBD
 +
|-
 +
|Pin AF3
 +
|TBD
 +
|-
 +
|Pin AF4
 +
|TBD
 
|-
 
|-
 
|Pin AF5
 
|Pin AF5
−
|SPI5_SCK
+
|TBD
 
|-
 
|-
 
|Pin AF6
 
|Pin AF6
−
|SAI1_MCLK_B
+
|TBD
 
|-
 
|-
 
|Pin AF7
 
|Pin AF7
−
|UART7_TX
+
|TBD
 +
|-
 +
|Pin AF8
 +
|TBD
 
|-
 
|-
 
|Pin AF9
 
|Pin AF9
−
|QUADSPI_BK1_IO2
+
|TBD
 
|-
 
|-
−
|Pin AF15
+
|Pin AF10
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
|J1.76
+
|Pin AF11
−
 
+
|TBD
−
(NOR on board)
 
−
|PF9
 
−
|CPU.PF9
 
−
|W9
 
−
|VDD
 
−
|I/O
 
−
|internally used for NOR flash.
 
−
 
 
−
do not connect
 
−
|
 
−
|
 
 
|-
 
|-
−
| rowspan="8" |J1.76
+
|Pin AF12
−
| rowspan="8" |PF9
+
|TBD
−
| rowspan="8" |CPU.PF9
 
−
| rowspan="8" |W9
 
−
| rowspan="8" |VDD
 
−
| rowspan="8" |I/O
 
−
| rowspan="8" |
 
−
|Pin AF0
 
−
|TRACED13
 
 
|-
 
|-
−
|Pin AF1
+
|Pin AF13
−
|TIM17_CH1N
+
|TBD
 
|-
 
|-
−
|Pin AF5
+
|Pin AF14
−
|SPI5_MOSI
+
|TBD
 
|-
 
|-
−
|Pin AF6
+
|Pin AF15
−
|SAI1_FS_B
+
|TBD
 
|-
 
|-
−
|Pin AF7
+
| rowspan="16" |J1.195
−
|UART7_CTS
+
| rowspan="16" |PE2
 +
| rowspan="16" |CPU.PE2
 +
| rowspan="16" |T1
 +
| rowspan="16" |VDD
 +
| rowspan="16" |I/O
 +
| rowspan="16" |TBD
 +
|Pin AF0
 +
|TBD
 
|-
 
|-
−
|Pin AF9
+
|Pin AF1
−
|TIM14_CH1
+
|TBD
 
|-
 
|-
−
|Pin AF10
+
|Pin AF2
−
|QUADSPI_BK1_IO1
+
|TBD
 
|-
 
|-
−
|Pin AF15
+
|Pin AF3
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
|J1.78
+
|Pin AF4
−
 
+
|TBD
−
(NOR on board)
 
−
|PF8
 
−
|CPU.PF8
 
−
|U10
 
−
|VDD
 
−
|I/O
 
−
|internally used for NOR flash.
 
−
 
 
−
do not connect
 
−
|
 
−
|
 
−
|-
 
−
| rowspan="8" |J1.78
 
−
| rowspan="8" |PF8
 
−
| rowspan="8" |CPU.PF8
 
−
| rowspan="8" |U10
 
−
| rowspan="8" |VDD
 
−
| rowspan="8" |I/O
 
−
| rowspan="8" |
 
−
|Pin AF0
 
−
|TRACED12
 
−
|-
 
−
|Pin AF1
 
−
|TIM16_CH1N
 
 
|-
 
|-
 
|Pin AF5
 
|Pin AF5
−
|SPI5_MISO
+
|TBD
 
|-
 
|-
 
|Pin AF6
 
|Pin AF6
−
|SAI1_SCK_B
+
|TBD
 
|-
 
|-
 
|Pin AF7
 
|Pin AF7
−
|UART7_RTS/UART7_DE
+
|TBD
 +
|-
 +
|Pin AF8
 +
|TBD
 
|-
 
|-
 
|Pin AF9
 
|Pin AF9
−
|TIM13_CH1
+
|TBD
 
|-
 
|-
 
|Pin AF10
 
|Pin AF10
−
|QUADSPI_BK1_IO0
+
|TBD
 +
|-
 +
|Pin AF11
 +
|TBD
 +
|-
 +
|Pin AF12
 +
|TBD
 +
|-
 +
|Pin AF13
 +
|TBD
 +
|-
 +
|Pin AF14
 +
|TBD
 
|-
 
|-
 
|Pin AF15
 
|Pin AF15
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
|J1.80
+
| rowspan="16" |J1.197
−
 
+
| rowspan="16" |PA13
−
(NOR on board)
+
| rowspan="16" |CPU.PA13
−
|PF6
+
| rowspan="16" |P2
−
|CPU.PF6
+
| rowspan="16" |VDD
−
|V9
+
| rowspan="16" |I/O
−
|VDD
+
| rowspan="16" |TBD
−
|I/O
+
|Pin AF0
−
|internally used for NOR flash.
+
|TBD
−
 
 
−
do not connect
 
−
|
 
−
|
 
 
|-
 
|-
−
| rowspan="7" |J1.80
 
−
| rowspan="7" |PF6
 
−
| rowspan="7" |CPU.PF6
 
−
| rowspan="7" |V9
 
−
| rowspan="7" |VDD
 
−
| rowspan="7" |I/O
 
−
| rowspan="7" |
 
 
|Pin AF1
 
|Pin AF1
−
|TIM16_CH1
+
|TBD
 +
|-
 +
|Pin AF2
 +
|TBD
 +
|-
 +
|Pin AF3
 +
|TBD
 +
|-
 +
|Pin AF4
 +
|TBD
 
|-
 
|-
 
|Pin AF5
 
|Pin AF5
−
|SPI5_NSS
+
|TBD
 
|-
 
|-
 
|Pin AF6
 
|Pin AF6
−
|SAI1_SD_B
+
|TBD
 
|-
 
|-
 
|Pin AF7
 
|Pin AF7
−
|UART7_RX
+
|TBD
 +
|-
 +
|Pin AF8
 +
|TBD
 
|-
 
|-
 
|Pin AF9
 
|Pin AF9
−
|QUADSPI_BK1_IO3
+
|TBD
 +
|-
 +
|Pin AF10
 +
|TBD
 +
|-
 +
|Pin AF11
 +
|TBD
 
|-
 
|-
 
|Pin AF12
 
|Pin AF12
−
|SAI4_SCK_B
+
|TBD
 +
|-
 +
|Pin AF13
 +
|TBD
 +
|-
 +
|Pin AF14
 +
|TBD
 
|-
 
|-
 
|Pin AF15
 
|Pin AF15
−
|EVENTOUT
+
|TBD
 +
|-
 +
| rowspan="16" |J1.199
 +
| rowspan="16" |PD14
 +
| rowspan="16" |CPU.PD14
 +
| rowspan="16" |F3
 +
| rowspan="16" |VDD
 +
| rowspan="16" |I/O
 +
| rowspan="16" |TBD
 +
|Pin AF0
 +
|TBD
 
|-
 
|-
−
|J1.82
+
|Pin AF1
−
|DGND
+
|TBD
−
|DGND
+
|-
−
| -
+
|Pin AF2
−
| -
+
|TBD
−
|G
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.84
+
|Pin AF3
−
|PMIC_3V3
+
|TBD
−
|VOLTAGE OUTPUT
 
−
| -
 
−
|PMIC_3V3
 
−
|S
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.86
+
|Pin AF4
−
|PMIC_3V3
+
|TBD
−
|VOLTAGE OUTPUT
 
−
| -
 
−
|PMIC_3V3
 
−
|S
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.88
+
|Pin AF5
−
|PMIC_3V3
+
|TBD
−
|VOLTAGE OUTPUT
 
−
| -
 
−
|PMIC_3V3
 
−
|S
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.90
+
|Pin AF6
−
|JTMS-SWDIO
+
|TBD
−
|CPU.JTMS-SWDIO
+
|-
−
|D15
+
|Pin AF7
−
|VDD
+
|TBD
−
|I/O
+
|-
−
|
+
|Pin AF8
−
|
+
|TBD
−
|
 
 
|-
 
|-
−
|J1.92
+
|Pin AF9
−
|JTDI
+
|TBD
−
|CPU.JTDI
 
−
|D13
 
−
|VDD
 
−
|I/O
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.94
+
|Pin AF10
−
|NJTRST
+
|TBD
−
|CPU.NJTRST
 
−
|D12
 
−
|VDD
 
−
|I/O
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.96
+
|Pin AF11
−
|JTDO-TRACESWOO
+
|TBD
−
|CPU.JTDO-TRACESWOO
+
|-
−
|D14
+
|Pin AF12
−
|VDD
+
|TBD
−
|I/O
+
|-
−
|
+
|Pin AF13
−
|
+
|TBD
−
|
 
 
|-
 
|-
−
|J1.98
+
|Pin AF14
−
|JTCK-SWCLK
+
|TBD
−
|CPU.JTCK-SWCLK
 
−
|D16
 
−
|VDD
 
−
|I/O
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.100
+
|Pin AF15
−
|DGND
+
|TBD
−
|DGND
 
−
| -
 
−
| -
 
−
|G
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.102
+
| rowspan="16" |J1.201
−
|NRST_CORE
+
| rowspan="16" |PD15
−
|CPU.NRST_CORE
+
| rowspan="16" |CPU.PD15
−
|J2
+
| rowspan="16" |G1
−
|VDD
+
| rowspan="16" |VDD
−
|I
+
| rowspan="16" |I/O
−
|internally connected to NRST
+
| rowspan="16" |TBD
−
|
+
|Pin AF0
−
|
+
|TBD
 +
|-
 +
|Pin AF1
 +
|TBD
 +
|-
 +
|Pin AF2
 +
|TBD
 
|-
 
|-
−
|J1.104
+
|Pin AF3
−
|PDR_ON
+
|TBD
−
|CPU.PDR_ON
 
−
|N2
 
−
|VDD
 
−
|I
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.106
+
|Pin AF4
−
|PDR_ON_CORE
+
|TBD
−
|CPU.PDR_ON_CORE
 
−
|N1
 
−
|VDD
 
−
|I
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.108
+
|Pin AF5
−
|PWR_LP
+
|TBD
−
|CPU.PWR_LP
+
|-
−
|P1
+
|Pin AF6
−
|VDD
+
|TBD
−
|O
+
|-
−
|
+
|Pin AF7
−
|
+
|TBD
−
|
+
|-
 +
|Pin AF8
 +
|TBD
 +
|-
 +
|Pin AF9
 +
|TBD
 +
|-
 +
|Pin AF10
 +
|TBD
 +
|-
 +
|Pin AF11
 +
|TBD
 +
|-
 +
|Pin AF12
 +
|TBD
 +
|-
 +
|Pin AF13
 +
|TBD
 +
|-
 +
|Pin AF14
 +
|TBD
 +
|-
 +
|Pin AF15
 +
|TBD
 
|-
 
|-
−
|J1.110
+
|J1.203
−
| -
+
|DGND
−
|NC
+
|DGND
−
| -
 
 
| -
 
| -
 
| -
 
| -
 +
|G
 
|
 
|
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.112
+
|}
−
| -
+
 
−
|NC
+
==Pinout Table EVEN  pins declaration ==
−
| -
+
 
 +
{| class="wikitable"
 +
! latexfontsize="scriptsize" | Pin
 +
! latexfontsize="scriptsize" | Pin Name
 +
! latexfontsize="scriptsize" | Internal Connections
 +
! latexfontsize="scriptsize" | Ball/pin #
 +
! latexfontsize="scriptsize" | Voltage domain
 +
! latexfontsize="scriptsize" | Type
 +
! latexfontsize="scriptsize" | Notes
 +
! colspan="2" latexfontsize="scriptsize" | Alternative Functions
 +
|-
 +
|J1.2
 +
|DGND
 +
|DGND
 
| -
 
| -
 
| -
 
| -
 +
|G
 
|
 
|
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.114
+
|J1.4
−
| -
+
|3.3VIN
−
|NC
+
|INPUT VOLTAGE
−
| -
 
−
| -
 
 
| -
 
| -
 +
|3.3VIN
 +
|S
 
|
 
|
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.116
+
|J1.6
−
| -
+
|3.3VIN
−
|NC
+
|INPUT VOLTAGE
−
| -
 
−
| -
 
 
| -
 
| -
 +
|3.3VIN
 +
|S
 
|
 
|
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.118
+
|J1.8
−
| -
+
|3.3VIN
−
|NC
+
|INPUT VOLTAGE
−
| -
 
−
| -
 
 
| -
 
| -
 +
|3.3VIN
 +
|S
 
|
 
|
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.120
+
|J1.10
−
| -
+
|3.3VIN
−
|NC
+
|INPUT VOLTAGE
−
| -
 
−
| -
 
 
| -
 
| -
 +
|3.3VIN
 +
|S
 
|
 
|
 
|
 
|
 
|
 
|
 
|-
 
|-
−
|J1.122
+
|J1.12
 
|DGND
 
|DGND
 
|DGND
 
|DGND
Line 3,521: Line 3,280:
 
|
 
|
 
|-
 
|-
−
| rowspan="9" |J1.124
+
|J1.14
−
| rowspan="9" |PE13
+
|VBAT
−
| rowspan="9" |CPU.PE13
+
|CPU.VBAT
−
| rowspan="9" |C2
+
|H3
−
| rowspan="9" |VDD
+
|VBAT
−
| rowspan="9" |I/O
+
|S
−
| rowspan="9" |
+
|BACKUP VOLTAGE
−
|Pin AF0
+
|
−
|HDP2
+
|
 
|-
 
|-
−
|Pin AF1
+
|J1.16
−
|TIM1_CH3
+
|PONKEYn
 +
|PMIC.PONKEYN
 +
|17
 +
|3.3VIN
 +
|I
 +
|
 +
|
 +
|
 
|-
 
|-
−
|Pin AF3
+
|J1.18
−
|DFSDM1_CKIN5
+
|SOM_PGOOD
−
|-
+
| -
−
|Pin AF5
+
| -
−
|SPI4_MISO
 
−
|-
 
−
|Pin AF10
 
−
|SAI2_FS_B
 
−
|-
 
−
|Pin AF12
 
−
|FMC_AD10/FMC_D10
 
−
|-
 
−
|Pin AF13
 
−
|DCMI_D6
 
−
|-
 
−
|Pin AF14
 
−
|LCD_DE
 
−
|-
 
−
|Pin AF15
 
−
|EVENTOUT
 
−
|-
 
−
|J1.126
 
−
|PC13
 
−
|CPU.PC13
 
−
|K3
 
 
|VDD
 
|VDD
−
|I/O
+
|O
−
|internally used for PMIC,
+
|
−
do not connect
 
 
|
 
|
 
|
 
|
 
|-
 
|-
−
| rowspan="12" |J1.128
+
|J1.20
−
| rowspan="12" |PA4
+
|BOOT_MODE0
−
| rowspan="12" |CPU.PA4
+
|CPU.BOOT0
−
| rowspan="12" |R4
+
|K1
−
| rowspan="12" |VDD
+
|VDD
−
| rowspan="12" |I/O
+
|I
−
| rowspan="12" |
+
|internall pull-up or pull-down
−
|Pin AF0
+
according to specific model
−
|HDP0
+
|
−
|-
+
|
−
|Pin AF2
 
−
|TIM5_ETR
 
 
|-
 
|-
−
|Pin AF4
+
|J1.22
−
|SAI4_D2
+
|PWR_ON
−
|-
+
|CPU.PWR_ON
−
|Pin AF5
+
|L1
−
|SPI1_NSS/I2S1_WS
 
−
|-
 
−
|Pin AF6
 
−
|SPI3_NSS/I2S3_WS
 
−
|-
 
−
|Pin AF7
 
−
|USART2_CK
 
−
|-
 
−
|Pin AF8
 
−
|SPI6_NSS
 
−
|-
 
−
|Pin AF12
 
−
|SAI4_FS_A
 
−
|-
 
−
|Pin AF13
 
−
|DCMI_HSYNC
 
−
|-
 
−
|Pin AF14
 
−
|LCD_VSYNC
 
−
|-
 
−
|Pin AF15
 
−
|EVENTOUT
 
−
|-
 
−
|Additional
 
−
functions
 
−
|ADC1_INP18
 
−
 
 
−
ADC2_INP18
 
−
 
 
−
DAC_OUT1
 
−
|-
 
−
|J1.130
 
−
 
 
−
(eMMC 8-bit
 
−
 
 
−
on board)
 
−
|PC6_OPT
 
−
|CPU.PC6
 
−
|D10
 
 
|VDD
 
|VDD
−
|I/O
+
|O
−
|internally used for eMMC,
+
|
−
do not connect
 
 
|
 
|
 
|
 
|
 
|-
 
|-
−
| rowspan="14" |J1.130
+
|J1.24
−
| rowspan="14" |PC6_OPT
+
|NRST
−
| rowspan="14" | CPU.PC6
+
|CPU.NRST
−
| rowspan="14" | D10
+
PMIC.RSTN
−
| rowspan="14" |VDD
+
 
−
| rowspan="14" |I/O
+
eMMC.RST_n
−
| rowspan="14" |
+
 
−
|Pin AF0
+
NOR.NRESET
−
|HDP1
+
|J1
 +
1
 +
 
 +
K5
 +
 
 +
A4
 +
|VDD
 +
|I/O
 +
|TBD
 +
|
 +
|
 
|-
 
|-
−
|Pin AF2
+
|J1.26
−
|TIM3_CH1
+
|BOOT_MODE1
 +
|CPU.BOOT1
 +
|K4
 +
|VDD
 +
|I
 +
|internall pull-up or pull-down
 +
according to specific model
 +
|
 +
|
 
|-
 
|-
−
|Pin AF3
+
| rowspan="5" |J1.28
−
|TIM8_CH1
+
| rowspan="5" |PA9
 +
| rowspan="5" |CPU.PA9
 +
| rowspan="5" |C8
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin AF4
+
|Pin ALT-1
−
|DFSDM1_CKIN3
+
|TBD
 
|-
 
|-
−
|Pin AF5
+
|Pin ALT-2
−
|I2S2_MCK
+
|TBD
 
|-
 
|-
−
|Pin AF7
+
|Pin ALT-3
−
|USART6_TX
+
|TBD
 
|-
 
|-
−
|Pin AF8
+
|Pin ALT-5
−
|SDMMC1_D0DIR
+
|TBD
 
|-
 
|-
−
|Pin AF9
+
|J1.30
−
|SDMMC2_D0DIR
+
|DGND
 +
|DGND
 +
| -
 +
| -
 +
|G
 +
|
 +
|
 +
|
 
|-
 
|-
−
|Pin AF10
+
|J1.32
−
|SDMMC2_D6
+
|WAKEUP
 +
|PMIC.WAKEUP
 +
|2
 +
|VINTLDO
 +
|I
 +
|
 +
|
 +
|
 
|-
 
|-
−
|Pin AF11
+
| rowspan="5" |J1.34
−
|DSI_TE
+
| rowspan="5" |PB13
−
|-
+
| rowspan="5" |CPU.PB13
−
|Pin AF12
+
| rowspan="5" |T9
−
|SDMMC1_D6
+
| rowspan="5" |VDD
−
|-
+
| rowspan="5" |I/O
−
|Pin AF13
+
| rowspan="5" |TBD
−
|DCMI_D0
+
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin AF14
+
|Pin ALT-1
−
|LCD_HSYNC
+
|TBD
 
|-
 
|-
−
|Pin AF15
+
|Pin ALT-2
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
| rowspan="9" |J1.132
+
|Pin ALT-3
−
| rowspan="9" |PG7
+
|TBD
−
| rowspan="9" |CPU.PG7
 
−
| rowspan="9" |W10
 
−
| rowspan="9" |VDD
 
−
| rowspan="9" |I/O
 
−
| rowspan="9" |
 
−
|Pin AF0
 
−
|TRACED5
 
 
|-
 
|-
−
|Pin AF6
+
|Pin ALT-5
−
|SAI1_MCLK_A
+
|TBD
 
|-
 
|-
−
|Pin AF7
+
|J1.36
−
|USART6_CK
+
|BOOT_MODE2
 +
|CPU-BOOT2
 +
|L2
 +
|VDD
 +
|I
 +
|internall pull-up or pull-down
 +
according to specific model
 +
|
 +
|
 
|-
 
|-
−
|Pin AF8
+
| rowspan="5" |J1.38
−
|UART8_RTS/UART8_DE
+
| rowspan="5" |PA11
 +
| rowspan="5" |CPU.PA11
 +
| rowspan="5" |V17
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin AF9
+
|Pin ALT-1
−
|QUADSPI_CLK
+
|TBD
 
|-
 
|-
−
|Pin AF11
+
|Pin ALT-2
−
|QUADSPI_BK2_IO3
+
|TBD
 
|-
 
|-
−
|Pin AF13
+
|Pin ALT-3
−
|DCMI_D13
+
|TBD
 
|-
 
|-
−
|Pin AF14
+
|Pin ALT-5
−
|LCD_CLK
+
|TBD
 
|-
 
|-
−
|Pin AF15
+
|J1.40
−
|EVENTOUT
+
|MEM_WP#
 +
|NAND.NWP
 +
NOR.NWP
 +
|19
 +
C4
 +
|VDD
 +
|I
 +
|internal pull-up to VDD
 +
|
 +
|
 
|-
 
|-
−
| rowspan="9" |J1.134
+
| rowspan="5" |J1.42
−
| rowspan="9" |PG10
+
| rowspan="5" |PB6
−
| rowspan="9" |CPU.PG10
+
| rowspan="5" |CPU.PB6
−
| rowspan="9" |V7
+
| rowspan="5" |T12
−
| rowspan="9" |VDD
+
| rowspan="5" |VDD
−
| rowspan="9" |I/O
+
| rowspan="5" |I/O
−
| rowspan="9" |
+
| rowspan="5" |TBD
−
|Pin AF0
+
|Pin ALT-0
−
|TRACED10
+
|TBD
 
|-
 
|-
−
|Pin AF8
+
|Pin ALT-1
−
|UART8_CTS
+
|TBD
 
|-
 
|-
−
|Pin AF9
+
|Pin ALT-2
−
|LCD_G3
+
|TBD
 
|-
 
|-
−
|Pin AF10
+
|Pin ALT-3
−
|SAI2_SD_B
+
|TBD
 
|-
 
|-
−
|Pin AF11
+
|Pin ALT-5
−
|QUADSPI_BK2_IO2
+
|TBD
 
|-
 
|-
−
|Pin AF12
+
| rowspan="5" |J1.44
−
|FMC_NE3
+
| rowspan="5" |PB7
 +
| rowspan="5" |CPU.PB7
 +
| rowspan="5" |B5
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin AF13
+
|Pin ALT-1
−
|DCMI_D2
+
|TBD
 
|-
 
|-
−
|Pin AF14
+
|Pin ALT-2
−
|LCD_B2
+
|TBD
 
|-
 
|-
−
|Pin AF15
+
|Pin ALT-3
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
| rowspan="10" |J1.136
+
|Pin ALT-5
−
| rowspan="10" |PD10
+
|TBD
−
| rowspan="10" |CPU.PD10
 
−
| rowspan="10" |C5
 
−
| rowspan="10" |VDD
 
−
| rowspan="10" |I/O
 
−
| rowspan="10" |
 
−
|Pin AF0
 
−
|RTC_REFIN
 
 
|-
 
|-
−
|Pin AF1
+
| rowspan="5" |J1.46
−
|TIM16_BKIN
+
| rowspan="5" |PE14
 +
| rowspan="5" |CPU.PE14
 +
| rowspan="5" |D3
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin AF3
+
|Pin ALT-1
−
|DFSDM1_CKOUT
+
|TBD
 
|-
 
|-
−
|Pin AF4
+
|Pin ALT-2
−
|I2C5_SMBA
+
|TBD
 
|-
 
|-
−
|Pin AF5
+
|Pin ALT-3
−
|SPI3_MISO/I2S3_SDI
+
|TBD
 
|-
 
|-
−
|Pin AF6
+
|Pin ALT-5
−
|SAI3_FS_B
+
|TBD
 
|-
 
|-
−
|Pin AF7
+
| rowspan="5" |J1.48
−
|USART3_CK
+
| rowspan="5" |PA12
 +
| rowspan="5" |CPU.PA12
 +
| rowspan="5" |U16
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin AF12
+
|Pin ALT-1
−
|FMC_AD15/FMC_D15
+
|TBD
 
|-
 
|-
−
|Pin AF14
+
|Pin ALT-2
−
|LCD_B3
+
|TBD
 
|-
 
|-
−
|Pin AF15
+
|Pin ALT-3
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
| rowspan="8" |J1.138
+
|Pin ALT-5
−
| rowspan="8" |PE12
+
|TBD
−
| rowspan="8" |CPU.PE12
 
−
| rowspan="8" |D2
 
−
| rowspan="8" |VDD
 
−
| rowspan="8" |I/O
 
−
| rowspan="8" |
 
−
|Pin AF1
 
−
|TIM1_CH3N
 
 
|-
 
|-
−
|Pin AF3
+
|J1.50
−
|DFSDM1_DATIN5
+
|BST_OUT
 +
|PMIC.BST_OUT
 +
|34
 +
|BST_OUT
 +
|S
 +
|BOOST OUTPUT
 +
|
 +
|
 
|-
 
|-
−
|Pin AF5
+
|J1.52
−
|SPI4_SCK
+
|BST_OUT
 +
|PMIC.BST_OUT
 +
|34
 +
|BST_OUT
 +
|S
 +
|BOOST OUTPUT
 +
|
 +
|
 
|-
 
|-
−
|Pin AF8
+
|J1.54
−
|SDMMC1_D0DIR
+
|PMIC_INT#
−
|-
+
|PMIC-INTN
−
|Pin AF10
+
|43
−
|SAI2_SCK_B
+
|VDD
 +
|O
 +
|
 +
|
 +
|
 
|-
 
|-
−
|Pin AF12
+
|J1.56
−
|FMC_AD9/FMC_D9
+
|DGND
 +
|DGND
 +
| -
 +
| -
 +
|G
 +
|
 +
|
 +
|
 
|-
 
|-
−
|Pin AF14
+
| rowspan="5" |J1.58
−
|LCD_B4
+
| rowspan="5" |PA14
 +
| rowspan="5" |CPU.PA14
 +
| rowspan="5" |R1
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin AF15
+
|Pin ALT-1
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
| rowspan="10" |J1.140
+
|Pin ALT-2
−
| rowspan="10" |PA3
+
|TBD
−
| rowspan="10" |CPU.PA3
 
−
| rowspan="10" |P3
 
−
| rowspan="10" |VDD
 
−
| rowspan="10" |I/O
 
−
| rowspan="10" |
 
−
|Pin AF1
 
−
|TIM2_CH4
 
 
|-
 
|-
−
|Pin AF2
+
|Pin ALT-3
−
|TIM5_CH4
+
|TBD
 
|-
 
|-
−
|Pin AF3
+
|Pin ALT-5
−
|LPTIM5_OUT
+
|TBD
 
|-
 
|-
−
|Pin AF4
+
|J1.60
−
|TIM15_CH2
+
|VDD
 +
|VOLTAGE OUTPUT
 +
| -
 +
|VDD
 +
|S
 +
|
 +
|
 +
|
 
|-
 
|-
−
|Pin AF7
+
|J1.62
−
|USART2_RX
+
|VDD
 +
|VOLTAGE OUTPUT
 +
| -
 +
|VDD
 +
|S
 +
|
 +
|
 +
|
 
|-
 
|-
−
|Pin AF9
+
|J1.64
−
|LCD_B2
+
|1V8
 +
|PMIC.LDO6OUT
 +
|21
 +
|1V8
 +
|S
 +
|Spare LDO output
 +
|
 +
|
 
|-
 
|-
−
|Pin AF11
+
| rowspan="5" |J1.66
−
|ETH1_GMII_COL/
+
| rowspan="5" |PG12
−
 
+
| rowspan="5" |CPU.PG12
−
ETH1_MII_COL
+
| rowspan="5" |F1
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin AF14
+
|Pin ALT-1
−
|LCD_B5
+
|TBD
 
|-
 
|-
−
|Pin AF15
+
|Pin ALT-2
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
|Additional
+
|Pin ALT-3
−
functions
+
|TBD
−
|ADC1_INP15
 
−
 
 
−
PVD_IN
 
 
|-
 
|-
−
| rowspan="16" |J1.142
+
|Pin ALT-5
−
| rowspan="16" |PB8
+
|TBD
−
| rowspan="16" |CPU.PB8
 
−
| rowspan="16" |W6
 
−
| rowspan="16" |VDD
 
−
| rowspan="16" |I/O
 
−
| rowspan="16" |
 
−
|Pin AF0
 
−
|HDP6
 
 
|-
 
|-
−
|Pin AF1
+
| rowspan="5" |J1.68
−
|TIM16_CH1
+
| rowspan="5" |PB5
 +
| rowspan="5" |CPU.PB5
 +
| rowspan="5" |T8
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin AF2
+
|Pin ALT-1
−
|TIM4_CH3
+
|TBD
 
|-
 
|-
−
|Pin AF3
+
|Pin ALT-2
−
|DFSDM1_CKIN7
+
|TBD
 
|-
 
|-
−
|Pin AF4
+
|Pin ALT-3
−
|I2C1_SCL
+
|TBD
 
|-
 
|-
−
|Pin AF5
+
|Pin ALT-5
−
|SDMMC1_CKIN
+
|TBD
 
|-
 
|-
−
|Pin AF6
+
| rowspan="5" |J1.70
−
|I2C4_SCL
+
| rowspan="5" |PG8
 +
| rowspan="5" |CPU.PG8
 +
| rowspan="5" |U7
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin AF7
+
|Pin ALT-1
−
|SDMMC2_CKIN
+
|TBD
 
|-
 
|-
−
|Pin AF8
+
|Pin ALT-2
−
|UART4_RX
+
|TBD
 
|-
 
|-
−
|Pin AF9
+
|Pin ALT-3
−
|FDCAN1_RX
+
|TBD
 
|-
 
|-
−
|Pin AF10
+
|Pin ALT-5
−
|SDMMC2_D4
+
|TBD
 
|-
 
|-
−
|Pin AF11
+
| rowspan="5" |J1.72
−
|ETH1_GMII_TXD3/
+
| rowspan="5" |PA8
−
 
+
| rowspan="5" |CPU.PA8
−
ETH1_MII_TXD3/
+
| rowspan="5" |B8
−
 
+
| rowspan="5" |VDD
−
ETH1_RGMII_TXD3
+
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin AF12
+
|Pin ALT-1
−
|SDMMC1_D4
+
|TBD
 
|-
 
|-
−
|Pin AF13
+
|Pin ALT-2
−
|DCMI_D6
+
|TBD
 
|-
 
|-
−
|Pin AF14
+
|Pin ALT-3
−
|LCD_B6
+
|TBD
 
|-
 
|-
−
|Pin AF15
+
|Pin ALT-5
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
| rowspan="16" |J1.144
+
| rowspan="5" |J1.74
−
| rowspan="16" |PB9
+
| rowspan="5" |PF7
−
| rowspan="16" |CPU.PB9
+
| rowspan="5" |CPU.PF7
−
| rowspan="16" |D9
+
| rowspan="5" |W8
−
| rowspan="16" |VDD
+
| rowspan="5" |VDD
−
| rowspan="16" |I/O
+
| rowspan="5" |I/O
−
| rowspan="16" |
+
| rowspan="5" |TBD
−
|Pin AF0
+
|Pin ALT-0
−
|HDP7
+
|TBD
 
|-
 
|-
−
|Pin AF1
+
|Pin ALT-1
−
|TIM17_CH1
+
|TBD
 
|-
 
|-
−
|Pin AF2
+
|Pin ALT-2
−
|TIM4_CH4
+
|TBD
 
|-
 
|-
−
|Pin AF3
+
|Pin ALT-3
−
|DFSDM1_DATIN7
+
|TBD
 
|-
 
|-
−
|Pin AF4
+
|Pin ALT-5
−
|I2C1_SDA
+
|TBD
 
|-
 
|-
−
|Pin AF5
+
| rowspan="5" |J1.76
−
|SPI2_NSS/I2S2_WS
+
| rowspan="5" |PF9
 +
| rowspan="5" |CPU.PF9
 +
| rowspan="5" |W9
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin AF6
+
|Pin ALT-1
−
|I2C4_SDA
+
|TBD
 
|-
 
|-
−
|Pin AF7
+
|Pin ALT-2
−
|SDMMC2_CDIR
+
|TBD
 
|-
 
|-
−
|Pin AF8
+
|Pin ALT-3
−
|UART4_TX
+
|TBD
 
|-
 
|-
−
|Pin AF9
+
|Pin ALT-5
−
|FDCAN1_TX
+
|TBD
 
|-
 
|-
−
|Pin AF10
+
| rowspan="5" |J1.78
−
|SDMMC2_D5
+
| rowspan="5" |PF8
 +
| rowspan="5" |CPU.PF8
 +
| rowspan="5" |U10
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin AF11
+
|Pin ALT-1
−
|SDMMC1_CDIR
+
|TBD
 +
|-
 +
|Pin ALT-2
 +
|TBD
 +
|-
 +
|Pin ALT-3
 +
|TBD
 +
|-
 +
|Pin ALT-5
 +
|TBD
 +
|-
 +
| rowspan="5" |J1.80
 +
| rowspan="5" |PF6
 +
| rowspan="5" |CPU.PF6
 +
| rowspan="5" |V9
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin AF12
+
|Pin ALT-1
−
|SDMMC1_D5
+
|TBD
 
|-
 
|-
−
|Pin AF13
+
|Pin ALT-2
−
|DCMI_D7
+
|TBD
 
|-
 
|-
−
|Pin AF14
+
|Pin ALT-3
−
|LCD_B7
+
|TBD
 
|-
 
|-
−
|Pin AF15
+
|Pin ALT-5
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
|J1.146
+
|J1.82
 
|DGND
 
|DGND
 
|DGND
 
|DGND
Line 3,980: Line 3,837:
 
|
 
|
 
|-
 
|-
−
| rowspan="13" |J1.148
+
|J1.84
−
| rowspan="13" |PA6
+
|PMIC_3V3
−
| rowspan="13" |CPU.PA6
+
|VOLTAGE OUTPUT
−
| rowspan="13" |T5
+
| -
−
| rowspan="13" |VDD
+
|PMIC_3V3
−
| rowspan="13" |I/O
+
|S
−
| rowspan="13" |
+
|
−
|Pin AF1
+
|
−
|TIM1_BKIN
+
|
 
|-
 
|-
−
|Pin AF2
+
|J1.86
−
|TIM3_CH1
+
|PMIC_3V3
 +
|VOLTAGE OUTPUT
 +
| -
 +
|PMIC_3V3
 +
|S
 +
|
 +
|
 +
|
 
|-
 
|-
−
|Pin AF3
+
|J1.88
−
|TIM8_BKIN
+
|PMIC_3V3
 +
|VOLTAGE OUTPUT
 +
| -
 +
|PMIC_3V3
 +
|S
 +
|
 +
|
 +
|
 
|-
 
|-
−
|Pin AF4
+
|J1.90
−
|SAI4_CK2
+
|JTMS-SWDIO
 +
|CPU.JTMS-SWDIO
 +
|D15
 +
|VDD
 +
|I/O
 +
|TBD
 +
|
 +
|
 
|-
 
|-
−
|Pin AF5
+
|J1.92
−
|SPI1_MISO/I2S1_SDI
+
|JTDI
 +
|CPU.JTDI
 +
|D13
 +
|VDD
 +
|I/O
 +
|TBD
 +
|
 +
|
 
|-
 
|-
−
|Pin AF8
+
|J1.94
−
|SPI6_MISO
+
|NJTRST
 +
|CPU.NJTRST
 +
|D12
 +
|VDD
 +
|I/O
 +
|TBD
 +
|
 +
|
 
|-
 
|-
−
|Pin AF9
+
|J1.96
−
|TIM13_CH1
+
|JTDO-TRACESWOO
 +
|CPU.JTDO-TRACESWOO
 +
|D14
 +
|VDD
 +
|I/O
 +
|TBD
 +
|
 +
|
 
|-
 
|-
−
|Pin AF11
+
|J1.98
−
|MDIOS_MDC
+
|JTCK-SWCLK
 +
|CPU.JTCK-SWCLK
 +
|D16
 +
|VDD
 +
|I/O
 +
|TBD
 +
|
 +
|
 
|-
 
|-
−
|Pin AF12
+
|J1.100
−
|SAI4_SCK_A
+
|DGND
 +
|DGND
 +
| -
 +
| -
 +
|G
 +
|
 +
|
 +
|
 
|-
 
|-
−
|Pin AF13
+
|J1.102
−
|DCMI_PIXCLK
+
|NRST_CORE
−
|-
+
|CPU.NRST_CORE
−
|Pin AF14
+
|J2
−
|LCD_G2
+
|VDD
−
|-
+
|I
−
|Pin AF15
+
|internally connected to NRST
−
|EVENTOUT
+
|
 +
|
 
|-
 
|-
−
|Additional
+
|J1.104
−
functions
+
|PDR_ON
−
|ADC1_INP3
+
|CPU.PDR_ON
−
 
+
|N2
−
ADC2_INP3
+
|VDD
 +
|I
 +
|
 +
|
 +
|
 
|-
 
|-
−
| rowspan="9" |J1.150
+
|J1.106
−
| rowspan="9" |PE11
+
|PDR_ON_CORE
−
| rowspan="9" |CPU.PE11
+
|CPU.PDR_ON_CORE
−
| rowspan="9" |C1
+
|N1
−
| rowspan="9" |VDD
+
|VDD
−
| rowspan="9" |I/O
+
|I
−
| rowspan="9" |
+
|
−
|Pin AF1
+
|
−
|TIM1_CH2
+
|
 
|-
 
|-
−
|Pin AF3
+
|J1.108
−
|DFSDM1_CKIN4
+
|PWR_LP
 +
|CPU.PWR_LP
 +
|P1
 +
|VDD
 +
|O
 +
|
 +
|
 +
|
 
|-
 
|-
−
|Pin AF5
+
|J1.110
−
|SPI4_NSS
+
| -
 +
|NC
 +
| -
 +
| -
 +
| -
 +
|
 +
|
 +
|
 
|-
 
|-
−
|Pin AF7
+
|J1.112
−
|USART6_CK
+
| -
 +
|NC
 +
| -
 +
| -
 +
| -
 +
|
 +
|
 +
|
 
|-
 
|-
−
|Pin AF10
+
|J1.114
−
|SAI2_SD_B
+
| -
 +
|NC
 +
| -
 +
| -
 +
| -
 +
|
 +
|
 +
|
 
|-
 
|-
−
|Pin AF12
+
|J1.116
−
|FMC_AD8/FMC_D8
+
| -
−
|-
+
|NC
−
|Pin AF13
+
| -
−
|DCMI_D4
+
| -
 +
| -
 +
|
 +
|
 +
|
 
|-
 
|-
−
|Pin AF14
+
|J1.118
−
|LCD_G3
+
| -
 +
|NC
 +
| -
 +
| -
 +
| -
 +
|
 +
|
 +
|
 
|-
 
|-
−
|Pin AF15
+
|J1.120
−
|EVENTOUT
+
| -
 +
|NC
 +
| -
 +
| -
 +
| -
 +
|
 +
|
 +
|
 
|-
 
|-
−
| rowspan="10" |J1.152
+
|J1.122
−
| rowspan="10" |PB10
+
|DGND
−
| rowspan="10" |CPU.PB10
+
|DGND
−
| rowspan="10" |W5
+
| -
−
| rowspan="10" |VDD
+
| -
−
| rowspan="10" |I/O
+
|G
−
| rowspan="10" |
+
|
−
|Pin AF1
+
|
−
|TIM2_CH3
+
|
 
|-
 
|-
−
|Pin AF3
+
| rowspan="5" |J1.124
−
|LPTIM2_IN1
+
| rowspan="5" |PE13
 +
| rowspan="5" |CPU.PE13
 +
| rowspan="5" |C2
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin AF4
+
|Pin ALT-1
−
|I2C2_SCL
+
|TBD
 
|-
 
|-
−
|Pin AF5
+
|Pin ALT-2
−
|SPI2_SCK/I2S2_CK
+
|TBD
 
|-
 
|-
−
|Pin AF6
+
|Pin ALT-3
−
|DFSDM1_DATIN7
+
|TBD
 
|-
 
|-
−
|Pin AF7
+
|Pin ALT-5
−
|USART3_TX
+
|TBD
 
|-
 
|-
−
|Pin AF9
+
| rowspan="5" |J1.126
−
|QUADSPI_BK1_NCS
+
| rowspan="5" |PC13
 +
| rowspan="5" |CPU.PC13
 +
| rowspan="5" |K3
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin AF11
+
|Pin ALT-1
−
|ETH1_GMII_RX_ER/
+
|TBD
−
 
 
−
ETH1_MII_RX_ER
 
 
|-
 
|-
−
|Pin AF14
+
|Pin ALT-2
−
|LCD_G4
+
|TBD
 
|-
 
|-
−
|Pin AF15
+
|Pin ALT-3
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
| rowspan="6" |J1.154
+
|Pin ALT-5
−
| rowspan="6" |PF11
+
|TBD
−
| rowspan="6" |CPU.PF11
 
−
| rowspan="6" |U5
 
−
| rowspan="6" |VDD
 
−
| rowspan="6" |I/O
 
−
| rowspan="6" |
 
−
|Pin AF5
 
−
|SPI5_MOS
 
 
|-
 
|-
−
|Pin AF10
+
| rowspan="5" |J1.128
−
|SAI2_SD_B
+
| rowspan="5" |PA4
 +
| rowspan="5" |CPU.PA4
 +
| rowspan="5" |R4
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin AF13
+
|Pin ALT-1
−
|DCMI_D12
+
|TBD
 
|-
 
|-
−
|Pin AF14
+
|Pin ALT-2
−
|LCD_G5
+
|TBD
 
|-
 
|-
−
|Pin AF15
+
|Pin ALT-3
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
|Additional
+
|Pin ALT-5
−
functions
+
|TBD
−
|ADC1_INP2
 
 
|-
 
|-
−
| rowspan="13" |J1.156
+
| rowspan="5" |J1.130
−
| rowspan="13" |PC7
+
| rowspan="5" |PC6_OPT
−
| rowspan="13" |CPU.PC7
+
| rowspan="5" | -
−
| rowspan="13" |A9
+
| rowspan="5" | -
−
| rowspan="13" |VDD
+
| rowspan="5" |VDD
−
| rowspan="13" |I/O
+
| rowspan="5" |I/O
−
| rowspan="13" |
+
| rowspan="5" |TBD
−
|Pin AF0
+
|Pin ALT-0
−
|HDP4
+
|TBD
 
|-
 
|-
−
|Pin AF2
+
|Pin ALT-1
−
|TIM3_CH2
+
|TBD
 
|-
 
|-
−
|Pin AF3
+
|Pin ALT-2
−
|TIM8_CH2
+
|TBD
 
|-
 
|-
−
|Pin AF4
+
|Pin ALT-3
−
|DFSDM1_DATIN3
+
|TBD
 
|-
 
|-
−
|Pin AF6
+
|Pin ALT-5
−
|I2S3_MCK
+
|TBD
 
|-
 
|-
−
|Pin AF7
+
| rowspan="5" |J1.132
−
|USART6_RX
+
| rowspan="5" |PG7
 +
| rowspan="5" |CPU.PG7
 +
| rowspan="5" |W10
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin AF8
+
|Pin ALT-1
−
|SDMMC1_D123DIR
+
|TBD
 
|-
 
|-
−
|Pin AF9
+
|Pin ALT-2
−
|SDMMC2_D123DIR
+
|TBD
 
|-
 
|-
−
|Pin AF10
+
|Pin ALT-3
−
|SDMMC2_D7
+
|TBD
 
|-
 
|-
−
|Pin AF12
+
|Pin ALT-5
−
|SDMMC1_D7
+
|TBD
 
|-
 
|-
−
|Pin AF13
+
| rowspan="5" |J1.134
−
|DCMI_D1
+
| rowspan="5" |PG10
 +
| rowspan="5" |CPU.PG10
 +
| rowspan="5" |V7
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin AF14
+
|Pin ALT-1
−
|LCD_G6
+
|TBD
 
|-
 
|-
−
|Pin AF15
+
|Pin ALT-2
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
|J1.158
+
|Pin ALT-3
−
 
+
|TBD
−
(eMMC 8-bit
 
−
 
 
−
on board)
 
−
|PD3_OPT
 
−
|CPU.PD3
 
−
|C6
 
−
|VDD
 
−
|I/O
 
−
|internally used for eMMC,
 
−
do not connect
 
−
|
 
−
|
 
 
|-
 
|-
−
| rowspan="13" |J1.158
+
|Pin ALT-5
−
| rowspan="13" |PD3_OPT
+
|TBD
−
| rowspan="13" | CPU.PD3
 
−
| rowspan="13" | C6
 
−
| rowspan="13" |VDD
 
−
| rowspan="13" |I/O
 
−
| rowspan="13" |
 
−
|Pin AF0
 
−
|HDP5
 
 
|-
 
|-
−
|Pin AF3
+
| rowspan="5" |J1.136
−
|DFSDM1_CKOUT
+
| rowspan="5" |PD10
 +
| rowspan="5" |CPU.PD10
 +
| rowspan="5" |C5
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin AF5
+
|Pin ALT-1
−
|SPI2_SCK/I2S2_CK
+
|TBD
 
|-
 
|-
−
|Pin AF6
+
|Pin ALT-2
−
|DFSDM1_DATIN0
+
|TBD
 
|-
 
|-
−
|Pin AF7
+
|Pin ALT-3
−
|USART2_CTS/USART2_NSS
+
|TBD
 
|-
 
|-
−
|Pin AF8
+
|Pin ALT-5
−
|SDMMC1_D123DIR
+
|TBD
 
|-
 
|-
−
|Pin AF9
+
| rowspan="5" |J1.138
−
|SDMMC2_D7
+
| rowspan="5" |PE12
 +
| rowspan="5" |CPU.PE12
 +
| rowspan="5" |D2
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin AF10
+
|Pin ALT-1
−
|SDMMC2_D123DIR
+
|TBD
 
|-
 
|-
−
|Pin AF11
+
|Pin ALT-2
−
|SDMMC1_D7
+
|TBD
 
|-
 
|-
−
|Pin AF12
+
|Pin ALT-3
−
|FMC_CLK
+
|TBD
 
|-
 
|-
−
|Pin AF13
+
|Pin ALT-5
−
|DCMI_D5
+
|TBD
 
|-
 
|-
−
|Pin AF14
+
| rowspan="5" |J1.140
−
|LCD_G7
+
| rowspan="5" |PA3
 +
| rowspan="5" |CPU.PA3
 +
| rowspan="5" |P3
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin AF15
+
|Pin ALT-1
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
| rowspan="11" |J1.160
+
|Pin ALT-2
−
| rowspan="11" |PC10
+
|TBD
−
| rowspan="11" |CPU.PC10
 
−
| rowspan="11" |D11
 
−
| rowspan="11" |VDD
 
−
| rowspan="11" |I/O
 
−
| rowspan="11" |
 
−
|Pin AF0
 
−
|TRACED2
 
 
|-
 
|-
−
|Pin AF3
+
|Pin ALT-3
−
|DFSDM1_CKIN5
+
|TBD
 
|-
 
|-
−
|Pin AF6
+
|Pin ALT-5
−
|SPI3_SCK/I2S3_CK
+
|TBD
 
|-
 
|-
−
|Pin AF7
+
| rowspan="5" |J1.142
−
|USART3_TX
+
| rowspan="5" |PB8
 +
| rowspan="5" |CPU.PB8
 +
| rowspan="5" |W6
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin AF8
+
|Pin ALT-1
−
|UART4_TX
+
|TBD
 
|-
 
|-
−
|Pin AF9
+
|Pin ALT-2
−
|QUADSPI_BK1_IO1
+
|TBD
 
|-
 
|-
−
|Pin AF10
+
|Pin ALT-3
−
|SAI4_MCLK_B
+
|TBD
 
|-
 
|-
−
|Pin AF12
+
|Pin ALT-5
−
|SDMMC1_D2
+
|TBD
 
|-
 
|-
−
|Pin AF13
+
| rowspan="5" |J1.144
−
|DCMI_D8
+
| rowspan="5" |PB9
−
|-
+
| rowspan="5" |CPU.PB9
−
|Pin AF14
+
| rowspan="5" |D9
−
|LCD_R2
+
| rowspan="5" |VDD
−
|-
+
| rowspan="5" |I/O
−
|Pin AF15
+
| rowspan="5" |TBD
−
|EVENTOUT
+
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
| rowspan="11" |J1.162
+
|Pin ALT-1
−
| rowspan="11" |PB0
+
|TBD
−
| rowspan="11" |CPU.PB0
 
−
| rowspan="11" |W3
 
−
| rowspan="11" |VDD
 
−
| rowspan="11" |I/O
 
−
| rowspan="11" |
 
−
|Pin AF1
 
−
|TIM1_CH2N
 
 
|-
 
|-
−
|Pin AF2
+
|Pin ALT-2
−
|TIM3_CH3
+
|TBD
 
|-
 
|-
−
|Pin AF3
+
|Pin ALT-3
−
|TIM8_CH2N
+
|TBD
 
|-
 
|-
−
|Pin AF6
+
|Pin ALT-5
−
|DFSDM1_CKOUT
+
|TBD
 
|-
 
|-
−
|Pin AF8
+
|J1.146
−
|UART4_CTS
 
−
|-
 
−
|Pin AF9
 
−
|LCD_R3
 
−
|-
 
−
|Pin AF11
 
−
|ETH1_GMII_RXD2/
 
−
 
 
−
ETH1_MII_RXD2/
 
−
 
 
−
ETH1_RGMII_RXD2
 
−
|-
 
−
|Pin AF12
 
−
|MDIOS_MDIO
 
−
|-
 
−
|Pin AF14
 
−
|LCD_G1
 
−
|-
 
−
|Pin AF15
 
−
|EVENTOUT
 
−
|-
 
−
|Additional
 
−
functions
 
−
|ADC1_INP9
 
−
 
 
−
ADC1_INN5
 
−
 
 
−
ADC2_INP9
 
−
 
 
−
ADC2_INN5
 
−
|-
 
−
|J1.164
 
 
|DGND
 
|DGND
 
|DGND
 
|DGND
Line 4,336: Line 4,289:
 
|
 
|
 
|-
 
|-
−
| rowspan="9" |J1.166
+
| rowspan="5" |J1.148
−
| rowspan="9" |PA5
+
| rowspan="5" |PA6
−
| rowspan="9" |CPU.PA5
+
| rowspan="5" |CPU.PA6
−
| rowspan="9" |P4
+
| rowspan="5" |T5
−
| rowspan="9" |VDD
+
| rowspan="5" |VDD
−
| rowspan="9" |I/O
+
| rowspan="5" |I/O
−
| rowspan="9" |
+
| rowspan="5" |TBD
−
|Pin AF1
+
|Pin ALT-0
−
|TIM2_CH1/TIM2_ETR
+
|TBD
 
|-
 
|-
−
|Pin AF3
+
|Pin ALT-1
−
|TIM8_CH1N
+
|TBD
 
|-
 
|-
−
|Pin AF4
+
|Pin ALT-2
−
|SAI4_CK1
+
|TBD
 
|-
 
|-
−
|Pin AF5
+
|Pin ALT-3
−
|SPI1_SCK/I2S1_CK
+
|TBD
 
|-
 
|-
−
|Pin AF8
+
|Pin ALT-5
−
|SPI6_SCK
+
|TBD
 
|-
 
|-
−
|Pin AF12
+
| rowspan="5" |J1.150
−
|SAI4_MCLK_A
+
| rowspan="5" |PE11
 +
| rowspan="5" |CPU.PE11
 +
| rowspan="5" |C1
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin AF14
+
|Pin ALT-1
−
|LCD_R4
+
|TBD
 
|-
 
|-
−
|Pin AF15
+
|Pin ALT-2
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
|Additional
+
|Pin ALT-3
−
functions
+
|TBD
−
|ADC1_INP19
 
−
 
 
−
ADC1_INN18
 
−
 
 
−
ADC2_INP19
 
−
 
 
−
ADC2_INN18
 
−
 
 
−
DAC_OUT2
 
 
|-
 
|-
−
| rowspan="8" |J1.168
+
|Pin ALT-5
−
| rowspan="8" |PC0
+
|TBD
−
| rowspan="8" |CPU.PC0
 
−
| rowspan="8" |T7
 
−
| rowspan="8" |VDD
 
−
| rowspan="8" |I/O
 
−
| rowspan="8" |
 
−
|Pin AF3
 
−
|DFSDM1_CKIN0
 
 
|-
 
|-
−
|Pin AF4
+
| rowspan="5" |J1.152
−
|LPTIM2_IN2
+
| rowspan="5" |PB10
 +
| rowspan="5" |CPU.PB10
 +
| rowspan="5" |W5
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin AF6
+
|Pin ALT-1
−
|DFSDM1_DATIN4
+
|TBD
 
|-
 
|-
−
|Pin AF8
+
|Pin ALT-2
−
|SAI2_FS_B
+
|TBD
 
|-
 
|-
−
|Pin AF10
+
|Pin ALT-3
−
|QUADSPI_BK2_NCS
+
|TBD
 
|-
 
|-
−
|Pin AF14
+
|Pin ALT-5
−
|LCD_R5
+
|TBD
 
|-
 
|-
−
|Pin AF15
+
| rowspan="5" |J1.154
−
|EVENTOUT
+
| rowspan="5" |PF11
 +
| rowspan="5" |CPU.PF11
 +
| rowspan="5" |U5
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Additional
+
|Pin ALT-1
−
functions
+
|TBD
−
|ADC1_INP10
 
−
 
 
−
ADC2_INP10
 
 
|-
 
|-
−
| rowspan="10" |J1.170
+
|Pin ALT-2
−
| rowspan="10" |PB1
+
|TBD
−
| rowspan="10" |CPU.PB1
 
−
| rowspan="10" |V3
 
−
| rowspan="10" |VDD
 
−
| rowspan="10" |I/O
 
−
| rowspan="10" |
 
−
|Pin AF1
 
−
|TIM1_CH3N
 
 
|-
 
|-
−
|Pin AF2
+
|Pin ALT-3
−
|TIM3_CH4
+
|TBD
 
|-
 
|-
−
|Pin AF3
+
|Pin ALT-5
−
|TIM8_CH3N
+
|TBD
 
|-
 
|-
−
|Pin AF6
+
| rowspan="5" |J1.156
−
|DFSDM1_DATIN1
+
| rowspan="5" |PC7
 +
| rowspan="5" |CPU.PC7
 +
| rowspan="5" |A9
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin AF9
+
|Pin ALT-1
−
|LCD_R6
+
|TBD
 
|-
 
|-
−
|Pin AF11
+
|Pin ALT-2
−
|ETH1_GMII_RXD3/
+
|TBD
−
 
 
−
ETH1_MII_RXD3/
 
−
 
 
−
ETH1_RGMII_RXD3
 
 
|-
 
|-
−
|Pin AF12
+
|Pin ALT-3
−
|MDIOS_MDC
+
|TBD
 
|-
 
|-
−
|Pin AF14
+
|Pin ALT-5
−
|LCD_G0
+
|TBD
 
|-
 
|-
−
|Pin AF15
+
| rowspan="5" |J1.158
−
|EVENTOUT
+
| rowspan="5" |PD3_OPT
 +
| rowspan="5" | -
 +
| rowspan="5" | -
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Additional
+
|Pin ALT-1
−
functions
+
|TBD
−
|ADC1_INP5
 
−
 
 
−
ADC2_INP5
 
 
|-
 
|-
−
| rowspan="9" |J1.172
+
|Pin ALT-2
−
| rowspan="9" |PE15
+
|TBD
−
| rowspan="9" |CPU.PE15
 
−
| rowspan="9" |E1
 
−
| rowspan="9" |VDD
 
−
| rowspan="9" |I/O
 
−
| rowspan="9" |
 
−
|Pin AF0
 
−
|HDP3
 
 
|-
 
|-
−
|Pin AF1
+
|Pin ALT-3
−
|TIM1_BKIN
+
|TBD
 
|-
 
|-
−
|Pin AF4
+
|Pin ALT-5
−
|TIM15_BKIN
+
|TBD
 
|-
 
|-
−
|Pin AF7
+
| rowspan="5" |J1.160
−
|USART2_CTS/USART2_NSS
+
| rowspan="5" |PC10
 +
| rowspan="5" |CPU.PC10
 +
| rowspan="5" |D11
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin AF8
+
|Pin ALT-1
−
|UART8_CTS
+
|TBD
 
|-
 
|-
−
|Pin AF10
+
|Pin ALT-2
−
|FMC_NCE2
+
|TBD
 
|-
 
|-
−
|Pin AF12
+
|Pin ALT-3
−
|FMC_AD12/FMC_D12
+
|TBD
 
|-
 
|-
−
|Pin AF14
+
|Pin ALT-5
−
|LCD_R7
+
|TBD
 
|-
 
|-
−
|Pin AF15
+
| rowspan="5" |J1.162
−
|EVENTOUT
+
| rowspan="5" |PB0
−
|-
+
| rowspan="5" |CPU.PB0
−
|J1.174
+
| rowspan="5" |W3
−
 
+
| rowspan="5" |VDD
−
(eMMC 8-bit
+
| rowspan="5" |I/O
−
 
+
| rowspan="5" |TBD
−
on board)
+
|Pin ALT-0
−
|PE4_OPT
+
|TBD
−
|CPU.PE4
 
−
|B11
 
−
|VDD
 
−
|I/O
 
−
|internally used for eMMC,
 
−
do not connect
 
−
|
 
−
|
 
−
|-
 
−
| rowspan="14" |J1.174
 
−
| rowspan="14" |PE4_OPT
 
−
| rowspan="14" | CPU.PE4
 
−
| rowspan="14" | B11
 
−
| rowspan="14" |VDD
 
−
| rowspan="14" |I/O
 
−
| rowspan="14" |
 
−
|Pin AF0
 
−
|TRACED1
 
 
|-
 
|-
−
|Pin AF2
+
|Pin ALT-1
−
|SAI1_D2
+
|TBD
 
|-
 
|-
−
|Pin AF3
+
|Pin ALT-2
−
|DFSDM1_DATIN3
+
|TBD
 
|-
 
|-
−
|Pin AF4
+
|Pin ALT-3
−
|TIM15_CH1N
+
|TBD
 
|-
 
|-
−
|Pin AF5
+
|Pin ALT-5
−
|SPI4_NSS
+
|TBD
 
|-
 
|-
−
|Pin AF6
+
|J1.164
−
|SAI1_FS_A
+
|DGND
 +
|DGND
 +
| -
 +
| -
 +
|G
 +
|
 +
|
 +
|
 
|-
 
|-
−
|Pin AF7
+
| rowspan="5" |J1.166
−
|SDMMC2_CKIN
+
| rowspan="5" |PA5
 +
| rowspan="5" |CPU.PA5
 +
| rowspan="5" |P4
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin AF8
+
|Pin ALT-1
−
|SDMMC1_CKIN
+
|TBD
 
|-
 
|-
−
|Pin AF9
+
|Pin ALT-2
−
|SDMMC2_D4
+
|TBD
 
|-
 
|-
−
|Pin AF11
+
|Pin ALT-3
−
|SDMMC1_D4
+
|TBD
 
|-
 
|-
−
|Pin AF12
+
|Pin ALT-5
−
|FMC_A20
+
|TBD
 
|-
 
|-
−
|Pin AF13
+
| rowspan="5" |J1.168
−
|DCMI_D4
+
| rowspan="5" |PC0
 +
| rowspan="5" |CPU.PC0
 +
| rowspan="5" |T7
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin AF14
+
|Pin ALT-1
−
|LCD_B0
+
|TBD
 
|-
 
|-
−
|Pin AF15
+
|Pin ALT-2
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
| rowspan="9" |J1.176
+
|Pin ALT-3
−
| rowspan="9" |PA10
+
|TBD
−
| rowspan="9" |CPU.PA10
 
−
| rowspan="9" |T16
 
−
| rowspan="9" |VDD
 
−
| rowspan="9" |I/O
 
−
| rowspan="9" |
 
−
|Pin AF1
 
−
|TIM1_CH3
 
 
|-
 
|-
−
|Pin AF5
+
|Pin ALT-5
−
|SPI3_NSS/I2S3_WS
+
|TBD
 
|-
 
|-
−
|Pin AF7
+
| rowspan="5" |J1.170
−
|USART1_RX
+
| rowspan="5" |PB1
 +
| rowspan="5" |CPU.PB1
 +
| rowspan="5" |V3
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin AF11
+
|Pin ALT-1
−
|MDIOS_MDIO
+
|TBD
 
|-
 
|-
−
|Pin AF12
+
|Pin ALT-2
−
|SAI4_FS_B
+
|TBD
 
|-
 
|-
−
|Pin AF13
+
|Pin ALT-3
−
|DCMI_D1
+
|TBD
 
|-
 
|-
−
|Pin AF14
+
|Pin ALT-5
−
|LCD_B1
+
|TBD
 
|-
 
|-
−
|Pin AF15
+
| rowspan="5" |J1.172
−
|EVENTOUT
+
| rowspan="5" |PE15
 +
| rowspan="5" |CPU.PE15
 +
| rowspan="5" |E1
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Additional
+
|Pin ALT-1
−
functions
+
|TBD
−
|OTG_FS_ID
 
−
 
 
−
OTG_HS_ID
 
 
|-
 
|-
−
| rowspan="14" |J1.178
+
|Pin ALT-2
−
| rowspan="14" |PE5
+
|TBD
−
| rowspan="14" |CPU.PE5
 
−
| rowspan="14" |B7
 
−
| rowspan="14" |VDD
 
−
| rowspan="14" |I/O
 
−
| rowspan="14" |
 
−
|Pin AF0
 
−
|TRACED3
 
 
|-
 
|-
−
|Pin AF2
+
|Pin ALT-3
−
|SAI1_CK2
+
|TBD
 
|-
 
|-
−
|Pin AF3
+
|Pin ALT-5
−
|DFSDM1_CKIN3
+
|TBD
 
|-
 
|-
−
|Pin AF4
+
| rowspan="5" |J1.174
−
|TIM15_CH1
+
| rowspan="5" |PE4_OPT
 +
| rowspan="5" | -
 +
| rowspan="5" | -
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin AF5
+
|Pin ALT-1
−
|SPI4_MISO
+
|TBD
 
|-
 
|-
−
|Pin AF6
+
|Pin ALT-2
−
|SAI1_SCK_A
+
|TBD
 
|-
 
|-
−
|Pin AF7
+
|Pin ALT-3
−
|SDMMC2_D0DIR
+
|TBD
 
|-
 
|-
−
|Pin AF8
+
|Pin ALT-5
−
|SDMMC1_D0DIR
+
|TBD
 
|-
 
|-
−
|Pin AF9
+
| rowspan="5" |J1.176
−
|SDMMC2_D6
+
| rowspan="5" |PA10
 +
| rowspan="5" |CPU.PA10
 +
| rowspan="5" |T16
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin AF11
+
|Pin ALT-1
−
|SDMMC1_D6
+
|TBD
 
|-
 
|-
−
|Pin AF12
+
|Pin ALT-2
−
|FMC_A21
+
|TBD
 
|-
 
|-
−
|Pin AF13
+
|Pin ALT-3
−
|DCMI_D6
+
|TBD
 
|-
 
|-
−
|Pin AF14
+
|Pin ALT-5
−
|LCD_G0
+
|TBD
 
|-
 
|-
−
|Pin AF15
+
| rowspan="5" |J1.178
−
|EVENTOUT
+
| rowspan="5" |PE5
−
|-
+
| rowspan="5" |CPU.PE5
−
| rowspan="13" |J1.180
+
| rowspan="5" |B7
−
| rowspan="13" |PE6_OPT
+
| rowspan="5" |VDD
−
| rowspan="13" | CPU.PE6
+
| rowspan="5" |I/O
−
| rowspan="13" | B3
+
| rowspan="5" |TBD
−
| rowspan="13" |VDD
+
|Pin ALT-0
−
| rowspan="13" |I/O
+
|TBD
−
| rowspan="13" |for SDMMC1_D2 function
 
−
use pin J1.79
 
−
 
 
−
(SDMMC lenght match)
 
−
|Pin AF0
 
−
|TRACED2
 
 
|-
 
|-
−
|Pin AF1
+
|Pin ALT-1
−
|TIM1_BKIN2
+
|TBD
 
|-
 
|-
−
|Pin AF2
+
|Pin ALT-2
−
|SAI1_D1
+
|TBD
 
|-
 
|-
−
|Pin AF4
+
|Pin ALT-3
−
|TIM15_CH2
+
|TBD
 
|-
 
|-
−
|Pin AF5
+
|Pin ALT-5
−
|SPI4_MOSI
+
|TBD
 
|-
 
|-
−
|Pin AF6
+
| rowspan="5" |J1.180
−
|SAI1_SD_A
+
| rowspan="5" |PE6_OPT
 +
| rowspan="5" | -
 +
| rowspan="5" | -
 +
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin AF7
+
|Pin ALT-1
−
|SDMMC2_D0
+
|TBD
 
|-
 
|-
−
|<s>Pin AF8</s>
+
|Pin ALT-2
−
|<s>SDMMC1_D2</s>
+
|TBD
 
|-
 
|-
−
|Pin AF10
+
|Pin ALT-3
−
|SAI2_MCLK_B
+
|TBD
 
|-
 
|-
−
|Pin AF12
+
|Pin ALT-5
−
|FMC_A22
+
|TBD
 
|-
 
|-
−
|Pin AF13
+
| rowspan="5" |J1.182
−
|DCMI_D7
+
| rowspan="5" |PG13
−
|-
+
| rowspan="5" |CPU.PG13
−
|Pin AF14
+
| rowspan="5" |U2
−
|LCD_G1
+
| rowspan="5" |VDD
 +
| rowspan="5" |I/O
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin AF15
+
|Pin ALT-1
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
| rowspan="12" |J1.182
+
|Pin ALT-2
−
| rowspan="12" |PG13
+
|TBD
−
| rowspan="12" |CPU.PG13
 
−
| rowspan="12" |U2
 
−
| rowspan="12" |VDD
 
−
| rowspan="12" |I/O
 
−
| rowspan="12" |
 
−
|Pin AF0
 
−
|TRACED0
 
 
|-
 
|-
−
|Pin AF1
+
|Pin ALT-3
−
|LPTIM1_OUT
+
|TBD
 
|-
 
|-
−
|Pin AF2
+
|Pin ALT-5
−
|SAI1_CK2
+
|TBD
 
|-
 
|-
−
|Pin AF4
+
| rowspan="5" |J1.184
−
|SAI4_CK1
+
| rowspan="5" |PA15_OPT
−
|-
+
| rowspan="5" | -
−
|Pin AF5
+
| rowspan="5" | -
−
|SPI6_SCK
+
| rowspan="5" |VDD
−
|-
+
| rowspan="5" |I/O
−
|Pin AF6
+
| rowspan="5" |TBD
−
|SAI1_SCK_A
+
|Pin ALT-0
−
|-
+
|TBD
−
|Pin AF7
 
−
|USART6_CTS/USART6_NSS
 
−
|-
 
−
|Pin AF10
 
−
|SAI4_MCLK_A
 
−
|-
 
−
|Pin AF11
 
−
|ETH1_GMII_TXD0/
 
−
 
 
−
ETH1_MII_TXD0/
 
−
 
 
−
ETH1_RGMII_TXD0/
 
−
 
 
−
ETH1_RMII_TXD0
 
−
|-
 
−
|Pin AF12
 
−
|FMC_A24
 
−
|-
 
−
|Pin AF14
 
−
|LCD_R0
 
−
|-
 
−
|Pin AF15
 
−
|EVENTOUT
 
−
|-
 
−
|J1.184
 
−
 
 
−
(eMMC 8-bit
 
−
 
 
−
on board)
 
−
|PA15_OPT
 
−
|CPU.PA15
 
−
|C7
 
−
|VDD
 
−
|I/O
 
−
|internally used for eMMC,
 
−
do not connect
 
−
|
 
−
|
 
−
|-
 
−
| rowspan="16" |J1.184
 
−
| rowspan="16" |PA15_OPT
 
−
| rowspan="16" | CPU.PA15
 
−
| rowspan="16" | C7
 
−
| rowspan="16" |VDD
 
−
| rowspan="16" |I/O
 
−
| rowspan="16" |
 
−
|Pin AF0
 
−
|DBTRGI
 
 
|-
 
|-
−
|Pin AF1
+
|Pin ALT-1
−
|TIM2_CH1/TIM2_ETR
+
|TBD
 
|-
 
|-
−
|Pin AF2
+
|Pin ALT-2
−
|SAI4_D2
+
|TBD
−
|-
 
−
|Pin AF3
 
−
|SDMMC1_CDIR
 
−
|-
 
−
|Pin AF4
 
−
|CEC
 
−
|-
 
−
|Pin AF5
 
−
|SPI1_NSS/I2S1_WS
 
 
|-
 
|-
−
|Pin AF6
+
|Pin ALT-3
−
|SPI3_NSS/I2S3_WS
+
|TBD
 
|-
 
|-
−
|Pin AF7
+
|Pin ALT-5
−
|SPI6_NSS
+
|TBD
 
|-
 
|-
−
|Pin AF8
+
| rowspan="5" |J1.186
−
|UART4_RTS/UART4_DE
+
| rowspan="5" |VBUS_OTG_IN
 +
| rowspan="5" |CPU.OTG_VBUS
 +
| rowspan="5" |U15
 +
| rowspan="5" |VBUS_OTG_IN
 +
| rowspan="5" |S
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin AF9
+
|Pin ALT-1
−
|SDMMC2_D5
+
|TBD
 
|-
 
|-
−
|Pin AF10
+
|Pin ALT-2
−
|SDMMC2_CDIR
+
|TBD
 
|-
 
|-
−
|Pin AF11
+
|Pin ALT-3
−
|SDMMC1_D5
+
|TBD
 
|-
 
|-
−
|Pin AF12
+
|Pin ALT-5
−
|SAI4_FS_A
+
|TBD
 
|-
 
|-
−
|Pin AF13
+
| rowspan="5" |J1.188
−
|UART7_TX
+
| rowspan="5" |VBUS_SW
 +
| rowspan="5" |PMIC.SWOUT
 +
| rowspan="5" |38
 +
| rowspan="5" |VBUS_SW
 +
| rowspan="5" |S
 +
| rowspan="5" |TBD
 +
|Pin ALT-0
 +
|TBD
 
|-
 
|-
−
|Pin AF14
+
|Pin ALT-1
−
|LCD_R1
+
|TBD
 
|-
 
|-
−
|Pin AF15
+
|Pin ALT-2
−
|EVENTOUT
+
|TBD
 
|-
 
|-
−
|J1.186
+
|Pin ALT-3
−
|VBUS_OTG_IN
+
|TBD
−
|CPU.OTG_VBUS
 
−
|U15
 
−
|VBUS_OTG_IN
 
−
|S
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
−
|J1.188
+
|Pin ALT-5
−
|VBUS_SW
+
|TBD
−
|PMIC.SWOUT
 
−
|38
 
−
|VBUS_SW
 
−
|S
 
−
|
 
−
|
 
−
|
 
 
|-
 
|-
 
|J1.190
 
|J1.190
Line 4,913: Line 4,823:
 
----
 
----
  
−
[[Category:ETRA]]
+
[[Category:{{{nome-som}}}]]

Revision as of 17:19, 28 December 2020

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TBD: modificare la tabella seguente con le caratteristiche dei pin del SOM

TBD: modificare le due tabelle ODD e EVEN con la mappa completa dei pins

TBD: nella tabella naming conventions, inserire il codice dei vari IC presenti (PMIC, PHY ETH, ecc.)

Connectors and Pinout Table[edit | edit source]

Connectors description[edit | edit source]

In the following table are described all available connectors integrated on ETRA:

Connector name Connector Type Notes Carrier board counterpart
J1 SODIMM DDR3 edge connector 204 pin TE Connectivity 2-2013289-1

The dedicated carrier board must mount the mating connector and connect the desired peripheral interfaces according to ETRA pinout specifications. See the images below for reference:

File:ETRA-top.png
ETRA TOP view
File:ETRA-bottom.png
ETRA BOTTOM view

Pinout table naming conventions[edit | edit source]

This chapter contains the pinout description of the ETRA module, grouped in two tables (odd and even pins) that report the pin mapping of the TBD: connector type ETRA connector.

Each row in the pinout tables contains the following information:

Pin Reference to the connector pin
Pin Name Pin (signal) name on the ETRA connectors
Internal
connections 		Connections to the ETRA components
  • CPU.<x> : pin connected to CPU pad named <x>
  • PMIC.<x> : pin connected to the Power Manager IC STPMIC1APQR
  • LAN.<x> : pin connected to the LAN PHY KSZ8091RNAIA
  • NOR.<x>: pin connected to the flash NOR
  • NAND.<x>: pin connected to the flash NAND
  • eMMC.<x>: pin connected to the flash eMMC
  • EXP.<x>: pin connected to the I/O EXPANDER ADP5589ACPZ
Ball/pin # Component ball/pin number connected to signal
Voltage I/O voltage levels
Type Pin type:
  • I = Input
  • O = Output
  • D = Differential
  • Z = High impedance
  • S = Power supply voltage
  • G = Ground
  • A = Analog signal
Notes Remarks on special pin characteristics
Pin MUX alternative functions Muxes:
  • Pin ALT-0
  • ...
  • Pin ALT-N

The number of functions depends on platform

Pinout Table ODD pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage domain Type Notes Alternative Functions
J1.1 DGND DGND - - G
J1.3 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.5 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.7 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.9 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.11 DGND DGND - - G
J1.13 ETH_LED LAN.LED0/PME_N1 23 VDD I/O
J1.15 - NC - - -
J1.17 DGND DGND - - G
J1.19 ETH_TX_P LAN.TXP 6 - D
J1.21 ETH_TX_M LAN.TXM 5 - D
J1.23 ETH_RX_P LAN.RXP 4 - D
J1.25 ETH_RX_M LAN.RXM 3 - D
J1.27 LDO2 PMIC.LDO2OUT 18 LDO2 S Spare LDO output
J1.29 LDO5 PMIC.LDO5OUT 20 LDO5 S Spare LDO output
J1.31 - NC - - -
J1.33 - NC - - -
J1.35 DGND DGND - - G
J1.37 PD1 CPU.PD1 A4 VDD I/O Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.39 PD4 CPU.PD4 D6 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.41 PD5 CPU.PD5 D7 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.43 PD7 CPU.PD7 B4 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.45 PD0 CPU.PD0 A3 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.47 PG15 CPU.PG15 A2 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.49 PF10 CPU.PF10 U9 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.51 PE7 CPU.PE7 T10 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.53 PE8 CPU.PE8 T11 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.55 - NC - - -
J1.57 DGND DGND - - G
J1.59 - NC - - -
J1.61 PB14 CPU.PB14 C9 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.63 PB15 CPU.PB15 A8 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.65 PB3 CPU.PB3 A7 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.67 PB4 CPU.PB4 B9 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.69 PG6 CPU.PG6 A6 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.71 PE3 CPU.PE3 A5 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.73 DGND DGND - - G
J1.75 PC8 CPU.PC8 C11 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.77 PC9 CPU.PC9 A10 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.79 PE6 CPU.PE6 B3 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.81 PC11 CPU.PC11 A11 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.83 PD2 CPU.PD2 B10 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.85 PC12 CPU.PC12 C10 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.87 DGND DGND - - G
J1.89 PD8 CPU.PD8 F2 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.91 PD9 CPU.PD9 G3 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.93 PC2 CPU.PC2 T2 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.95 PA0 CPU.PA0 R3 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.97 PD13 CPU.PD13 U12 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.99 PD12 CPU.PD12 U11 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.101 PD11 CPU.PD11 V8 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.103 - NC - - -
J1.105 PG9 CPU.PG9 T14 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.107 - NC - - -
J1.109 DGND DGND - - G
J1.111 DSI_CKN CPU.DSI_CKN A14 - D
J1.113 DSI_CKP CPU.DSI_CKP B14 - D
J1.115 DSI_D0N CPU.DSI_D0N A13 - D
J1.117 DSI_D0P DSI_D0P B13 - D
J1.119 DSI_D1N CPU.DSI_D1N A15 - D
J1.121 DSI_D1P CPU.DSI_D1P B15 - D
J1.123 - NC - - -
J1.125 - NC - - -
J1.127 - NC - - -
J1.129 - NC - - -
J1.131 DGND DGND - - G
J1.133 ADP5589_R7 EXP.R7 1 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF5 TBD
J1.135 ADP5589_R6 EXP.R6 2 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF5 TBD
J1.137 ADP5589_R5 EXP.R5 3 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF5 TBD
J1.139 ADP5589_R4 EXP.R4 4 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF5 TBD
J1.141 ADP5589_R3 EXP.R3 5 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF5 TBD
J1.143 ADP5589_R2 EXP.R2 6 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF5 TBD
J1.145 ADP5589_R1 EXP.R1 7 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF5 TBD
J1.147 ADP5589_R0 EXP.R0 8 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF5 TBD
J1.149 ADP5589_C0 EXP.C0 9 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF5 TBD
J1.151 ADP5589_C1 EXP.C1 10 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF5 TBD
J1.153 DGND DGND - - G
J1.155 ADP5589_C2 EXP.C2 11 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF5 TBD
J1.157 ADP5589_C3 EXP.C3 12 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF5 TBD
J1.159 ADP5589_C4 EXP.C4 13 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF5 TBD
J1.161 ADP5589_C5 EXP.C5 14 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF5 TBD
J1.163 ADP5589_C6 EXP.C6 15 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF5 TBD
J1.165 ADP5589_C7 EXP.C7 16 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF5 TBD
J1.167 ADP5589_C8 EXP.C8 19 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF5 TBD
J1.169 ADP5589_C9 EXP.C9 20 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF5 TBD
J1.171 ADP5589_C10 EXP.C10 21 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF5 TBD
J1.173 - NC - - -
J1.175 DGND DGND - - G
J1.177 PE9 CPU.PE9 W7 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.179 PC3 CPU.PC3 T3 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.181 PD6 CPU.PD6 E3 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.183 PE10 CPU.PE10 V10 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.185 VBUS_OTG_OUT PMIC.VBUSOTG 35 VBUSOTG S USB OTG VOUT
J1.187 PG11 CPU.PG11 V6 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.189 PB2 CPU.PB2 T13 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.191 PE1 CPU.PE1 B1 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.193 PE0 CPU.PE0 C4 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.195 PE2 CPU.PE2 T1 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.197 PA13 CPU.PA13 P2 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.199 PD14 CPU.PD14 F3 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.201 PD15 CPU.PD15 G1 VDD I/O TBD Pin AF0 TBD
Pin AF1 TBD
Pin AF2 TBD
Pin AF3 TBD
Pin AF4 TBD
Pin AF5 TBD
Pin AF6 TBD
Pin AF7 TBD
Pin AF8 TBD
Pin AF9 TBD
Pin AF10 TBD
Pin AF11 TBD
Pin AF12 TBD
Pin AF13 TBD
Pin AF14 TBD
Pin AF15 TBD
J1.203 DGND DGND - - G

Pinout Table EVEN pins declaration[edit | edit source]

Pin Pin Name Internal Connections Ball/pin # Voltage domain Type Notes Alternative Functions
J1.2 DGND DGND - - G
J1.4 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.6 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.8 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.10 3.3VIN INPUT VOLTAGE - 3.3VIN S
J1.12 DGND DGND - - G
J1.14 VBAT CPU.VBAT H3 VBAT S BACKUP VOLTAGE
J1.16 PONKEYn PMIC.PONKEYN 17 3.3VIN I
J1.18 SOM_PGOOD - - VDD O
J1.20 BOOT_MODE0 CPU.BOOT0 K1 VDD I internall pull-up or pull-down

according to specific model

J1.22 PWR_ON CPU.PWR_ON L1 VDD O
J1.24 NRST CPU.NRST

PMIC.RSTN

eMMC.RST_n

NOR.NRESET

J1

1

K5

A4

VDD I/O TBD
J1.26 BOOT_MODE1 CPU.BOOT1 K4 VDD I internall pull-up or pull-down

according to specific model

J1.28 PA9 CPU.PA9 C8 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.30 DGND DGND - - G
J1.32 WAKEUP PMIC.WAKEUP 2 VINTLDO I
J1.34 PB13 CPU.PB13 T9 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.36 BOOT_MODE2 CPU-BOOT2 L2 VDD I internall pull-up or pull-down

according to specific model

J1.38 PA11 CPU.PA11 V17 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.40 MEM_WP# NAND.NWP

NOR.NWP

19

C4

VDD I internal pull-up to VDD
J1.42 PB6 CPU.PB6 T12 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.44 PB7 CPU.PB7 B5 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.46 PE14 CPU.PE14 D3 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.48 PA12 CPU.PA12 U16 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.50 BST_OUT PMIC.BST_OUT 34 BST_OUT S BOOST OUTPUT
J1.52 BST_OUT PMIC.BST_OUT 34 BST_OUT S BOOST OUTPUT
J1.54 PMIC_INT# PMIC-INTN 43 VDD O
J1.56 DGND DGND - - G
J1.58 PA14 CPU.PA14 R1 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.60 VDD VOLTAGE OUTPUT - VDD S
J1.62 VDD VOLTAGE OUTPUT - VDD S
J1.64 1V8 PMIC.LDO6OUT 21 1V8 S Spare LDO output
J1.66 PG12 CPU.PG12 F1 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.68 PB5 CPU.PB5 T8 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.70 PG8 CPU.PG8 U7 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.72 PA8 CPU.PA8 B8 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.74 PF7 CPU.PF7 W8 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.76 PF9 CPU.PF9 W9 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.78 PF8 CPU.PF8 U10 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.80 PF6 CPU.PF6 V9 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.82 DGND DGND - - G
J1.84 PMIC_3V3 VOLTAGE OUTPUT - PMIC_3V3 S
J1.86 PMIC_3V3 VOLTAGE OUTPUT - PMIC_3V3 S
J1.88 PMIC_3V3 VOLTAGE OUTPUT - PMIC_3V3 S
J1.90 JTMS-SWDIO CPU.JTMS-SWDIO D15 VDD I/O TBD
J1.92 JTDI CPU.JTDI D13 VDD I/O TBD
J1.94 NJTRST CPU.NJTRST D12 VDD I/O TBD
J1.96 JTDO-TRACESWOO CPU.JTDO-TRACESWOO D14 VDD I/O TBD
J1.98 JTCK-SWCLK CPU.JTCK-SWCLK D16 VDD I/O TBD
J1.100 DGND DGND - - G
J1.102 NRST_CORE CPU.NRST_CORE J2 VDD I internally connected to NRST
J1.104 PDR_ON CPU.PDR_ON N2 VDD I
J1.106 PDR_ON_CORE CPU.PDR_ON_CORE N1 VDD I
J1.108 PWR_LP CPU.PWR_LP P1 VDD O
J1.110 - NC - - -
J1.112 - NC - - -
J1.114 - NC - - -
J1.116 - NC - - -
J1.118 - NC - - -
J1.120 - NC - - -
J1.122 DGND DGND - - G
J1.124 PE13 CPU.PE13 C2 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.126 PC13 CPU.PC13 K3 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.128 PA4 CPU.PA4 R4 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.130 PC6_OPT - - VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.132 PG7 CPU.PG7 W10 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.134 PG10 CPU.PG10 V7 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.136 PD10 CPU.PD10 C5 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.138 PE12 CPU.PE12 D2 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.140 PA3 CPU.PA3 P3 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.142 PB8 CPU.PB8 W6 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.144 PB9 CPU.PB9 D9 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.146 DGND DGND - - G
J1.148 PA6 CPU.PA6 T5 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.150 PE11 CPU.PE11 C1 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.152 PB10 CPU.PB10 W5 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.154 PF11 CPU.PF11 U5 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.156 PC7 CPU.PC7 A9 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.158 PD3_OPT - - VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.160 PC10 CPU.PC10 D11 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.162 PB0 CPU.PB0 W3 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.164 DGND DGND - - G
J1.166 PA5 CPU.PA5 P4 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.168 PC0 CPU.PC0 T7 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.170 PB1 CPU.PB1 V3 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.172 PE15 CPU.PE15 E1 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.174 PE4_OPT - - VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.176 PA10 CPU.PA10 T16 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.178 PE5 CPU.PE5 B7 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.180 PE6_OPT - - VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.182 PG13 CPU.PG13 U2 VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.184 PA15_OPT - - VDD I/O TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.186 VBUS_OTG_IN CPU.OTG_VBUS U15 VBUS_OTG_IN S TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.188 VBUS_SW PMIC.SWOUT 38 VBUS_SW S TBD Pin ALT-0 TBD
Pin ALT-1 TBD
Pin ALT-2 TBD
Pin ALT-3 TBD
Pin ALT-5 TBD
J1.190 DGND DGND - - G
J1.192 - NC - - -
J1.194 - NC - - -
J1.196 USB_DM2 CPU.USB_DM2 V13 - D
J1.198 USB_DP2 CPU.USB_DP2 W13 - D
J1.200 USB_DP1 CPU.USB_DP1 V14 - D
J1.202 USB_DM1 CPU.USB_DM1 W14 - D
J1.204 DGND DGND - - G

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